SGLS202A − OCTOBER 2003 – REVISED OCTOBER 2006
D Qualification in Accordance With
D
D
D
D
D Available in Standard-Pinout Small-Outline
AEC-Q100†
Qualified for Automotive Applications
Customer-Specific Configuration Control
Can Be Supported Along With
Major-Change Approval
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Outstanding Combination of DC Precision
and AC Performance:
Unity-Gain Bandwidth . . . 15 MHz Typ
Vn . . . . 3.3 nV/√Hz at f = 10 Hz Typ,
2.5 nV/√Hz at f = 1 kHz Typ
VIO . . . . 25 µV Max
AVD . . . 45 V/µV Typ With RL = 2 kΩ,
19 V/µV Typ With RL = 600 Ω
D
D
Package
Output Features Saturation Recovery
Circuitry
Macromodels and Statistical information
D PACKAGE
(TOP VIEW)
OFFSET N1
IN −
IN +
VCC −
1
8
2
7
3
6
4
5
OFFSET N2
VCC +
OUT
NC
† Contact factory for details. Q100 qualification data available on
request.
description
The TLE20x7 and TLE20x7A contain innovative circuit design expertise and high-quality process control
techniques to produce a level of ac performance and dc precision previously unavailable in single operational
amplifiers. Manufactured using Texas Instruments state-of-the-art Excalibur process, these devices allow
upgrades to systems that use lower-precision devices.
In the area of dc precision, the TLE20x7 and TLE20x7A offer maximum offset voltages of 100 µV and 25 µV,
respectively, common-mode rejection ratio of 131 dB (typ), supply voltage rejection ratio of 144 dB (typ), and
dc gain of 45 V/µV (typ).
The ac performance of the TLE2027 and TLE2037 is highlighted by a typical unity-gain bandwidth specification
of 15 MHz, 55° of phase margin, and noise voltage specifications of 3.3 nV/√Hz and 2.5 nV/√Hz at frequencies
of 10 Hz and 1 kHz, respectively. The TLE2037 and TLE2037A have been decompensated for faster slew rate
(−7.5 V/µs, typical) and wider bandwidth (50 MHz). To ensure stability, the TLE2037 and TLE2037A should be
operated with a closed-loop gain of 5 or greater.
ORDERING INFORMATION
TA
VIOmax
AT 25°C
ORDERABLE
PART NUMBER
PACKAGE‡
25 µV
V
SOIC (D)
Tape and reel
100 µV
V
SOIC (D)
Tape and reel
−40°C to 125°C
TOP-SIDE
MARKING
TLE2027AQDRQ1
2027AQ
TLE2037AQDRQ1
2037AQ
TLE2027QDRQ1
2027Q1
TLE2037QDRQ1
2037Q1
‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available
at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2006 Texas Instruments Incorporated
!"#$%&" ' ()##*& %' "! +),-(%&" .%&*/
#".)(&' ("!"#$ &" '+*(!(%&"' +*# &0* &*#$' "! *1%' '&#)$*&'
'&%.%#. 2%##%&3/ #".)(&" +#"(*''4 ."*' "& *(*''%#-3 (-).*
&*'&4 "! %-- +%#%$*&*#'/
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SGLS202A − OCTOBER 2003 – REVISED OCTOBER 2006
description (continued)
Both the TLE20x7 and TLE20x7A are available in a wide variety of packages, including the industry-standard
8-pin small-outline version for high-density system applications. The Q-suffix devices are characterized for
operation from −40°C to 125°C.
symbol
OFFSET N1
IN +
+
OUT
IN −
−
OFFSET N2
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
IN −
IN +
Q1
Q3
Q2
Q4
OFFSET N1
OFFSET N2
Q6
Q5
Q7
Q8
Q9
equivalent schematic
Q11
R1
Q10
R2
R3
Q16
Q15
Q12
Q14
Q18
Q17
Q13
R5
R4
Q20
C1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
R12
Q29
Q30
Q34
C3
Q33
R14
Q31
R13
Q32
R18
C4
R17
R16
Q37
61
26
1
4
Resistors
epiFET
Capacitors
TLE2027
Transistors
Q38
VCC −
Q35
Q36
R15
4
1
26
61
TLE2037
ACTUAL DEVICE COMPONENT COUNT
R7 R10
Q26
C2
COMPONENT
R6
Q22
Q21
R11
Q25 Q28
Q23 Q24
Q19
R8
Q27
R9
V CC+
R19
Q40
Q41
Q39
R20
Q46
Q45
Q47
Q44
R22
Q43
R21
Q42
R23
R25
Q54
Q57
Q56
Q55
Q60
Q59
Q58
R24 R26
Q52
Q53
Q50
Q51
Q48
Q49
Q62
OUT
Q61
5
5
5
55
55
SGLS202A − OCTOBER 2003 − REVISED OCTOBER 2006
3
SGLS202A − OCTOBER 2003 – REVISED OCTOBER 2006
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC+ (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 V
Supply voltage, VCC − . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −19 V
Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1.2 V
Input voltage range, VI (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC±
Input current, II (each Input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1 mA
Output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Total current into VCC+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Total current out of VCC − . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Duration of short-circuit current at (or below) 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited
Junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142°C
Operating free-air temperature range, TA: Q suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 65°C to 150°C
Package thermal impedance, θJA (D Package) (0 LFPM) (see Note 4) . . . . . . . . . . . . . . . . . . . . . . 101°C/W
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D package . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to the midpoint between VCC + and VCC − .
2. Differential voltages are at IN+ with respect to IN −. Excessive current flows if a differential input voltage in excess of approximately
±1.2 V is applied between the inputs, unless some limiting resistance is used.
3. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum
dissipation rating is not exceeded.
4. The thermal impedance is calculated in accordance with JESD 51−7.
recommended operating conditions
Supply voltage, VCC ±
TA = 25°C
TA = Full range‡
Common-mode input voltage, VIC
Operating free-air temperature, TA
‡ Full range is −40°C to 125°C for Q-suffix devices.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MIN
MAX
UNIT
V
±4
±19
−11
11
−10.2
10.2
−40
125
V
°C
SGLS202A − OCTOBER 2003 – REVISED OCTOBER 2006
TLE20x7-Q1 electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless
otherwise noted)
PARAMETER
TA†
TEST CONDITIONS
TLE20x7-Q1
MIN
MAX
20
100
25°C
VIO
Input offset voltage
αVIO
Temperature coefficient of
input offset voltage
Input offset voltage
long-term drift (see Note 4)
IIO
Input offset current
IIB
Input bias current
Full range
RS = 50 Ω
VOM +
Maximum positive peak
output voltage swing
µV/°C
25°C
0.006
1
0.006
1
µV/mo
25°C
6
90
6
90
RS = 50 Ω
150
Maximum negative peak
VOM −
output voltage swing
AVD
Large-signal differential
voltage amplification
10
25°C
12
RL = 2 kΩ
Full range
−11
VO = ± 11 V, RL = 2 kΩ
VO = ± 10 V, RL = 2 kΩ
Full range
2.5
25°C
3.5
Full range
1.8
Open-loop output
impedance
IO = 0
CMRR
Common-mode rejection
ratio
VIC = VICRmin,
RS = 50 Ω
25°C
10.5
nA
−13
to
13
V
12.9
10
13.2
12
−13
−10.5
V
13.2
11
−13
−10
−13.5
2
−12
V
−13.5
−11
45
10
45
3.5
38
8
38
V/µV
2.2
19
5
19
25°C
8
8
pF
25°C
50
50
Ω
25°C
100
96
VCC ± = ± 4 V to ± 18 V,
RS = 50 Ω
25°C
94
VCC ± = ± 4 V to ± 18 V,
RS = 50 Ω
Full range
90
No load
12.9
nA
90
150
−10.4
to
10.4
5
Full range
VO = 0,
15
−11
to
11
11
−12
VO = ± 10 V, RL = 1 kΩ
90
−13
to
13
−10.5
25°C
zo
Supply current
10.5
−10
Ci
ICC
25°C
Full range
Input capacitance
Supply-voltage rejection
ratio (∆VCC ± /∆V
/ VIO)
−11
to
11
Full range
25°C
150
150
Full range
25°C
VO = ± 10 V, RL = 600 Ω
kSVR
15
−10.3
to
10.3
Full range
RL = 600 Ω
µV
V
1
Full range
RL = 2 kΩ
25
105
UNIT
0.2
Full range
RL = 600 Ω
10
MAX
1
25°C
Common-mode input
voltage range
TYP
0.4
25°C
VICR
MIN
200
Full range
VIC = 0,
TLE20x7A-Q1
TYP
131
117
131
dB
113
144
110
144
dB
25°C
Full range
105
3.8
5.3
5.6
3.8
5.3
5.6
mA
† Full range is −40°C to 125°C.
NOTE 4: Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SGLS202A − OCTOBER 2003 – REVISED OCTOBER 2006
TLE20x7-Q1 operating characteristics at specified free-air temperature, VCC ± = ±15 V, TA = 25°C
(unless otherwise specified)
TLE20x7-Q1
PARAMETER
SR
Slew rate at unity gain
Vn
Equivalent input noise
voltage (see Figure 2)
VN(PP)
Peak-to-peak equivalent
input noise voltage
In
Equivalent input noise
current
TEST CONDITIONS
Total harmonic distortion
TYP
MIN
TYP
MAX
TLE2027
1.7
2.8
1.7
2.8
TLE2037
6
7.5
6
7.5
RL = 2 kΩ,
CL = 100 pF,
TA = − 55°C to 125°C,
See Figure 1
TLE2027
1
1
TLE2037
4.4
4.4
RS = 20 Ω,
f = 10 Hz
3.3
8
3.3
4.5
RS = 20 Ω,
f = 1 kHz
2.5
4.5
2.5
3.8
50
250
50
130
f = 0.1 Hz to 10 Hz
10
10
f = 1 kHz
0.8
0.8
VO = + 10 V,
AVD = 5,
See Note 5
Unity-gain bandwidth
(see Figure 3)
RL = 2 kΩ,
CL = 100 pF
BOM
Maximum output-swing
bandwidth
RL = 2 kΩ
φm
Phase margin at unity
gain (see Figure 3)
RL = 2 kΩ,
CL = 100 pF
TLE2027
<0.002
UNIT
V/µs
f = 10 Hz
B1
nV/√Hz
nV
pA/√Hz
<0.002
%
TLE2037
<0.002
<0.002
TLE2027
7
13
9
13
TLE2037
35
50
35
50
TLE2027
30
30
TLE2037
80
80
TLE2027
55
55
TLE2037
50
50
NOTE 5: Measured distortion of the source used in the analysis was 0.002%.
6
TLE20x7A-Q1
MAX
RL = 2 kΩ,
CL = 100 pF,
See Figure 1
VO = + 10 V,
AVD = 1,
See Note 5
THD
MIN
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MHz
kHz
°
SGLS202A − OCTOBER 2003 – REVISED OCTOBER 2006
PARAMETER MEASUREMENT INFORMATION
2 kΩ
Rf
15 V
15 V
−
−
VO
VO
RI
+
+
VI
CL =
100 pF
(see Note A)
− 15 V
RL = 2 kΩ
20 Ω
20 Ω
− 15 V
NOTE A: CL includes fixture capacitance.
Figure 1. Slew-Rate Test Circuit
Figure 2. Noise-Voltage Test Circuit
Rf
10 kΩ
15 V
100 Ω
VI
15 V
−
−
VO
VO
RI
VI
+
−15 V
CL =
100 pF
(see Note A)
+
CL =
100 pF
(see Note A)
− 15 V
2 kΩ
NOTE A: CL includes fixture capacitance.
2 kΩ
NOTES: A. CL includes fixture capacitance.
B. For the TLE2037 and TLE2037A,
AVD must be ≥ 5.
Figure 3. Unity-Gain Bandwidth and
Phase-Margin Test Circuit (TLE2027 Only)
POST OFFICE BOX 655303
Figure 4. Small-Signal PulseResponse Test Circuit
• DALLAS, TEXAS 75265
7
SGLS202A − OCTOBER 2003 – REVISED OCTOBER 2006
typical values
Typical values presented in this data sheet represent the median (50% point) of device parametric performance.
initial estimates of parameter distributions
In the ongoing program of improving data sheets and supplying more information to our customers, Texas
Instruments has added an estimate of not only the typical values, but also the spread around these values.
These are in the form of distribution bars that show the 95% (upper) points and the 5% (lower) points from the
characterization of the initial wafer lots of this new device type (see Figure 5). The distribution bars are shown
at the points where data was actually collected. The 95% and 5% points are used instead of ±3 sigma, since
some of the distributions are not true Gaussian distributions.
The number of units tested and the number of different wafer lots used are on all of the graphs where distribution
bars are shown. As noted in Figure 5, there were a total of 835 units from two wafer lots. In this case, there is
a good estimate for the within-lot variability and a possibly poor estimate of the lot-to-lot variability. This is always
the case on newly released products, since there can only be data available from a few wafer lots.
The distribution bars are not intended to replace the minimum and maximum limits in the electrical tables. Each
distribution bar represents 90% of the total units tested at a specific temperature. While 10% of the units tested
fell outside any given distribution bar, this should not be interpreted to mean that the same individual devices
fell outside every distribution bar.
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
I CC − Supply Current − mA
5
4.5
4
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
VCC± = ±15 V
VO = 0
No Load
Sample Size = 835 Units
From 2 Water Lots
95% point on the distribution bar
(5% of the devices fell above this point.)
90% of the devices were within the upper
and lower points on the distribution bar.
5% point on the distribution bar
(5% of the devices fell below this point.)
3.5
3
2.5
− 75 − 50 − 25
0
25
50
75
100 125 150
TA − Free-Air Temperature − °C
Figure 5. Sample Graph With Distribution Bars
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SGLS202A − OCTOBER 2003 – REVISED OCTOBER 2006
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VIO
Input offset voltage
Distribution
6, 7
∆VIO
Input offset voltage change
vs
Time after power on
8, 9
IIO
Input offset current
vs
Free-air temperature
10
IIB
Input bias current
vs
vs
Free-air temperature
Common-mode input voltage
11
12
II
VO(PP)
Input current
vs
Differential input voltage
Maximum peak-to-peak output voltage
vs
Frequency
14, 15
Maximum (positive/negative) peak output
voltage
vs
vs
Load resistance
Free-air temperature
16, 17
18, 19
AVD
Large-signal differential voltage amplification
vs
vs
vs
vs
Supply voltage
Load resistance
Frequency
Free-air temperature
20
21
22 − 25
26
zo
Output impedance
vs
Frequency
27
CMRR
Common-mode rejection ratio
vs
Frequency
28
kSVR
Supply-voltage rejection ratio
vs
Frequency
29
IOS
Short-circuit output current
vs
vs
vs
Supply voltage
Elapsed time
Free-air temperature
30, 31
32, 33
34, 35
ICC
Supply current
vs
vs
Supply voltage
Free-air temperature
36
37
Voltage-follower pulse response
Small signal
Large signal
Equivalent input noise voltage
vs
Noise voltage (referred to input)
Over 10-second interval
43
Unity-gain bandwidth
vs
vs
Supply voltage
Load capacitance
44
45
Gain bandwidth product
vs
vs
Supply voltage
Load capacitance
46
47
Slew rate
vs
Free-air temperature
48, 49
Phase margin
vs
vs
vs
Supply voltage
Load capacitance
Free-air temperature
50, 51
52, 53
54, 55
Phase shift
vs
Frequency
22 − 25
VOM
Vn
B1
SR
φm
POST OFFICE BOX 655303
Frequency
• DALLAS, TEXAS 75265
13
38, 40
39, 41
42
9
SGLS202A − OCTOBER 2003 – REVISED OCTOBER 2006
TYPICAL CHARACTERISTICS
DISTRIBUTION
INPUT OFFSET VOLTAGE
INPUT OFFSET VOLTAGE CHANGE
vs
TIME AFTER POWER ON
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
16
Percentage of Amplifiers − %
14
12
AVIO
∆
VIO − Change in Input Offset Voltage − µV
1568 Amplifiers Tested From 2 Wafer Lots
VCC± = +15 V
TA = 25°C
D Package
10
8
6
4
2
0
− 120 − 90 − 60 − 30
0
30
60
90
120
VIO − Input Offset Voltage − µV
12
10
8
6
ÎÎÎÎÎÎÎÎÎÎÎ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁ ÎÎÎÎÎÎÎÎÎÎÎ
ÁÁ ÎÎÎÎ ÁÁÁÁÁ
ÁÁ ÎÎÎÎ
4
50 Amplifiers Tested From 2 Wafer Lots
VCC± = ±15 V
TA = 25°C
D Package
2
0
0
10
20
30
40
50
t − Time After Power On − s
Figure 6
Figure 7
INPUT OFFSET CURRENT †
vs
FREE-AIR TEMPERATURE
6
30
5
25
4
3
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÁÁÁ ÎÎÎÎ
ÁÁÁ ÎÎÎÎ
2
50 Amplifiers Tested From 2 Wafer Lots
VCC± = ±15 V
TA = 25°C
P Package
0
0
20
40
60
80
100 120 140 160 180
IIO
I IO − Input Offset Current − nA
AVIO
∆
VIO − Change in Input Offset Voltage − µV
INPUT OFFSET VOLTAGE CHANGE
vs
TIME AFTER POWER ON
1
60
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
VCC± = ±15 V
VIC = 0
Sample Size = 833 Units
From 2 Wafer Lots
20
15
10
5
0
− 75 − 50 − 25
0
25
50
75
100 125 150
TA − Free-Air Temperature − °C
t − Time After Power On − s
Figure 8
Figure 9
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
10
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• DALLAS, TEXAS 75265
SGLS202A − OCTOBER 2003 – REVISED OCTOBER 2006
TYPICAL CHARACTERISTICS
INPUT BIAS CURRENT †
vs
FREE-AIR TEMPERATURE
VCC ± = ±15 V
VIC = 0
Sample Size = 836 Units
From 2 Wafer Lots
IIIB
IB − Input Bias Current − nA
50
40
30
20
10
0
40
35
IIIB
IB − Input Bias Current − nA
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
60
INPUT BIAS CURRENT
vs
COMMON-MODE INPUT VOLTAGE
VCC± = ±15 V
TA = 25°C
30
25
20
15
10
−10
5
−20
−75 −50 −25 0
25 50 75 100 125 150
TA − Free-Air Temperature − °C
0
−12
−8
−4
0
4
8
VIC − Common-Mode Input Voltage − V
Figure 10
Figure 11
TLE2027
MAXIMUM PEAK-TO-PEAK
OUTPUT VOLTAGE †
vs
FREQUENCY
INPUT CURRENT
vs
DIFFERENTIAL INPUT VOLTAGE
0.8
IIII − Input Current − mA
0.6
0.4
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
VO(PP) − Maximum Peak-to-Peak Output Voltage − V
1
VCC ± = ±15 V
VIC = 0
TA = 25°C
0.2
0
− 0.2
− 0.4
− 0.6
− 0.8
−1
− 1.8
− 1.2
− 0.6
0
12
0.6
1.2
1.8
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
30
VCC± = ±15 V
RL = 2 kΩ
25
20
15
TA = 125°C
10
5
TA = − 55°C
0
10 k
VID − Differential Input Voltage − V
100 k
1M
10 M
f − Frequency − Hz
Figure 13
Figure 12
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
SGLS202A − OCTOBER 2003 – REVISED OCTOBER 2006
TYPICAL CHARACTERISTICS
20
ÎÎÎÎ
ÎÎÎÎ
15
TA = 125°C
10
TA = − 55°C
5
0
10 k
100 k
1M
10 M
100 M
f − Frequency − Hz
Figure 14
− 12
− 10
ÁÁ
ÁÁ
ÁÁ
−8
−6
0
100
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
12
10
8
6
4
VCC ± = ±15 V
TA = 25°C
2
0
100
1k
RL − Load Resistance − Ω
10 k
Figure 15
− 14
−2
14
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁ
MAXIMUM NEGATIVE PEAK
OUTPUT VOLTAGE
vs
LOAD RESISTANCE
−4
VVOM+
OM + − Maximum Positive Peak Output Voltage − V
VCC ± = ±15 V
RL = 2 kΩ
25
ÁÁ
ÁÁ
ÁÁ
VVOM−
OM − − Maximum Negative Peak Output Voltage − V
ÎÎÎÎÎÎ
ÁÁÁÁÁ
ÎÎÎÎÎÎ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÎÎÎÎÎÎ
30
MAXIMUM POSITIVE PEAK
OUTPUT VOLTAGE
vs
LOAD RESISTANCE
VCC ± = ±15 V
TA = 25°C
1k
RL − Load Resistance − Ω
10 k
VVOM+
OM + − Maximum Positive Peak Output Voltage − V
VO(PP)
VO(PP) − Maximum Peak-to-Peak Output Voltage − V
TLE2037
MAXIMUM PEAK-TO-PEAK
OUTPUT VOLTAGE †
vs
FREQUENCY
MAXIMUM POSITIVE PEAK
OUTPUT VOLTAGE †
vs
FREE-AIR TEMPERATURE
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
13.5
13.4
VCC± = ±15 V
RL = 2 kΩ
Sample Size = 832 Units
From 2 Wafer Lots
13.3
13.2
13.1
ÁÁ
ÁÁ
ÁÁ
13
12.9
− 75 − 50 − 25
Figure 16
0
25
50
75
100 125 150
TA − Free-Air Temperature − °C
Figure 17
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
12
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SGLS202A − OCTOBER 2003 – REVISED OCTOBER 2006
LARGE-SIGNAL DIFFERENTIAL
VOLTAGE AMPLIFICATION
vs
SUPPLY VOLTAGE
MAXIMUM NEGATIVE PEAK
OUTPUT VOLTAGE †
vs
FREE-AIR TEMPERATURE
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
− 13
VCC ± = ±15 V
RL = 2 kΩ
Sample Size = 831 Units
From 2 Wafer Lots
− 13.2
− 13.4
TA = 25°C
RL = 2 kΩ
40
RL = 1 kΩ
30
ÁÁ
ÁÁ
ÁÁ
− 13.6
− 13.8
ÁÁ
ÁÁ
ÁÁ
ÎÎÎÎ
50
AVD
AVD − Large-Signal Differential
Voltage Amplification − V/ µ V
VVOM−
OM − − Maximum Negative Peak Output Voltage − V
TYPICAL CHARACTERISTICS
− 14
− 75 − 50 − 25
20
RL = 600 Ω
10
0
0
25
50
75
0
100 125 150
4
8
12
16
20
VCC± − Supply Voltage − V
TA − Free-Air Temperature − °C
Figure 19
Figure 18
LARGE-SIGNAL DIFFERENTIAL
VOLTAGE AMPLIFICATION
vs
LOAD RESISTANCE
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
AVD
AVD − Large-Signal Differential
Voltage Amplification − V/ µ V
50
ÁÁ
ÁÁ
ÁÁ
VCC± = ±15 V
TA = 25°C
40
30
20
10
0
100
200
400
1k
2k
4k
10 k
RL − Load Resistance − Ω
Figure 20
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
SGLS202A − OCTOBER 2003 – REVISED OCTOBER 2006
TYPICAL CHARACTERISTICS
TLE2027
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
160
75°
Phase Shift
100°
120
125°
AVD
100
150°
80
175°
60
200°
ÁÁ
ÁÁ
40
225°
VCC± = ±15 V
RL = 2 kΩ
CL = 100 pF
TA = 25°C
20
250°
0
100
100 k
f − Frequency − Hz
0.1
Phase Shift
AVD
AVD− Large-Signal Differential
Voltage Amplification − dB
140
275°
100 M
Figure 21
TLE2037
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
AVD
AVD − Large-Signal Differential
Voltage Amplification − dB
140
120
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
Phase Shift
AVD
100
ÁÁ ÁÁÁÁÁ
ÁÁ ÁÁÁÁÁ
ÁÁ ÁÁÁÁÁ
ÁÁÁÁÁ
0
0.1
VCC± = ±15 V
RL = 2 kΩ
CL = 100 pF
TA = 25°C
150°
225°
250°
100
100 k
f − Frequency − MHz
Figure 22
14
125°
200°
60
20
100°
175°
80
40
75°
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
275°
100 M
Phase Shift
160
SGLS202A − OCTOBER 2003 – REVISED OCTOBER 2006
TYPICAL CHARACTERISTICS
6
100°
3
125°
0
150°
−3
175°
AVD
−6
200°
Phase Shift
−9
225°
ÁÁ
ÁÁ ÎÎÎÎÎ
ÁÁ ÎÎÎÎÎ
ÎÎÎÎÎ
− 12
250°
VCC± = ±15 V
RL = 2 kΩ
CL = 100 pF
TA = 25°C
− 15
− 18
275°
20
10
Phase Shift
AVD
AVD− Large-Signal Differential
Voltage Amplification − dB
TLE2027
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
40
70
300°
100
f − Frequency − MHz
Figure 23
TLE2037
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
100 °
30
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
AVD
20
125 °
Phase Shift
150 °
15
175 °
10
200 °
5
225 °
Á ÁÁÁÁÁÁ
Á ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
VCC± = ±15 V
RL = 2 kΩ
CL = 100 pF
TA = 25°C
0
−5
250 °
275 °
300 °
−10
1
2
Phase Shift
AVD
AVD − Large-Signal Differential
Voltage Amplification − dB
25
4
10
20
f − Frequency − MHz
40
100
Figure 24
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
SGLS202A − OCTOBER 2003 – REVISED OCTOBER 2006
TYPICAL CHARACTERISTICS
LARGE-SIGNAL DIFFERENTIAL
VOLTAGE AMPLIFICATION †
vs
FREE-AIR TEMPERATURE
OUTPUT IMPEDANCE
vs
FREQUENCY
60
RL = 1 kΩ
ÁÁ
ÁÁ
ÁÁ
40
0
25
50
75
100 125 150
TA − Free-Air Temperature − °C
CMRR − Common-Mode Rejection Ratio − dB
10
AVD = 100
See Note A
1
AVD = 10
−10
−100
10
100
1k
10 k
100 k
1M
10 M 100 M
f − Frequency − Hz
NOTE A: For this curve, the TLE2027 is AVD = 1 and the
TLE2037 is AVD = 5.
Figure 25
Figure 26
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
SUPPLY-VOLTAGE REJECTION RATIO
vs
FREQUENCY
ÎÎÎÎÎ
ÁÁÁ
ÁÁÁ
ÎÎÎÎÎ
ÎÎÎ
ÁÁÁ
140
VCC ± = ±15 V
TA = 25°C
120
100
80
60
40
20
0
10
zo - Output Impedance - W
RL = 2 kΩ
VCC ± = ±15 V
TA = 25°C
100
1k
10 k 100 k 1 M
f − Frequency − Hz
10 M 100 M
140
KSVR − Supply-Voltage Rejection Ratio − dB
AVD
AVD − Large-Signal Differential
Voltage Amplification − V/ µ V
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
50
30
−75 −50 −25
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
100
VCC ± = ±15 V
ÎÎÎÎÎ
ÁÁÁÁ
ÁÁÁÁ
ÎÎÎÎ
VCC ± = ±15 V
TA = 25°C
120
ÎÎÎ
ÎÎÎ
100
kSVR −
80
ÎÎÎ
ÎÎÎ
60
kSVR +
40
20
0
10
100
Figure 27
1k
10 k 100 k 1 M
f − Frequency − Hz
10 M 100 M
Figure 28
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
16
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SGLS202A − OCTOBER 2003 – REVISED OCTOBER 2006
TYPICAL CHARACTERISTICS
SHORT-CIRCUIT OUTPUT CURRENT
vs
SUPPLY VOLTAGE
SHORT-CIRCUIT OUTPUT CURRENT
vs
SUPPLY VOLTAGE
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÎÎÎÎ
ÁÁ
ÁÁ
VID = 100 mV
VO = 0
TA = 25°C
P Package
−40
−38
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
44
IIOS
OS − Short-Circuit Output Current − mA
IIOS
OS − Short-Circuit Output Current − mA
−42
−36
−34
VID = −100 mV
VO = 0
TA = 25°C
P Package
42
40
38
36
34
ÁÁ
ÁÁ
−32
32
30
−30
0
2
4
6
8 10 12 14 16
VCC± − Supply Voltage − V
18
0
20
2
4
6
8 10 12 14 16
VCC± − Supply Voltage − V
Figure 29
− 41
SHORT-CIRCUIT OUTPUT CURRENT
vs
ELAPSED TIME
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÎÎÎÎÎ
ÁÁÁÁÁ
ÎÎÎÎÎ
− 39
ÁÁ
ÁÁ
ÁÁ
− 37
− 35
0
30
60
90
120
t − Elapsed Time − s
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÎÎÎÎ
ÁÁÁÁÁ
44
VCC ± = ±15 V
VID = 100 mV
VO = 0
TA = 25°C
P Package
IIOS
OS − Short-Circuit Output Current − mA
IIOS
OS − Short-Circuit Output Current − mA
− 43
20
Figure 30
SHORT-CIRCUIT OUTPUT CURRENT
vs
ELAPSED TIME
− 45
18
150
180
VCC ± = ±15 V
VID = 100 mV
VO = 0
TA = 25°C
P Package
42
40
38
ÁÁ
ÁÁ
ÁÁ
36
34
0
Figure 31
30
60
90
120
t − Elapsed Time − s
150
180
Figure 32
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
17
SGLS202A − OCTOBER 2003 – REVISED OCTOBER 2006
TYPICAL CHARACTERISTICS
SHORT-CIRCUIT OUTPUT CURRENT †
vs
FREE-AIR TEMPERATURE
IIOS
OS − Short-Circuit Output Current − mA
VCC ± = ±15 V
VID = 100 mV
VO = 0
P Package
− 44
− 40
− 36
− 32
ÁÁ
ÁÁ
ÁÁ
− 28
− 24
− 75 − 50 − 25 0
25 50 75 100 125 150
TA − Free-Air Temperature − °C
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
46
IIOS
OS − Short-Circuit Output Current − mA
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
− 48
SHORT-CIRCUIT OUTPUT CURRENT †
vs
FREE-AIR TEMPERATURE
VCC ± = ±15 V
VID = − 100 mV
VO = 0
P Package
42
38
34
ÁÁ
ÁÁ
ÁÁ
30
26
− 75 − 50 − 25 0
25 50 75 100 125 150
TA − Free-Air Temperature − °C
Figure 33
Figure 34
SUPPLY CURRENT †
vs
FREE-AIR TEMPERATURE
SUPPLY CURRENT †
vs
SUPPLY VOLTAGE
ÁÁÁÁ
ÁÁÁÁ
VO = 0
No Load
ICC
I CC − Supply Current − mA
5
ÁÁ
ÁÁ
4
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
TA = 125°C
TA = 25°C
3
TA = − 55°C
2
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
5
IICC
CC − Supply Current − mA
6
4.5
VCC ± = ±15 V
VO = 0
No Load
Sample Size = 836 Units
From 2 Wafer Lots
4
ÁÁ
ÁÁ
3.5
3
1
0
0
2
4
6
8 10 12 14 16
VCC± − Supply Voltage − V
18
20
2.5
− 75 − 50 − 25 0
25 50 75 100 125 150
TA − Free-Air Temperature − °C
Figure 35
Figure 36
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
18
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SGLS202A − OCTOBER 2003 – REVISED OCTOBER 2006
TYPICAL CHARACTERISTICS
TLE2027
VOLTAGE-FOLLOWER
SMALL-SIGNAL
PULSE RESPONSE
VO − Output Voltage − mV
VCC± = ±15 V
RL = 2 kΩ
CL = 100 pF
TA = 25°C
See Figure 4
50
0
− 50
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
15
VCC± = ±15 V
RL = 2 kΩ
CL = 100 pF
TA = 25°C
See Figure 1
10
VO − Output Voltage − V
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
100
TLE2027
VOLTAGE-FOLLOWER
LARGE-SIGNAL
PULSE RESPONSE
5
0
−5
− 10
− 100
− 15
0
200
400
600
t − Time − ns
800
1000
0
5
Figure 37
ÎÎÎÎÎÎ
15
50
V
VO
O − Output Voltage − V
V
VO
O − Output Voltage − mV
10
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
100
200
ÎÎÎÎÎ
ÎÎÎÎÎ
5
0
−5
− 10
− 100
0
VCC ± = ±15 V
AVD = 5
RL = 2 kΩ
CL = 100 pF
TA = 25°C
See Figure 1
ÁÁ
ÁÁ
VCC ± = ±15 V
AVD = 5
RL = 2 kΩ
CL = 100 pF
TA = 25°C
See Figure 4
− 50
25
TLE2037
VOLTAGE-FOLLOWER
LARGE-SIGNAL
PULSE RESPONSE
100
ÁÁ
ÁÁ
20
Figure 38
TLE2037
VOLTAGE-FOLLOWER
SMALL-SIGNAL
PULSE RESPONSE
0
10
15
t − Time − µs
300
400
− 15
0
t − Time − ns
Figure 39
2
4
6
t − Time − µs
8
10
Figure 40
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
19
SGLS202A − OCTOBER 2003 – REVISED OCTOBER 2006
TYPICAL CHARACTERISTICS
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
10
VCC ± = ±15 V
RS = 20 Ω
TA = 25°C
See Figure 2
Sample Size = 100 Units
From 2 Wafer Lots
8
6
4
50
40
30
Noise Voltage − nV
ÁÁ
ÁÁ
ÁÁ
Vn
V n − Equivalent Input Noise Voltage − nVHz
nV/ Hz
NOISE VOLTAGE
(REFERRED TO INPUT)
OVER A 10-SECOND INTERVAL
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
20
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
VCC ± = ±15 V
f = 0.1 to 10 Hz
TA = 25°C
10
0
− 10
− 20
2
− 30
− 40
0
1
10
100
1k
10 k
100 k
− 50
0
2
4
f − Frequency − Hz
Figure 41
52
RL = 2 kΩ
CL = 100 pF
TA = 25°C
See Figure 3
Gain-Bandwidth Product − MHz
B1 − Unity-Gain Bandwidth − MHz
10
TLE2037
GAIN-BANDWIDTH PRODUCT
vs
SUPPLY VOLTAGE
20
16
14
12
51
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
f = 100 kHz
RL = 2 kΩ
CL = 100 pF
TA = 25°C
50
49
48
10
0
2
4
6
8 10 12 14 16 18
| VCC± | − Supply Voltage − V
20
22
0
2
4
6
8
10
Figure 44
POST OFFICE BOX 655303
12
14
16
VCC± − Supply Voltage − V
Figure 43
20
8
Figure 42
TLE2027
UNITY-GAIN BANDWIDTH
vs
SUPPLY VOLTAGE
18
6
t − Time − s
• DALLAS, TEXAS 75265
18
20
SGLS202A − OCTOBER 2003 – REVISED OCTOBER 2006
TYPICAL CHARACTERISTICS
TLE2027
UNITY-GAIN BANDWIDTH
vs
LOAD CAPACITANCE
VCC± = ±15 V
RL = 2 kΩ
TA = 25°C
See Figure 3
12
8
4
VCC± = ±15 V
RL = 2 kΩ
TA = 25°C
51
50
49
48
100
0
100
1000
CL − Load Capacitance − pF
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
52
Gain-Bandwidth Product − MHz
B1 − Unity-Gain Bandwidth − MHz
16
TLE2037
GAIN-BANDWIDTH PRODUCT
vs
LOAD CAPACITANCE
10000
1000
Figure 45
Figure 46
TLE2027
SLEW RATE †
vs
FREE-AIR TEMPERATURE
TLE2037
SLEW RATE †
vs
FREE-AIR TEMPERATURE
3
10
2.8
SR − Slew Rate − V/ µ s
SR − Slew Rate − V/ µs
9
2.6
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
2.4
2.2
VCC± = ±15 V
AVD = 1
RL = 2 kΩ
CL = 100 pF
See Figure 1
2
− 75 − 50 − 25
0
10000
CL − Load Capacitance − pF
8
ÎÎÎÎÎ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÎÎÎÎÎ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
VCC ± = ±15 V
AVD = 5
RL = 2 kΩ
CL = 100 pF
See Figure 1
7
6
25
50
75
100 125 150
TA − Free-Air Temperature − °C
5
− 75 − 50 − 25 0
25 50 75 100 125 150
TA − Free-Air Temperature − °C
Figure 47
Figure 48
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
21
SGLS202A − OCTOBER 2003 – REVISED OCTOBER 2006
TYPICAL CHARACTERISTICS
TLE2027
PHASE MARGIN
vs
SUPPLY VOLTAGE
56°
φ m − Phase Margin
54°
52°
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
52°
RL = 2 kΩ
CL = 100 pF
TA = 25°C
See Figure 3
AVD = 5
RL = 2 kΩ
CL = 100 pF
TA = 25°C
50°
φ m − Phase Margin
58°
TLE2037
PHASE MARGIN
vs
SUPPLY VOLTAGE
50°
ÁÁ
ÁÁ
48°
48°
46°
44°
42°
46°
40°
44°
38°
42°
0
2
4
6
8
10
12
14
16
18
20
0
22
2
8
10
12
14
16
VCC± − Supply Voltage − V
Figure 49
Figure 50
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
60°
ÁÁ
ÁÁ
30°
20°
20
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
60°
VCC ± = ±15 V
RL = 2 kΩ
TA = 25°C
50°
φ m − Phase Margin
40°
18
TLE2037
PHASE MARGIN
vs
LOAD CAPACITANCE
VCC± = ±15 V
RL = 2 kΩ
TA = 25°C
See Figure 3
50°
φ m − Phase Margin
6
| VCC± | − Supply Voltage − V
TLE2027
PHASE MARGIN
vs
LOAD CAPACITANCE
40°
30°
20°
10°
10°
0°
100
1000
CL − Load Capacitance − pF
0°
100
1000
CL − Load Capacitance − pF
Figure 51
22
4
Figure 52
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
10000
SGLS202A − OCTOBER 2003 – REVISED OCTOBER 2006
TYPICAL CHARACTERISTICS
TLE2027
PHASE MARGIN †
vs
FREE-AIR TEMPERATURE
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
65°
50°
ÁÁ
ÁÁ
45°
VCC ± = ±15 V
AVD = 5
RL = 2 kΩ
CL = 100 pF
53°
φ m − Phase Margin
55°
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
55°
VCC± = ±15 V
RL = 2 kΩ
TA = 25°C
See Figure 3
60°
φ m − Phase Margin
TLE2037
PHASE MARGIN †
vs
FREE-AIR TEMPERATURE
51°
49°
47°
40°
35°
− 75 − 50 − 25
0
25
50
75 100
TA − Free-Air Temperature − °C
125
150
45°
− 75 − 50 − 25
0
25
50
75
100 125 150
TA − Free-Air Temperature − °C
Figure 53
Figure 54
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
23
SGLS202A − OCTOBER 2003 – REVISED OCTOBER 2006
APPLICATION INFORMATION
input offset voltage nulling
The TLE2027 and TLE2037 series offers external null pins that can be used to further reduce the input offset
voltage. The circuits of Figure 55 can be connected as shown if the feature is desired. If external nulling is not
needed, the null pins may be left disconnected.
1 kΩ
VCC +
10 kΩ
4.7 kΩ
VCC +
4.7 kΩ
IN −
−
IN −
−
OUT
OUT
IN +
+
+
IN +
VCC −
VCC −
(b) ADJUSTMENT WITH IMPROVED SENSITIVITY
(a) STANDARD ADJUSTMENT
Figure 55. Input Offset Voltage Nulling Circuits
voltage-follower applications
The TLE2027 circuitry includes input-protection diodes to limit the voltage across the input transistors; however,
no provision is made in the circuit to limit the current if these diodes are forward biased. This condition can occur
when the device is operated in the voltage-follower configuration and driven with a fast, large-signal pulse. It
is recommended that a feedback resistor be used to limit the current to a maximum of 1 mA to prevent
degradation of the device. Also, this feedback resistor forms a pole with the input capacitance of the device.
For feedback resistor values greater than 10 kΩ, this pole degrades the amplifier phase margin. This problem
can be alleviated by adding a capacitor (20 pF to 50 pF) in parallel with the feedback resistor (see Figure 56).
CF = 20 to 50 pF
IF ≤ 1 mA
RF
VCC
−
VO
VI
+
VCC −
Figure 56. Voltage Follower
24
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SGLS202A − OCTOBER 2003 – REVISED OCTOBER 2006
APPLICATION INFORMATION
macromodel information
Macromodel information provided was derived using Microsim Parts, the model generation software used
with Microsim PSpice . The Boyle macromodel (see Note 6) and subcircuit in Figure 57, Figure 58, and
Figure 59 were generated using the TLE20x7 typical electrical and operating characteristics at 25°C. Using this
information, output simulations of the following key parameters can be generated to a tolerance of 20% (in most
cases):
•
•
•
•
•
•
•
•
•
•
•
•
Maximum positive output voltage swing
Maximum negative output voltage swing
Slew rate
Quiescent power dissipation
Input bias current
Open-loop voltage amplification
Gain-bandwidth product
Common-mode rejection ratio
Phase margin
DC output resistance
AC output resistance
Short-circuit output current limit
NOTE 6: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers”, IEEE Journal
of Solid-State Circuits, SC-9, 353 (1974).
3
VCC +
9 egnd
rc1
1
rp
c1
Q1
2
dp
vc
Q2
14
re1
+ dip
−
r2
C2
6
ree
cee
dc
−
vin
+
7
gcm
vlim
8
−
ro1
54 de
−
91
+
vip
−
+
ga
10
4
90
hlim
53
re2
lee
92
ro2
−
−
13
dln
− fb
vb
+
IN −
VCC −
+
12
11
IN +
rc2
99
+
5
+
ve
OUT
Figure 57. Boyle Macromodel
PSpice and Parts are trademarks of MicroSim Corporation.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
25
SGLS202A − OCTOBER 2003 – REVISED OCTOBER 2006
APPLICATION INFORMATION
macromodel information (continued)
.subckt TLE2027 1 2 3 4 5
*
c1
11
12
4.003E-12
c2
6
7
20.00E-12
dc
5
53
dz
de
54
5
dz
dlp
90
91
dz
dln
92
90
dx
dp
4
3
dz
egnd
99
0
poly(2) (3,0)
(4,0) 0 5 .5
fb
7
99
poly(5) vb vc
ve vlp vln 0 954.8E6 −1E9 1E9 1E9
−1E9
ga
6
0
11 12
2.062E-3
gcm
0
6
10 99
531.3E-12
iee
10
4
dc 56.01E-6
hlim
90
0
vlim 1K
q1
11
2
13 qx
q2
12
1
14 qx
r2
6
9
100.0E3
rc1
3
11
530.5
rc2
3
12
530.5
re1
13
10
−393.2
re2
14
10
−393.2
ree
10
99
3.571E6
ro1
8
5
25
ro2
7
99
25
rp
3
4
8.013E3
vb
9
0
dc 0
vc
3
53
dc 2.400
ve
54
4
dc 2.100
vlim
7
8
dc 0
vlp
91
0
dc 40
vln
0
92
dc 40
.modeldx D(Is=800.0E-18)
.modelqx NPN(Is=800.0E-18
Bf=7.000E3)
.ends
Figure 58. TLE2027 Macromodel Subcircuit
.subckt TLE2037 1 2 3 4 5
*
c1
11
12
4.003E−12
c2
6
7
7.500E−12
dc
5
53
dz
de
54
5
dz
dlp
90
91
dz
dln
92
90
dx
dp
4
3
dz
egnd
99
0
poly(2) (3,0)
(4,0) 0 .5 .5
fb
7
99
poly(5) vb vc
ve vip vln 0 923.4E6 A800E6
800E6 800E6 A800E6
ga
6
0
11 12 2.121E−3
gcm
0
6
10 99 597.7E−12
iee
10
4
dc 56.26E−6
hlim
90
0
vlim 1K
q1
11
2
13 qx
q2
12
1
14 qz
r2
6
9
100.0E3
rc1
3
11
471.5
rc2
3
12
471.5
re1
13
10
A448
re2
14
10
A448
ree
10
99
3.555E6
ro1
8
5
25
ro2
7
99
25
rp
3
4
8.013E3
vb
9
0
dc 0
vc
3
53
dc 2.400
ve
54
4
dc 2.100
vlim
7
8
dc 0
vlp
91
0
dc 40
vln
0
92
dc 40
.model
dxD(Is=800.0E−18)
.model
qxNPN(Is=800.0E−18
Bf=7.031E3)
.ends
Figure 59. TLE2037 Macromodel Subcircuit
26
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
4-Oct-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TLE2037AQDRG4Q1
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLE2037AQDRQ1
ACTIVE
SOIC
D
8
2500
CU NIPDAU
Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
TLE2037QDRG4Q1
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLE2037QDRQ1
ACTIVE
SOIC
D
8
2500
CU NIPDAU
Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
Pb-Free
(RoHS)
Pb-Free
(RoHS)
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
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Addendum-Page 1
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