TPS51727 www.ti.com .............................................................................................................................................................. SLUS806A – APRIL 2008 – REVISED MAY 2008 DUAL-PHASE, ECO-MODE™ STEP-DOWN POWER MANAGEMENT IC FOR 50-A+ APPLICATIONS FEATURES 1 DESCRIPTION • Seamless Phase Add/Drop Enables Maximum Efficiency Under Any Load Condition • Minimum External Parts Count • ±8 mV VOUT Accuracy Over Line/Load/Temp. • 5-Bit DAC with 0.4-V to 1.25-V Output Range Supports Wide Range of Applications • Optimized Efficiency at Light & Heavy Loads • Patent Pending Output Overshoot Reduction (OSR™) • Accurate, Adjustable Voltage Positioning • Selectable 200/300/400/500 kHz Frequency • Pat. pending AutoBalance™ Phase Balancing • Supports Resistor or Inductor DCR Current Sensing • Accurate, Selectable Current Limit • 4.5-V to 28-V Conversion Voltage Range • Fast MOSFET Driver w/Integrated Boost Diode • Integrated OVP Can Be Disabled Thermal Sensor and Output Power Monitor • Small 6 × 6, 40-Pin QFN PowerPAD™ Package 2 The TPS51727 is a complete, step down controller with integrated gate drivers. The PCNT pin enables operation in dual or single-phase mode to optimize efficiency depending on the load requirements. The advanced D-CAP+™ architecture provides fast transient response with minimum output capacitance. The DAC supports VID-on-the-fly transitions to optimize the output voltage to the operating state of the system to meet idle power requirements. The auto-skip feature of the TPS51727 optimizes light-load efficiency in both single and dual phase operation. System management features include an adjustable thermal sensor, output power monitoring and sleep state controls. Adjustable control of VOUT slew rate and voltage positioning are provided. In addition, the TPS51727 includes two high-current MOSFET gate drivers to drive high and low side N-channel MOSFETs with exceptionally high speed and low switching loss The PCNT and VID0 through VID4, pins have flexible LV I/O thresholds that enable interface with logic voltages from 1.0 V to 3.6 V. The TPS51727 is packaged in a space saving, thermally enhanced, RoHS compliant 40-pin QFN and is rated to operate from –10°C to 100°C. APPLICATIONS • High-Current, Low-Voltage Applications for Adapter, Battery, NVDC or 5-V/12-V Rails PMON EN SLP PGOOD 37 36 35 34 33 32 31 TONSEL PMON EN N/C SLP VREF V5 R5 1 39 38 ISLEW PGND C6 40 V5FILT VREF OSRSEL C1 1 mF DROOP VBAT PGOOD V5 TRIPSEL R1 3 GND CSP1 4 CSP1 CSN1 5 CSN1 CSN2 6 CSN2 PGND 25 CSP2 7 CSP2 DRVL2 24 8 GFB 9 COUT V5IN 26 PGND Q4 L2 0.36 mH C10 VFB VBST2 22 1 mF 10 THRM DRVH2 21 VID1 VID0 17 18 19 20 VID0 16 VID1 15 VID2 14 VID2 VID4 VID3 13 VID3 PD2 12 VID4 DACS Q3 11 V5 RT2 VOUT + Q2 LL2 23 THAL R7 TPS51727 RHA PCNT VFB LL1 28 PD1 GFB L1 0.36 mH C4 DRVL1 27 PCNT R6 VBST 29 THAL VOUT VREF CSN1 CIN Q1 DRVH1 30 C8 2 CSP1 Time Constant and Thermal Matching C11 1 mF Time Constant and Thermal Matching CSP2 CSN2 VBAT UDG-08003 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. ECO-MODE, OSR, AutoBalance, PowerPAD, D-CAP+, D-CAP+ are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008, Texas Instruments Incorporated TPS51727 SLUS806A – APRIL 2008 – REVISED MAY 2008 .............................................................................................................................................................. www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION TA PACKAGE –10°C to 100°C Plastic Quad Flat Pack (QFN) DEVICE NUMBER TPS51727RHAT TPS51727RHAR PINS OUTPUT SUPPLY 40 Tape-and-reel MINIMUM QUANTITY ECO PLAN 250 Green (RoHS and no Sb/Br) 2500 ABSOLUTE MAXIMUM RATINGS Over operating free-air temperature range (unless otherwise noted, all voltages are with respect to GND.) PARAMETER Input voltage range (2) Output voltage range (2) VALUE VBST1, VBST2 –0.3 to 36 VBST1, VBST2 to LL1 or LL2 –0.3 to 6 CSP1, CSN1, CSP2, CSN2, THRM, VID0, VID1, VID2, VID3, VID4, PD1, PD2, DACS, VFB, SLP, OSRSEL, GFB V5IN, V5FILT, PCNT, TRIPSEL TONSEL, ISLEW, EN –0.3 to 6 LL1, LL2 –5.0 to 30 DRVH1, DRVH2 –5.0 to 36 DRVH1, DRVH2 to LL1 or LL2 –0.3 to 6 Operating junction temperature Tstg Storage junction temperature (2) V –0.3 to 6 PGND, GFB TJ UNIT V VREF, DROOP, DRVL1, DRVL2, PMON, PGOOD (1) (1) –0.3 to 0.3 +150 °C –55 to 150 Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the network ground terminal unless otherwise noted. DISSIPATION RATINGS PACKAGE TA <25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 100°C POWER RATING 40-pin RHA 3.125 W 31.25 mW /°C 0.781 W RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) PARAMETER MIN TYP MAX Conversion voltage (no pin assigned) 3.0 28.0 V5IN, V5FILT 4.50 5.25 VBST1, VBST2 -0.1 34 DRVH1, DRVH2 -0.8 34 LL1, LL2 -0.8 28 Voltage range, 5-V pins VFB, CSP1, CSN1, CSP2, CSN2, PMON, DROOP, ISLEW, DRVL1, DRVL2, THRM, PGOOD, DACS, VREF, TRIPSEL, TONSEL, OSRSEL -0.1 5VIN Voltage range, 3.3-V pins SLP, EN, PCNT, VID0, VID1, VID2, VID3, VID4, PD1, PD2, THAL -0.1 3.6 Voltage range, ground pins PGND, GND, GFB -0.1 0.1 -10 100 Supply voltages Voltage range, conversion pins TJ, Operating junction temperature 2 UNIT V °C Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51727 TPS51727 www.ti.com .............................................................................................................................................................. SLUS806A – APRIL 2008 – REVISED MAY 2008 ELECTROSTATIC DISCHARGE (ESD) PROTECTION PARAMETER MIN TYP MAX UNIT Human body model 2000 V CDM 1500 V 3 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51727 TPS51727 SLUS806A – APRIL 2008 – REVISED MAY 2008 .............................................................................................................................................................. www.ti.com ELECTRICAL CHARACTERISTICS over recommended free-air temperature range, V5IN = V5FILT = 5.0 V GFB = PGND = GND, VFB = VOUT (Unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 2.5 4.0 mA 1 µA SUPPLY: CURRENTS, UVLO AND POWER-ON RESET IV5 V5IN + V5FILT supply current VDAC < VFB < VDAC + 100 mV, EN = HI IV5STBY V5IN + V5FILT standby current EN = LO VUVLOH V5FILT UVLO OK threshold V5FILT = V5IN, VFB < 200 mV, Ramp up; EN = HI; Switching begins 4.25 4.40 4.50 V VUVLOL V5FILT UVLO fault threshold V5FILT = V5IN. Ramp down; EN = HI, VFB = 100 mV, Restart if 5 V dips below VPOR then rises > VUVLOH or VEN is toggled with 5 V > VUVLOH 4.05 4.15 4.30 V VPOR V5FILT fault latch reset threshold V5FILT=V5IN, Ramp Down, EN = HI, Can restart if 5V goes up to VUVLOH and no other faults present 1.60 1.89 2.25 V REFERENCES: DAC, VREF, VBOOT AND DRVL DISCHARGE VVIDSTP VID Step Size Change VID0 HI to LO to HI VDAC1 VFB No Load Active 0.750 V ≤ VFB ≤ 1.250 V, +15°C ≤ TJ ≤ 105°C 25 VDAC2 VFB No Load Active/Sleep 0.500 V ≤ VFB ≤ 0.750 V –8 8 mV VDAC3 VFB Deeper Sleep 0.300V ≤ VFB ≤ 0.500 V –12 12 mV VVREF VREF Output V5FILT = 4.5 V to 5.5 V, IREF = 0 VVREFSRC VREF Output Source IREF = 0 µA to 250 µA VVREFSNK VREF Output Sink IREF = –250 µA to 0 µA VDLDQ DRVL Discharge Threshold VFB < 200 mV, DRVL goes high for 1ms –0.55% mV 0.55% 1.675 1.710 1.745 –9 –3 V 10 35 mV 200 250 325 mV 9 20 µA 90 125 175 µA –20 –8 µA ±300 mV mV VOLTAGE SENSE: VFB AND GFB IVFB VFB Input Bias Current Not in Fault, Disable or UVLO; VFB = 2 V, GFB = 0 V IVFBDQ VFB Input Bias Current, Discharge Fault, Disable or UVLO, VFB = 100 mV IGFB GFB Input Bias Current Not in Fault, Disable or UVLO; VFB = 2 V, GFB = 0 V VDELGND GFB Differential AGAINGND GFB/GND Gain VVFBCOM VFB Common Mode Input 0.993 1.000 –0.3 1.007 2.0 V/V V CURRENT SENSE: OVERCURRENT, ZERO CROSSING, VOLTAGE POSITIONING AND PHASE BALANCING VOCPP OCP Voltage Set (Valley Current Limit) TRIPSEL = GND 7.3 11.0 15.5 TRIPSEL = REF 10.7 14.3 19.2 TRIPSEL = 3.3 V 14.3 18.2 22.9 TRIPSEL = V5FILT 19.7 23.8 28.4 TRIPSEL = GND 10.3 14.9 19.0 TRIPSEL = REF 15.4 20.0 24.5 TRIPSEL = 3.3 V 20.4 25.0 29.8 TRIPSEL = V5FILT 27.3 31.7 37.0 VOCPN Negative OCP Voltage (Minimum Magnitude) VOCPCC Channel-to-Channel OCP matching (VCSP1–VCSN1) – (VCSP2–VCSN2) at OCP for each channel ICS CS Pin Input Bias Current CSPx and CSNx VZXOFF Zero Crossing Comp. Internal Offset GM-DROOP Droop Amplifier Transconductance IDROOP Droop Amplifier Sink/Source Current ±1.0 mV mV mV –1.00 0.02 1.00 µA CSPx – CSNx, SLP = High (Skip Mode) –4.0 –0.8 4.0 mV VFB = 1 V 485 500 515 µS 50 100 150 µA IBAL_TOL Internal Current Share Tolerance VDAC = 0.750 V; VCSP1 – VCSN1 = VCSP2 – VCSN2 = VOCP_MIN ACSINT Internal Current Sense Gain Gain from CSPx – CSNx to PWM comparator 4 –3% 5.85 3% 5.95 6.05 V/V Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51727 TPS51727 www.ti.com .............................................................................................................................................................. SLUS806A – APRIL 2008 – REVISED MAY 2008 ELECTRICAL CHARACTERISTICS (continued) over recommended free-air temperature range, V5IN = V5FILT = 5.0 V GFB = PGND = GND, VFB = VOUT (Unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER MONITOR VPWRLK Leakage Level Power Output VDAC = 0.5 V, ΣΔCS = 5 mV 125 280 mV VPWRLO Low Level Power Output VDAC = 1 V, ΣΔCS = 10 mV 180 500 750 mV VPWRMID Mid Level Power Output VDAC = 1.2 V, ΣΔCS = 20 mV 0.75 1.10 1.41 V VPWRHI High Level Power Output VDAC = 1.2875 V, ΣΔCS = 40 mV 1.92 2.25 2.56 KPWR Gain Factor IPWRSRC Power Monitor Source VPWR – 30 mV 800 900 1100 µA IPWRSNK Power Monitor Sink VPWR + 30 mV 130 200 250 µA VBSTx – LLx = 5 V, HI State, VBST – VDRVH = 0.25 V 1.2 2.5 VBSTx – LLx = 5V, LO State, VDRVH – VLL = 0.25 V 0.8 2.5 DRVHx =2.5 V, VBSTx – LLx = 5 V, Src 2.2 DRVHx =2.5 V, VBSTx – LLx = 5 V, Snk 2.2 47.6 V V/V DRIVERS: HIGH SIDE, LOW SIDE, CROSS CONDUCTION PREVENTION AND BOOST RECTIFIER RDRVH DRVH On Resistance IDRVH DRVH Sink/Source Current (1) TDRVH DRVH Transition Time RDRVL DRVL On Resistance IDRVL DRVL Sink/Source Current (1) TDRVL DRVL Transition Time TNONOVLP Driver Non Overlap Time VFBST IBSTLK A 21 40 15 40 HI State, V5IN – VDRVL = 0.25 V 0.9 2 LO State, VDRVL – PGND = 0.25 V 0.4 1 DRVLx = 2.5 V, Source 2.7 DRVHx 10% to 90% or 90% to 10%, CDRVHx = 3 nF DRVLx = 2.5 V, Sink Ω ns Ω A 8 DRVLx 90% to 10%, CDRVLx = 3 nF 10 35 DRVLx 10% to 90%, CDRVLx = 3 nF 20 35 ns LLx falls to 1V to DRVLx rises to 1 V 10 23 35 DRVLx falls to 1V to DRVHx rises to 1 V 15 30 43 BST Rectifier Forward Voltage V5IN – VBST, IF = 5 mA, TA = 25°C 0.6 0.7 0.8 V BST Rectifier Leakage Current VVBST = 34 V, VLL = 28 V 0.1 1 µA ns OVERSHOOT REDUCTION (OSR) THRESHOLD SETTING VOSR OSR Voltage Set VOSRHYS OSR Voltage Hysteresis (1) OSRSEL = GND 75 110 140 OSRSEL = REF 105 145 180 OSRSEL = 3.3 V 145 190 235 OSRSEL = V5FILT (1) All settings mV OFF 20 mV Ensured by design. Not production tested. 5 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51727 TPS51727 SLUS806A – APRIL 2008 – REVISED MAY 2008 .............................................................................................................................................................. www.ti.com ELECTRICAL CHARACTERISTICS (continued) over recommended free-air temperature range, V5IN = V5FILT = 5.0 V GFB = PGND = GND, VFB = VOUT (Unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TIMERS: SLEW RATE, ISLEW, ON-TIME AND I/O TIMING ISLEW 1 RSLEW to GND Current RSLEW = 125 kΩ from ISLEW to GND 9.90 10.00 10.15 µA ISLEW 2 RSLEW to VREF Current RSLEW = 45 kΩ from VREF to ISLEW 9.5 10.2 10.8 µA SLSTRT VFB VID Change Slew Rate ISLEW = |10 µA|, EN goes ‘HI’ (soft-start), VID Slew, Non-OVP Fault = Soft-stop 9 13 16 mV/µs TPGDDGLTO PGOOD Deglitch Time Time from VVFB out of +200 mV VDAC boundary to PGOOD low 40 74 100 µs TPGDDGLTU PGOOD Deglitch Time Time from VVFB out of –300 mV VDAC boundary to PGOOD low 50 105 150 µs VTON = GND, VLLx = 12 V, VVFB = 1 V 285 370 460 VTON = REF, VLLx = 12 V, VVFB = 1 V 200 250 300 VTON = 3.3V, VLLx = 12 V, VVFB = 1 V 160 195 230 VTON = V5FILT, VLLx = 12 V, VFB = 1 140 170 200 95 129 155 TTON On-Time Control TMIN Controller Minimum OFF time TVIDDBNC VID Debounce Time TPCNTBNC PCNT Debounce Time (2) Fixed Value (2) ns ns 100 ns 100 ns (2) TVCCVID VID Change to VFB Change TENPGD EN Low to PGOOD Low TPGDVCC PGOOD Low to VFB Change (2) TTHALDGLT THAL Deglitch Time 0.7 RSFTSTP Soft-stop Transitor Resistance 20 74 1500 ns 100 ns 100 ns 1.1 3.0 ms 600 850 1100 Ω PROTECTION: OVP, UVP, PGOOD, THAL, "FAULTS OFF" AND INTERNAL THRMAL SHUTDOWN Fixed OVP Voltage VVFB > VOVPH for 1 µs, DRVL turns ON 1.65 1.70 1.75 V VPGDH PGOOD High Threshold Measured at the VFB pin wrt / VID code. Device latches OFF, begins soft-stop 180 220 255 mV VPGDL PGOOD Low Threshold Measured at the VFB pin wrt / VID code. IC latches off, begins soft-stop –365 –325 –285 mV VTHRM Thermal Alarm Voltage Measured at THRM; THAL goes LO 0.72 0.75 0.82 V ITHRM THRM Current Measure ITHRM to GND 57 61 67 µA VNOFLT All Faults OFF VTHRM > (VV5FILT + VTH); not latched 4.75 4.90 5.00 THINT Internal Controller Thermal Shutdown (2) Not final tested. Latch off controller, attempt soft-stop THHYS Thermal Shutdown Hysteresis (2) Not final tested. Controller starts again after temperature has dropped VOVPH V 160 °C 10 °C LOGIC PINS: I/O VOLTAGE AND CURRENT VTHALL THAL Pull Down Voltage Pull down voltage with 20-mA sink current ITHALLK THAL Leakage Current Hi-Z Leakage Current, Apply 5-V in off state VPGL PGOOD Pull Down Voltage Pull down voltage with 3-mA sink current IPGLK PGOOD Leakage Current Hi-Z Leakage Current, Apply 5 V in off state VLV_H LV I/O Logic High PCNT, VID0, VID1, VID2, VID3, VID4 VLV_L LV I/O Logic Low PCNT, VID0, VID1, VID2, VID3, VID4 ILV_LK LV I/O Leakage Leakage current, VVID = VPCNT = 1.0 V, VSLP = 3.3 V, VEN = 0 V IVIDLK LV I/O Leakage Leakage current, VVID = VPCNT = 1.0 V, VEN = 3.3 V VV3P3H I/O 3.3 V Logic High EN, SLP VV3P3L I/O 3.3 V Logic Low EN, SLP IENH I/O 3.3 V Leakage Leakage current, VEN = 3.3 V 10.0 ISLPH I/O 3.3 V Leakage Leakage current, VEN = 3.3 V; VSLP = 3.3 V 20.0 –2.0 –2.0 0.4 V 0.2 2.0 µA 0.1 0.4 V 0.1 2.0 µA 0.6 0.7 V 0.3 0.4 –1.0 0.01 5 0.8 IVIDL VVID0 = VVID1 = VVID2 = VVID3 = VVID4 = 0 V, VEN = 3.3 V –3 IDACS VDACS = 5 V, VEN = 3.3 V 25 ISELECT VTRIPSEL = VOSRSEL = VTONSEL = 5 V –2 (2) 0.15 V 1.0 µA 10 15 µA 1.3 2.3 V 25.0 µA 45.0 µA 1 µA 75 µA 5 µA 1.1 –1.5 1.5 V Ensured by design. Not production tested. 6 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51727 TPS51727 www.ti.com .............................................................................................................................................................. SLUS806A – APRIL 2008 – REVISED MAY 2008 ELECTRICAL CHARACTERISTICS (continued) over recommended free-air temperature range, V5IN = V5FILT = 5.0 V GFB = PGND = GND, VFB = VOUT (Unless otherwise noted). PARAMETER ICTRL TEST CONDITIONS VPCNT = VSLP = 0 V; VEN = 3.3 V MIN –1 TYP MAX 1 UNIT µA 7 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51727 TPS51727 SLUS806A – APRIL 2008 – REVISED MAY 2008 .............................................................................................................................................................. www.ti.com DEVICE INFORMATION TERMINAL CONFIGURATION V5FILT ISLEW OSRSEL TONSEL TRIPSEL PMON EN N/C SLP PGOOD RHA Package Terminal Configuration (Top View) 40 39 38 37 36 35 34 33 32 31 DROOP 1 30 DRVH1 VREF 2 29 VBST1 GND 3 28 LL1 CSP1 4 27 DRVL1 26 V5IN CSN1 5 TPS51727 RHA PACKAGE CSN2 6 13 14 15 16 17 18 19 20 VID0 12 VID1 DRVH2 11 VID2 21 VID3 VBST2 THRM 10 VID4 LL2 22 PD2 23 VFB 9 PCNT DRVL2 DACS 24 GFB 8 PD1 PGND THAL 25 CSP2 7 TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION I Negative current sense inputs. Connect to the most negative node of current sense resistor or inductor DCR sense RC network. I Positive current sense inputs. Connect to the most positive node of current sense resistor or inductor DCR sense RC network. 14 I DAC range selection input. Tie to V5FILT. DROOP 1 O Output of GM error amplifier. A resistor to VREF sets the droop gain. A capacitor to VREF helps shape the transient response. DRVH1 30 DRVH2 21 O Top N-channel MOSFET gate drive outputs DRVL1 27 DRVL2 24 O Synchronous N-channel MOSFET gate drive outputs. EN 34 I Enable signal. 3.3V I/O level; 100ns de-bounce. Regulator enters controlled “soft-stop” when brought low. GFB 8 I Voltage sense return. Tie to GND with a 100-Ω resistor to close feedback when voltage sensing through a socket. GND 3 - Analog / signal ground. Tie to quiet ground plane. ISLEW 39 I Precision slew rate control setting. All voltage transitions, including start-up and shutdown, occur at the rated defined by the ISLEW resistor. Tie the ISLEW resistor to GND to enable OVP or VREF to disable OVP. LL1 28 LL2 23 N/C 33 NAME NO. CSN1 5 CSN2 6 CSP1 4 CSP2 7 DACS I/O - Top N-channel MOSFET gate drive return. Also, input for adaptive gate drive timing. Do not connect anything to this pin 8 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51727 TPS51727 www.ti.com .............................................................................................................................................................. SLUS806A – APRIL 2008 – REVISED MAY 2008 TERMINAL FUNCTIONS (continued) TERMINAL NAME OSRSEL NO. I/O DESCRIPTION 38 I Overshoot reduction (OSR) setting. The OSR threshold can be selected or OSR can be disabled. - - Thermal pad; Connect directly to system GND plane with multiple vias. PCNT 13 I Phase control input. 0.5-V threshold logic. High is dual phase mode. PD1 12 PD2 15 I Test pin. Tie to GND. PGOOD 31 O Open-drain PWRGD output. PGND 25 - Synchronous N-channel MOSFET gate drive return. PMON 35 O Power monitor output. VPMON = VOUT × ΣVISENSE × K. See applications section for more detail. SLP 32 I Sleep mode control. 3.3-V I/O Level; disallows switching when entering sleep mode. THAL 11 O Thermal alarm; open drain output, Active low. 1-ms de-glitch filter. THRM 10 I/O Thermal sensor input. An internal 60-µA current source flows into an NTC thermistor connected to GND. The voltage threshold is 0.75-V. Also is a ‘Faults off’ input, (VTHRM = VV5FILT) for debug mode. TONSEL 37 I On-time selection pin. The operating frequency can be set between 200-kHz and 500-kHz in 100-kHz steps. Frequency can be changed during operation. TRIPSEL 36 I Overcurrent protection (OCP) setting. The valley current limit at the CS inputs can be selected in a range between approximately 10-mV to 20-mV. V5IN 26 I 5-V power input for drivers; bypass to PGND with ≥ 1µF ceramic capacitor. V5FILT 40 I 5-V power input for control circuitry. Has internal, 3-Ω resistor to 5VFILT. Bypass to GND with ≥ 1-µF ceramic capacitor. VBST1 22 VBST2 29 I Top N-channel MOSFET bootstrap voltage inputs. VFB 9 I Voltage sense line tied directly to VOUT. Tie to VOUT with a 100-Ω resistor to close feedback when voltage sensing through a socket. VID0 20 VID1 19 VID2 18 I DAC programming bits most significant bit (MSB) to least significant bit (LSB). 0.5-V threshold logic. VID3 17 VID4 16 VREF 2 O 1.7-V, 250-µA voltage reference. Bypass to GND with a 0.22-µF ceramic capacitor. PAD 9 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51727 TPS51727 SLUS806A – APRIL 2008 – REVISED MAY 2008 .............................................................................................................................................................. www.ti.com FUNCTIONAL BLOCK DIAGRAM DROOP TONSEL 1 37 V5FILT 40 Differential Amplifier VFB GFB VREF + 9 26 V5IN VFB + 8 E/A CMP + CLK PWM 2 De-MUX 30 DRVH1 Smart Driver ADDR ILIM MUX VID1 19 LL1 LL2 25 PGND DAC 22 VBST2 VID4 16 DACS 14 CO2 Smart Driver ISLEW 39 CSP1 + 4 IS1 I AMP CSN1 5 CSP2 7 CSN2 6 28 LL1 27 DRVL1 ISHARE DAC VID2 18 29 VBST1 CO1 LL VID0 20 VID3 17 CO On-Time Generator + 21 DRVH2 23 LL2 24 DRVL2 S + + I AMP IS2 Current Sensing Circuitry ADDR IS2 Analog and Protection Circuitry IS1 Control Logic and Status Circuitry VFB 3 10 11 35 36 38 13 32 34 31 GND THRM THAL PMON TRIPSEL OSRSEL PCNT SLP EN PGOOD TPS51727 UDG-08004 Figure 1. TPS51727 Functional Block Diagram 10 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51727 TPS51727 www.ti.com .............................................................................................................................................................. SLUS806A – APRIL 2008 – REVISED MAY 2008 C15 R9 RT3 330uFX4 C7 R10 10uF C12 C11 1uF Q4 Q3 C10 1uF DRH2 BST2 LL2 V5 DRL2 C9 1uF LL1 BST1 DRH1 10uF C14 10uF C13 R8 0.36uH 2 1 L2 0.36uH Q2 C5 10uF 10uF 10uF C3 Q1 C2 1 L1 R3 R2 2 + R4 RT1 C4 APPLICATION DIAGRAMS PGD VID0 SLP VID1 1 VID2 EN VID3 PMON VID4 TRIPSEL TONSEL V5 OSRSEL PCNT ISLEW C1 THRM CSN2 CSP2 CSN1 CSP1 VREF R6 R7 R5 C6 1 C8 0.1uF DROOP 1 1uF V5FILT R1 THAL# Figure 2. Inductor DCR Sense Application Diagram 11 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51727 TPS51727 330uFX4 10uF 10uF C13 C11 Q3 2.2uF C10 C9 1uF DRH2 BST2 LL2 DRL2 V5 LL1 BST1 DRH1 C8 1uF Q4 Q1 Q2 10uF C12 0.36uH 1 L2 1 10uF 10uF 10uF C2 C4 C3 L1 0.36uH 2 2 + C6 SLUS806A – APRIL 2008 – REVISED MAY 2008 .............................................................................................................................................................. www.ti.com PGD VID0 SLP VID1 1 VID2 EN VID3 PMON VID4 TRIPSEL TONSEL V5 OSRSEL PCNT ISLEW C1 THRM CSN2 CSP2 CSN1 CSP1 VREF R4 R5 R3 C5 1 C7 0.1uF DROOP 1 1uF V5FILT R1 THAL# Figure 3. Resistor Sense Application Diagram 12 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51727 TPS51727 www.ti.com .............................................................................................................................................................. SLUS806A – APRIL 2008 – REVISED MAY 2008 APPLICATION CIRCUIT LIST OF MATERIALS Recommended parts for key external components for the circuits in Figure 2 and Figure 3 are in Table 1. These components have passed applications tests. Table 1. Key External Component Recommendations FUNCTION MANUFACTURER COMPONENT NUMBER High-side MOSFET Infineon BSC080N03MSG Low-side MOSFET (x2) Infineon BSC030N03MSG Panasonic ETQP4LR36WFC Tokin MPCG1040LR36 Toko FDUE10140D-R36M Panasonic EEFSX0D331XE NEC Proadlizer PFAF250E127MNS Panasonic ECJ2FB0J106K Murata GRM21BR60J106KE19L Panasonic ERJM1WTJ1M0U Panasonic ERTJ1VV154J Murata NCP18XF151J03RB Inductors Bulk Output Capacitors Ceramic Output Capacitors Sense Resistor (Figure 3 only) NTC Thermistors 13 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51727 TPS51727 SLUS806A – APRIL 2008 – REVISED MAY 2008 .............................................................................................................................................................. www.ti.com TYPICAL CHARACTERISTICS TURBO MODE OUTPUT VOLTAGE vs OUTPUT CURRENT NORMAL MODE OUTPUT VOLTAGE vs OUTPUT CURRENT 1.12 1.300 Specification Maximum Specification Maximum 1.11 1.2875 VOUT – Output Voltage – V VOUT – Output Voltage – V VIN = 20 V Specification Nominal VIN = 20 V 1.275 1.2625 1.25 VIN = 10 V 1.2375 1.225 VIN = 10 V 1.08 1.07 Specification Minimum 1.05 1.2125 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 IOUT – Output Current – A IOUT – Output Current – A Figure 4. Figure 5. SLEEP MODE OUTPUT VOLTAGE vs OUTPUT CURRENT TURBO MODE EFFICIENCY vs OUTPUT CURRENT 20 9 10 90 Specification Maximum 18 88 VIN = 10 V 16 86 VIN = 20 V 14 84 h – Efficiency – % VOUT – Output Voltage – V 1.09 1.06 Specification Minimum Specification Nominal 1.10 VIN = 10 V 12 10 8 6 Specification Nominal 4 80 78 76 74 Specification Minimum 2 82 VIN = 20 V 72 0 70 0 1 2 3 4 5 6 7 8 9 10 0 5 10 15 20 25 30 IOUT – Output Current – A IOUT – Output Current – A Figure 6. Figure 7. 14 35 40 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51727 TPS51727 www.ti.com .............................................................................................................................................................. SLUS806A – APRIL 2008 – REVISED MAY 2008 TYPICAL CHARACTERISTICS (continued) NORMAL MODE EFFICIENCY vs OUTPUT CURRENT SLEEP MODE EFFICIENCY vs OUTPUT CURRENT 90 90 VIN = 10 V 88 85 86 VIN = 10 V h – Efficiency – % h – Efficiency – % 84 82 80 VIN = 20 V 78 76 80 75 VIN = 20 V 70 74 65 72 60 70 0 5 10 15 20 25 30 0 2 3 4 5 6 7 IOUT – Output Current – A Figure 8. Figure 9. CURRENT SHARE IMBALANCE vs OUTPUT CURRENT POWER MONITOR VOLTAGE vs OUTPUT CURRENT 20 8 9 10 2.5 VIN (V) IOUT = 50% Load VIN = 10 V VPMON - Power Monitor Voltage - V 18 16 Phase 1/Phase 2 Imbalance – % 1 IOUT – Output Current – A 14 12 10 5% Limit 8 6 4 Ideal VIPMON 20/10 Ideal VPMON 2.0 1.5 1.0 VIN = 20 V/10 V 0.5 VIN = 20 V 2 K = 47.6 0 0 0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 IOUT – Output Current – A IOUT – Output Current – A Figure 10. Figure 11. 40 45 50 15 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51727 TPS51727 SLUS806A – APRIL 2008 – REVISED MAY 2008 .............................................................................................................................................................. www.ti.com TYPICAL CHARACTERISTICS (continued) VOLTAGE REFERENCE vs OUTPUT CURRENT OPERATING FREQUENCY vs OUTPUT CURRENT 1.7080 550 VIN = 10 V Normal VIN = 20 V Turbo 500 fSW – Operating Frequency – kHz VREF – Voltage Reference – V 1.7075 1.7070 1.7065 VIN = 20 V Normal VIN = 10 V Turbo 1.7060 VIN = 20 V, Sleep 450 400 350 300 250 200 150 200 kHz 300 kHz 400 kHz 500 kHz 100 VIN = 10 V, Sleep 1.7055 0 5 10 15 20 25 30 35 Turbo 10 Turbo 20 Normal 10 Normal 20 50 40 5 10 15 IOUT – Output Current – A 20 25 30 35 40 IOUT – Output Current – A Figure 12. Figure 13. EFFICIENCY vs OUTPUT VOLTAGE EFFICIENCY vs INPUT VOLTAGE 92 92 VOUT = 1.28 V IOUT = 20 A VOUT = 10 V 90 91 h – Efficiency – % h – Efficiency – % 88 86 84 VOUT = 20 V 82 90 89 88 80 87 78 IOUT = 20 A 76 0.4 86 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 4 6 8 10 12 14 16 18 VOUT – Output Voltage – V VIN – Input Voltage – V Figure 14. Figure 15. 16 20 22 24 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51727 TPS51727 www.ti.com .............................................................................................................................................................. SLUS806A – APRIL 2008 – REVISED MAY 2008 TYPICAL CHARACTERISTICS Figure 16. Transient Load Onset, VIN = 10 V Figure 17. Transient Load Release, VIN = 10 V Figure 18. Transient Load Onset, VIN = 20 V Figure 19. Transient Load Release, VIN = 20 V Figure 20. Typical Start-Up to 1.1-V VID Figure 21. Typical Soft-Stop Waveform 17 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51727 TPS51727 SLUS806A – APRIL 2008 – REVISED MAY 2008 .............................................................................................................................................................. www.ti.com TYPICAL CHARACTERISTICS (continued) Figure 22. Typical VID Slew (Envelope Mode) Figure 23. Typical PCNT Phase Add Figure 24. Typical PCNT Phase Drop 18 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51727 TPS51727 www.ti.com .............................................................................................................................................................. SLUS806A – APRIL 2008 – REVISED MAY 2008 DETAILED DESCRIPTION FUNCTIONAL OVERVIEW The TPS51727 is a DCAP+™ mode adaptive on-time converter. The output voltage is set using the 5-bit VID code defined in Table 3. "VID-on-the-fly" transitions are supported with the slew rate controlled by a single resistor on the ISLEW pin. Two powerful integrated drivers support output currents in excess of 50 A. The converter enters single phase mode under PCNT control to optimize light-load efficiency. Four switching frequency selections are provided in 100-kHz increments from 200-kHz to 500-kHz per phase to enable optimization of the power chain for the cost, size and efficiency requirements of the design. (See Table 2) Table 2. Frequency Selection Table TONSEL VOLTAGE (VTONSEL) (V) FREQUENCY (kHz) GND 200 VREF 300 3.3 400 5 500 In adaptive on-time converters, the controller varies the on-time as a function of input and output voltage to maintain a nearly constant frequency during steady-state conditions. In conventional voltage-mode constant on-time converters, each cycle begins when the output voltage crosses to a fixed reference level. However, in the TPS51727, the cycle begins when the current feedback reaches an error voltage level which is the amplified difference between the DAC voltage and the feedback voltage. This approach has two advantages: 1. The amplifier DC gain sets an accurate linear load-line; this is required for many processing applications. 2. The error voltage input to the PWM comparator is filtered to improve the noise performance. In a steady-state condition, the two phases of the TPS51727 switch 180° out-of-phase. The phase displacement is maintained both by the architecture (which does not allow both top gate drives to be on in any condition) and the current ripple (which forces the pulses to be spaced equally). The controller forces current sharing adjusting the on-time of each phase. Current balancing requires no user intervention, compensation, or extra components. Multi-Phase, PWM Operation Referring to Figure 1, in dual-phase steady state, continuous conduction mode, the converter operates as follows: Starting with the condition that both top MOSFETs are off and both bottom MOSFETs are on, the summed current feedback (VCMP) is higher than the error amplifier output (VDROOP). VCMP falls until it hits VDROOP, which contains a component of the output ripple voltage. The PWM comparator senses where the two waveforms cross and triggers the on-time generator. 19 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51727 TPS51727 SLUS806A – APRIL 2008 – REVISED MAY 2008 .............................................................................................................................................................. www.ti.com Voltage - V Summed Current Feedback tON t VCMP VDROOP Time - ms UDG-08005 Figure 25. D-CAP+™ Mode Basic Waveforms The summed current feedback is an amplified and filtered version of the CSPx and CSNx inputs. The TPS51727 provides dual independent channels of current feedback to increase the system accuracy and reduce the dependence of circuit performance on layout compared to an externally summed architecture. PWM Frequency and Adaptive on Time Control The on-time (at the LL node) is determined by Equation 1. æV ö æ 1 ö t ON = ç OUT ÷ ´ ç ÷ + 30 ns è VIN ø è fSEL ø (1) where • fSEL is the frequency selected by the connection of the TONSEL pin The on-time pulse is sent to the top MOSFET. The inductor current and summed current feedback rise to their maximum value, and the multiplexer and de-multiplexer switch to the next phase. Each ON pulse is latched to prevent double pulsing. The current sharing circuitry compares the average values of the individual phase currents, then adds or subtracts a small amount from each on-time in order to bring the phase currents into line. No user design is required. Accurate droop is provided by the finite gain of the droop amplifier. The equation for droop is shown in Equation 2. VDROOP = R CS ´ A CS ´ å I(L) RDROOP ´ GM (2) In Equation 2, RCS is the effective current sense resistance, when using a sense resistor or inductor DCR is used. ACS is the gain of the current sense amplifier, ΣI(L) is the DC sum of inductor currents, RDROOP is the value of resistor from the DROOP pin to VREF, and GM(droop) is the transconductance of the droop amplifier. The capacitor in parallel with RDROOP matches the slew rate of the DROOP pin with the current feedback signals to prevent ring-back during transient load conditions. AutoBalance™ Current Sharing The basic mechanism for current sharing is to sense the average phase current, then adjust the pulse width of each phase to equalize the current in each phase. The block diagram is shown in Figure 26. 20 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51727 TPS51727 www.ti.com .............................................................................................................................................................. SLUS806A – APRIL 2008 – REVISED MAY 2008 TPS51727 LL1 28 MUX LL2 23 CSP1 4 VDAC R(tON) + I AMP CSN1 5 ms Filter + K ´ (I1 - I2 ) – 5 + MUX CSP2 6 – + I AMP CSN2 5 ms Filter + – K ´ (I2 - I1) + PWM C(tON) 7 UDG-08006 Figure 26. Current Sharing Block Diagram Figure 26 also shows the TI D-Cap™ constant on-time modulator. The PWM comparator (not shown) starts a pulse when the feedback voltage meets the reference. This pulse turns on the gate of the high-side MOSFET. After the MOSFET turns on, the LL voltage for that phase is driven up to the battery input. This charges C(tON) through R(tON). The pulse is terminated when the voltage at C(tON) matches the tON reference, normally the DAC voltage (VDAC). V(C(tON)) - On-Time Control Capacitor Voltage - V The block diagram in Figure 26 and Figure 27 show the circuit action at the level of an individual pulse (PWM1). First assume that the 5-µs averaged value of I1 = I2. In this case, the PWM modulator terminates at VDAC, and the normal pulse width is delivered to the system. PWM (Low) PWM (Nom) PWM (High) I1 < 12 VDAC I1 > 12 PWM1 Output Pulse t - Time - ms UDG-08007 Figure 27. Current Sharing Operation 21 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51727 TPS51727 SLUS806A – APRIL 2008 – REVISED MAY 2008 .............................................................................................................................................................. www.ti.com If instead, I1 > I2, then an offset is subtracted from VDAC, and the pulse width for phase one is shortened, reducing the current in phase one to compensate. If I1 < I2, then a longer pulse is produced, again compensating on a pulse-by-pulse basis. Because the increase in pulse width is proportional to the difference between the actual phase current and the ideal current, the system converges smoothly to equilibrium. Because the filtering is so much lighter than conventional current sharing schemes, the settling time is very fast. Analysis shows the response to be single pole with a bandwidth in the tens of kHz depending on circuit parameters. Detailed analysis of the current sharing circuit is available upon request. The speed advantage allows the TPS51727 to quickly move from full speed to idle and back to save power when processing light and moderate loads. A multi-phase converter that takes milliseconds to implement current sharing will never be in equilibrium and thermal hot-spots can result. The TPS51727 allows rapid dynamic current and output voltage changes while maintaining current balance. 22 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51727 TPS51727 www.ti.com .............................................................................................................................................................. SLUS806A – APRIL 2008 – REVISED MAY 2008 Overshoot Reduction (OSR™) Feature The problem of overshoot in low duty-cycle synchronous buck converters results from the output inductor having a small voltage (VOUT) with which to respond to a transient load release. In Figure 28, a single phase converter is shown for simplicity. In an ideal converter, with the common values of 12-V input and 1.2-V output, the inductor has 10.8 V (12 V – 1.2 V) to respond to a transient step, and 1.2 V to respond once the load releases. 12 V + – 10.8 V L 1.2 V – 1.2 V + C UDG-08008 Figure 28. Synchronous Converter Figure 29 shows a two-phase converter. The energy in the inductor is transferred to the capacitance on the VOUT node above and the output voltage (green trace) overshoots the desired level (lower cursor, also green). In this case, the magnitude of the overshoot is approximately –40 mV. The LLx waveforms (yellow and blue traces) remain flat during the overshoot, indicating the DRVLx signals are on. The performance of the same dual phase circuit, but with OSR enabled is shown in Figure 30. In this case, the low side FETs shut off when overshoot is detected and the energy in the inductor is partially dissipated by the body diodes. The overshoot is reduced by 20 mV. The dips in the LLx waveforms show the DRVLx signals are OFF only long enough to reduce the overshoot. Figure 29. CIrcuit Performance Without Overshoot Reduction Figure 30. Transient Release Performance Improved with Overshoot Reduction 23 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51727 TPS51727 SLUS806A – APRIL 2008 – REVISED MAY 2008 .............................................................................................................................................................. www.ti.com Implementation OSR is implemented using a comparator between the DROOP and CMP nodes in Figure 1. To implement OSR, simply terminate the OSRSEL pin to the desired voltage to set the threshold voltage for the comparator. The settings are: • GND = Minimum voltage (Maximum reduction) • VREF = Medium voltage • +3.3V = Maximum voltage • 5V = OSR off Use the highest setting that provides the desired level of overshoot reduction to eliminate the possibility of false OSR operation. Light Load Power Saving Features The TPS51727 has several power saving features to provide excellent efficiency over a very large load range. One is the PCNT pin. This pin has a low voltage I/O level which can work with logic signals from 1V to 3.6V. A LO on this pin puts the converter into single phase mode, thus eliminating the quiescent power of phase two when high power is not needed. In addition, the TPS51727 has an automatic pulse skipping "skip" mode. Regardless of the state of the logic inputs, the converter senses negative inductor current flow and prevents it by shutting off the bottom MOSFET(s). This saves power by eliminating recirculating current. When the bottom MOSFET shuts off, the converter enters discontinuous mode, and the switching frequency decreases, thus reducing switching losses as well. The SLP signal is used to enter a low-power state where unnecessary circuitry is powered down to save quiescent current for the lightest load conditions MOSFET Drivers The TPS51727 incorporates a pair of strong, high-performance gate drives with adaptive cross-conduction protection. The driver uses the state of the DRVLx and LLx pins to be sure the top or bottom MOSFET is off before turning the other on. Fast logic and high drive currents (up to 8 A typical!) quickly charge and discharge MOSFET gates to minimize dead-time to increase efficiency. The top gate driver also includes an internal P-N junction bootstrap diode, decreasing the size and cost of the external circuitry. For maximum efficiency, this diode can be bypassed externally by connecting Schottky diodes from V5IN (anode) to VBSTx (cathode). Voltage Slewing The TPS51727 ramps the internal DAC up and down to perform all voltage transitions. The timing is independent of switching frequency, as well as output resistive and capacitive loading. It is set by a resistor from the ISLEW pin to AGND (RSLEW). All voltage transitions have a single slew rate. RSLEW = K SLEW ´ VSLEW SR (3) where • • • KSLEW = 1.25 × 109 VSLEW = 1.25 V SR is the desired slew rate in units of mV/µs VSLEW is equal to the slew reference, VSLEWREF when RSLEW is tied to GND. Connecting RSLEW to VREF disables over-voltage protection (OVP) and changes VSLEW in Equation 3 to 0.45 V (VVREF – VSLEWREF). 24 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51727 TPS51727 www.ti.com .............................................................................................................................................................. SLUS806A – APRIL 2008 – REVISED MAY 2008 The soft start time to the voltage defined by the VID code at power-up is shown in Equation 4. tSS = VVID (s ) SR (4) Soft Stop Control with Low Impedance Output Termination The voltage slewing capability is also used to slowly slew the voltage down for a soft-stop without undershoot. The soft-stop rate equals the soft-start rate. As long as V5IN is available and EN toggles low, the TPS51727 slews from the current VID to 0.3 V. At this point, all DRVxx signals are held LO and an internal transistor connected from VFB to AGND turns on to keep VOUT from floating up as a result of stray leakage currents. Protection Features The TPS51727 features full protection of the converter power chain as well as the system electronics. Input Undervoltage Protection (UVLO) The TPS51727 continuously monitors the voltage on the V5FILT pin to ensure the value is high enough to bias the devices properly and provide sufficient gate drive potential to maintain high efficiency. The converter starts with approximately 4.4 V and has a nominal 200 mV of hysteresis. This function is not latched, therefore removing and restoring 5-V power to the device resets it. The power input (VBAT) does not include a UVLO function, so the circuit runs with power inputs down to approximately 3 × VOUT. Power Good Signals The TPS51727 has an open-drain power good pin, PGOOD. The high threshold is nominally VDAC +200 mV; the low threshold is nominally VDAC –300 mV. PGOOD goes inactive as soon as the EN pin is pulled low or an undervoltage condition on VOUT is detected. It is masked during DAC transitions to prevent false triggering during voltage slewing. When overvoltage protection is turned off, PGOOD continues to indicate an overvoltage condition. Output Overvoltage Protection (OVP) In addition to the power good function described above, the TPS51727 has additional OVP and UVP thresholds and protection circuits. An OVP condition is detected when VOUT is greater than 200 mV greater than VDAC. In this case, the converter sets PGOOD signal inactive, performs the soft-stop sequence, and then latches OFF. The converter remains in this state until the device is reset by cycling either V5IN or EN. However, because of the dynamic nature of the processor systems, the +200mV OVP threshold is “blanked” much of the time. In order to provide protection to the processor 100% of the time, there is a second OVP level fixed at 1.7 V which is always active. If the fixed OVP condition is detected, PGOOD is forced inactive and the DRVLx signals are driven HI. The converter remains in this state until either V5IN or EN are cycled. OVP is disabled when the RSLEW is terminated to VREF instead of GND. In this case, change the value of RSLEW as described in the Voltage Slewing section above. Ouptut Undervoltage Protection (UVP) Output undervoltage protection works in conjunction with the current protection described below. If VOUT drops below the low PGOOD threshold for 80 µs, then the converter enters soft-stop mode and latches OFF at the completion of soft stop. 25 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51727 TPS51727 SLUS806A – APRIL 2008 – REVISED MAY 2008 .............................................................................................................................................................. www.ti.com Current Protection Two types of current protection are provided in the TPS51727. • Overcurrent protection (OCP) • Negative overcurrent protection Overcurrent Protection (OCP) The TPS51727 uses a valley current limiting scheme, so the OCP set point is the OCP limit minus half of the ripple current. Current limiting occurs on a phase-by-phase and pulse-by-pulse basis. If the sensed current value is above the OCP setting, the converter holds off the next ON pulse until the current ramp drops below the OCP limit. Refer to the Electrical Characteristics table to choose the appropriate TRIPSEL value. In OCP, the voltage droops until the UVP limit is reached. Then, the converter sets PGOOD signal inactive, performs the soft-stop sequence, and then latches OFF. The converter remains in this state until the device is reset. Negative Overcurrent Protection The negative OCP circuit acts when the converter is sinking current. The converter continues to act in a valley mode, so to have a similar negative DC limit, the absolute value of the negative OCP set point is typically 50% higher than the positive OCP set point. Thermal Protection Two types of thermal protection are provided in the TPS51727 • Thermal flag open drain ouptut signal (THAL) • Thermal shutdown Thermal Flag Open Drain Ouptut Signal THAL The THAL signal is an open-drain signal that is used to protect the VOUT power chain. To use THAL, place an NTC thermistor at the hottest area of the PC board and connect it to the THRM pin. THRM sources a precise 60-µA current, and THAL goes LO when the voltage on THRM reaches 0.72 V. Therefore, the NTC thermistor needs to be 11.7 kΩ at the trip level. A series or parallel resistor can be used to trim the resistance to the desired value at the trip level. THAL causes the processor to draw less current. The TPS51727 continues to operate normally. Thermal Shutdown The TPS51727 includes an internal temperature sensor. When the temperature reaches a nominal 160°C, the device shuts down until the temperature cools approximately 10°C and the EN pin or 5-V power is recycled. Power Monitor The TPS51727 includes a power monitor function. The power monitor puts out an analog voltage proportional to the output power on the PMON pin. VPWRMON = KPWR ´ VDAC ´ å VCS (5) In Equation 5 KPWR is given in the Electrical Characteristics table and Σ VCS is the sum of the voltages at the inputs to the current sense amplifiers. Power Sequencing The TPS51727 is not sensitive to power sequencing if the EN pin comes up after all other voltages have settled. If EN is tied to 3.3 V without being controlled by a logic signal, 5 V must come up first. The VID lines must be valid within 10 µs of the time when EN goes high. 26 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51727 TPS51727 www.ti.com .............................................................................................................................................................. SLUS806A – APRIL 2008 – REVISED MAY 2008 VID TABLE Table 3. VID TABLE EN VID VDAC (V) –3% Offset 4 3 2 1 0 1 0 0 0 0 0 1.250 1 0 0 0 0 1 1.225 1 0 0 0 1 0 1.200 1 0 0 0 1 1 1.175 1 0 0 1 0 0 1.150 1 0 0 1 0 1 1.125 1 0 0 1 1 0 1.100 1 0 0 1 1 1 1.075 1 0 1 0 0 0 1.050 1 0 1 0 0 1 1.025 1 0 1 0 1 0 1.000 1 0 1 0 1 1 0.975 1 0 1 1 0 0 0.950 1 0 1 1 0 1 0.925 1 0 1 1 1 0 0.900 1 0 1 1 1 1 0.875 1 1 0 0 0 0 0.850 1 1 0 0 0 1 0.825 1 1 0 0 1 0 0.800 1 1 0 0 1 1 0.775 1 1 0 1 0 0 0.750 1 1 0 1 0 1 0.725 1 1 0 1 1 0 0.700 1 1 0 1 1 1 0.675 1 1 1 0 0 0 0.650 1 1 1 0 0 1 0.625 1 1 1 0 1 0 0.600 1 1 1 0 1 1 0.575 1 1 1 1 0 0 0.550 1 1 1 1 0 1 0.525 1 1 1 1 1 0 0.500 1 1 1 1 1 1 0.400 0 X X X X X 0.000 27 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51727 TPS51727 SLUS806A – APRIL 2008 – REVISED MAY 2008 .............................................................................................................................................................. www.ti.com APPLICATION INFORMATION Design Procedure The following section describes a very simple design procedure for the TPS51727, as a high-performance dual phase power controller. Choosing Initial Parameters Step One Determine the output requirements. For the purposes of this document, we use the following parameters for the design procedure. The processor requirements provide the following key parameters. • VOUT(max) = 1.05 V • ROUT = -1.0 mΩ • IMAX = 40 A • IDYN = 30 A • Slew rate = 5.0 mV/µs (minimum) The TPS51727 architecture is designed to work with a load line defined by ROUT. The output voltage drops by an accurately defined amount as the output current increases. The minimum supported load-line is –1.0mΩ. Step Two Determine system parameters. The input voltage range and operating frequency are of primary interest. For example: 1. VIN(max) = 15 V 2. VIN(min) = 8 V 3. f = 300 kHz Step Three Determine current sensing method. The TPS51727 supports both resistor sensing and inductor DCR sensing. Inductor DCR sensing is chosen. For resistor sensing, substitute the resistor value (1 mΩ recommended for a 40-A application) for RCS in the subsequent equations and skip Step Four. Step Four Determine inductor value and choose inductor. Smaller values of inductor have better transient performance but higher ripple and lower efficiency. Higher values have the opposite characteristics. It is common practice to limit the ripple current to 30% to 50% of the maximum current per phase. In this case, use 40%. IP -P = 40 A ´ 0.4 = 8.0 A 2 phases (6) At f = 300 kHz, with a 15-V input and a 1.05-V output: LMAX = V ´ dT IP-P (8) where • V = VIN(max) – VOUT(max) dT = VOUT(max ) f ´ VIN(max ) (7) LMAX = 0.406 µH 28 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51727 TPS51727 www.ti.com .............................................................................................................................................................. SLUS806A – APRIL 2008 – REVISED MAY 2008 To allow for inductor tolerances, 0.36 µH is chosen. The inductor must not saturate during peak loading conditions. æ I ö I ISAT = ç MAX + P-P ÷ ´ 1.5 = 36 A 2 ø è NPHASE (9) The factor of 1.5 allows for current sensing and current limiting tolerances. The chosen inductor should have the following characteristics:. 1. Create an inductance vs. current curve that is as flat as possible. Inductor DCR sensing is based on the idea L/DCR is approximately a constant through the current range of interest. 2. Either high saturation or “soft saturation”. 3. Low DCR for improved efficiency, but at least 0.7 mΩ for proper signal levels. 4. DCR tolerance as low as possible for load-line accuracy. For this application, a 0.36-µH, 1.2-mΩ inductor is chosen Step Five Design the thermal compensation network. In most designs, NTC thermistors are used to compensate thermal variations in the resistance of the inductor winding. This winding is generally copper, and so has a resistance coefficient of 3900 PPM/C. NTC thermistors, on the other hand, have very non-linear characteristics and need two or three resistors to linearize them over the range of interest. The typical DCR circuit is shown in Figure 31. L RSEQU RDCR RNTC I RSERIES RPAR CSENSE CSP CSN UDG-07188 Figure 31. Typical DCR Sensing Circuit In this circuit, good performance is obtained when: L RDCR = CSENSE ´ REQ (10) In Equation 10, all of the parameters are defined in Figure 26 except REQ, which is the series/parallel combination of the other four discrete resistors. CSENSE should be a capacitor type which is stable over temperature; use X7R or better dielectric (C0G preferred). 29 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51727 TPS51727 SLUS806A – APRIL 2008 – REVISED MAY 2008 .............................................................................................................................................................. www.ti.com Since calculating these values by hand is difficult, TI has a spreadsheet using the Excel "Solver" function available to calculate them. Please contact your local TI representative to get a copy of the spreadsheet. In • • • • the reference design, the following values are input to the spreadsheet:: L RDCR Load Line (ROUT) Thermistor R25 and "b" value The spreadsheet then calculates RSEQU, RSERIES, RPAR, and CSENSE. In this case, the nearest standard values are: • RSEQU = 24.9 kΩ • RSERIES = 43.2 kΩ • RPAR = 165 kΩ • CSENSE =18 nF Note the effective divider ratio for the inductor DCR. The effective current sense resistance, RCS(eff) is shown in Equation 11. æ RP _ N R CS (eff ) = RDCR ´ ç ç R SEQU + RP _ N è ö ÷ ÷ ø (11) Step Six Determine the output capacitor configuration. This depends on the transient specification of the load. If ROUT is high enough, the transient specification can be met within the DC load-line. A successful design includes a combination of bulk and ceramic capacitance totaling at least 1200 µF. Step Seven Set the load line. The load line is set by the droop resistor knowing ROUT and RCS(eff). RDROOP = RCS(eff ) ´ A CS GM ´ ROUT (12) RDROOP = 11.0 kΩ Step Eight Calculate the droop capacitance. From Equation 13 . CDROOP = ROUT ´ IDYN ´ GM ´ L - 30pF = 50pF RCS ´ A CS ´ DMAX ´ V (L ) (13) The next smaller standard value, 47 pF, is chosen. Step Nine Calculate RSLEW. RSLEW sets the rate for all transitions including: 1. Start-up slew rate 2. Shutdown slew rate 3. VID change slew rate (+ or –) RSLEW = K SLEW ´ VSLEW SR (14) Here, the OVP is enabled, so RSLEW is terminated to GND. KSLEW = 1.25 × 109 and VSLEW = 1.25 V. For a slew rate (SR) of 5.0 mV/µs, RSLEW = 312.5 kΩ. 30 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51727 TPS51727 www.ti.com .............................................................................................................................................................. SLUS806A – APRIL 2008 – REVISED MAY 2008 Step Ten Calculate THAL components. The THRM pin puts out a nominal 60-µA current. The trip voltage is 0.75 V. Therefore, the resistance at the trip point needs to be 0.75 V / 61 µA = 12.3 kΩ. For a trip temperature of 85°C, the recommended 150 kΩ NTC thermistor is 10.3 kΩ. To move the trip point to the correct resistance, we add a series resistance of 2.0 kΩ. Depending on the thermistors selection and desired trip point, adding a parallel resistance to obtain the correct resistance at the trip point is also possible. In order to keep the sensing as accurate as possible in both cases, the contribution of the fixed resistance at the trip point should be as small as possible. If THAL is not used, leave both THAL and THRM open. Step Eleven Select decoupling and peripheral components. For TPS51727 peripheral capacitors, use the following minimum values of ceramic capacitance. X5R or better temperature coefficient is recommended. Tighter tolerances and higher voltage ratings are always OK. • V5IN decoupling ≥ 2.2µF, ≥ 10V • V5FILT decoupling ≥ 1µF≥10V • VREF decoupling 0.22µF to 1µF, ≥ 4V • Bootstrap capacitors ≥ 0.22µF, ≥ 10V • Bootstrap diodes (optional) 30-V Schottky diode, BAT-54 or better • PMON filter, 10 kΩ, 5% resistor / 10 nF 20% capacitor • Pull-up resistors. Use a 10-kΩ, 5% resistor, or as system requirements dictate. For power chain and other component selection, see Table 1. 31 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51727 TPS51727 SLUS806A – APRIL 2008 – REVISED MAY 2008 .............................................................................................................................................................. www.ti.com Layout Guidelines The TPS51727 has fully differential current and voltage feedback. As a result, no special layout considerations are required. However, all high-performance multi-phase power converters, like the , require a certain level of care in layout. Schematic Review Because the voltage and current feedback signals are fully differential it is a good idea to double check their polarity. • CSP1/CSN1 • CSP2/CSN2 • VFB/GFB Specific Guidelines Separate Noisy Driver Interface Lines from Sensitive Analog Interface Lines ISLEW OSRSEL TONSEL TRIPSEL PMON EN N/C SLP PGOOD Control Interface V5FILT The TPS51727 makes this as easy as possible, as the two sets of pins are on opposite sides of the device. In addition, the CPU interface signals are grouped on the top and bottom sides of the device. This arrangement is shown in Figure 32. 40 39 38 37 36 35 34 33 32 31 Logic Interface #2 DROOP 1 30 DRVH1 VREF 2 29 VBST1 GND 3 28 LL1 CSP1 4 Sensitive Analog CSN1 5 Interface CSN2 6 27 DRVL1 26 V5IN TPS51727 RHA PACKAGE 25 Driver PGND Interface CSP2 7 24 DRVL2 GFB 8 23 LL2 VFB 9 22 VBST2 21 DRVH2 DACS 17 18 19 20 VID0 PCNT 16 VID1 PD1 15 VID2 14 VID3 13 PD2 12 VID4 11 THAL THRM 10 Logic Interface #1 UDG-08010 Figure 32. Device Layout by Pin Function 32 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51727 TPS51727 www.ti.com .............................................................................................................................................................. SLUS806A – APRIL 2008 – REVISED MAY 2008 Given the physical layout of most systems, the current feedback (CSPx, CSNx) may have to pass near the power chain. Clean current feedback is required for good load-line, current sharing, and current limiting performance of the TPS51727. This requires the designer take the following precautions. • Make a Kelvin connection to the pads of the resistor or inductor used for current sensing. See Figure 33 for a layout example. • Lay out the current feedback signals as a differential pair to the device. • Lay out the lines in a quiet layer. Isolate them from noisy signals by a voltage or ground plane. • Design the compensation capacitor for DCR sensing (CSENSE) as close to the CS pins as possible. • Design RPAR next to CSENSE. • Design any noise filtering capacitors directly under the TPS51727 and connect to the CS pins with the shortest trace length possible. • The ISLEW pin is susceptible to high frequency noise. Design the trace lengths to the slew resistor as short as possible and surround the pin and resistor with a guard ring of a quiet trace (analog ground is preferred). Noisy Quiet Inductor Outline LLx VOUT CSNx CSPx RSEQ Thermistor RSERIES UDG-08011 Figure 33. Make Kelvin Connections to the Inductor for DCR Sensing • • • • • Ensure that all vias in the CSPx and CSNx traces are isolated from all other signals Lay out the dotted signal traces in internal planes If possible, change the name of the CSNx trace to prevent unintended connections to the VOUT plane Design CSPx and CSNx as a differential pair in a quiet layer Design the capacittor as near to the device pins as possible 33 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51727 TPS51727 SLUS806A – APRIL 2008 – REVISED MAY 2008 .............................................................................................................................................................. www.ti.com Minimize High Current Loops Figure 34 shows the primary current loops in each phase, numbered in order of importance. The most important loop to minimize the area of is Loop 1, the path from the input capacitor through the high and low-side MOSFETs, and back to the capacitor through ground. VBAT CB CIN 1 Q1 4b DRVH L 4a VOUT LL 2 3b Q1 CD COUT DRVH 3a PGND UDG-08012 Figure 34. Major Current Loops Requiring Minimization Loop 2 is from the inductor through the output capacitor, ground and Q2. The layout of the low-side gate drive (Loops 3a and 3b) is important. The guidelines for gate drive layout are: • Make the low side gate drive as short as possible (1 inch or less preferred). • Make the DRVL width to length ratio of 1:10, wider (1:5) if possible • If changing layers is necessary, use at least two vias A sample breakout of the driver side of the device is shown in Figure 35. Figure 35. Recommended Gate Drive Section Breakout 34 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51727 TPS51727 www.ti.com .............................................................................................................................................................. SLUS806A – APRIL 2008 – REVISED MAY 2008 Power Chain Symmetry The TPS51727 does not require special care in the layout of the power chain components, because independent isolated current feedback is provided. Make every effort to lay out the phases in a symmetrical manner. The current feedback from each phase must be free of noise and have the same effective current sense resistance. Place Analog Components as Close to the Device as Possible Place components close to the device in the following order. 1. CS pin noise filtering components 2. DROOP pin compensation component 3. Decoupling capacitor 4. ISLEW resistor (RSLEW) Grounding Recommendations The TPS51727 has separate analog and power grounds, and a thermal pad. The normal procedure for connecting these is: 1. Connect the thermal pad to PGND. 2. Tie the thermal pad to the system ground plane with at least 4 small vias or one large via. 3. GND can be connected to any quiet space. A quiet space is defined as a spot where no power supply switching currents are likely to flow. This applies to all switching converters on the same board. Use a single point connection to the point, and pour a GND island around the analog components. 4. Make sure the bottom MOSFET source connection and the decoupling capacitors have plenty of vias. Decoupling Recommendations • Decouple V5 to PGND with at least a 2.2-µF ceramic capacitor. This fits best on the opposite side of the device. • Use double vias to connect to the device. • Decouple V5FILT with 1-µF to AGND with leads as short as possible. • Decouple VREF to AGND with 0.22-µF, with short leads as short as possible. Conductor Widths • Maximize the widths of power, ground and drive signal connections. • For conductors in the power path, be sure there is adequate trace width for the amount of current flowing through the traces. • Make sure there are sufficient vias for connections between layers. • Use a minimum of 1 via per ampere of current 35 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51727 PACKAGE OPTION ADDENDUM www.ti.com 5-May-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS51727RHAR ACTIVE QFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS51727RHAT ACTIVE QFN RHA 40 250 CU NIPDAU Level-2-260C-1 YEAR Green (RoHS & no Sb/Br) Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 5-May-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS51727RHAR QFN RHA 40 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2 TPS51727RHAT QFN RHA 40 250 180.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 5-May-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS51727RHAR QFN RHA 40 2500 346.0 346.0 33.0 TPS51727RHAT QFN RHA 40 250 190.5 212.7 31.8 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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