ETC R65C51P2

R65C51
ASYNCHRONOUS COMMUNICATIONS
PRELiMlNARY
DESCRIPTION
FEATURES
The Rockwell CMOS R65C51 Asynchronous Communications
Interface Adapter (ACIA) provides an easily implemented, program controlled interface between 8-bit microprocessor-based
systems and serial communication data sets and modems.
Low power CMOS N-well silicon gate technology
Direct replacement for NMOS R6551 ACIA
Full duplex operation with buffered receiver and transmitter
Data set/modem control functions
Internal baud rate generator
rates (50 to 19,200)
The ACIA has an internal baud rate generator. This feature eliminates the need for multiple component support circuits, a crystal
being the only other part required. The Transmitter baud rate
can be selected under program control to be either 1 of 15 different rates from 50 to 19,200 baud, or at l/16 times an external
clock rate. The Receiver baud rate may be selected under program control to be either the Transmitter rate, or at l/16 times
the external clock rate. The ACIA has programmable word
lengths of 5, 6, 7, or 8 bits; even, odd, or no parity; 1, 1'12, or
2 stop bits.
The ACIA is designed for maximum programmed
the microprocessor (MPU), to simplify hardware
tion. Three separate registers permit the MPU to
the R65C51’s operating modes and’ data checking
and determine operational status.
with 15 programmable
bau
.
Program-selectable
rate
.
Programmable word lengths, number of stop bits, and pant
bit generation and detection
Programmable
internally or’externally controlled receive
interrupt control
Program reset
Program-selectable
serial echo mode
Two chip selects
1 or 2 MI-Q operation
control from
implementaeasily select
parameters
5.0 Vdc t 5% supply requirements
28-pin plastic or ceramic DIP
Full TTL compatibility
Compatible
processors
The Command Register controls parity, receiver echo mode,
transmitter interrupt control, the state of the RTS line, receiver
interrupt control, and the state of the DTR line.
with.
R6500,
R6500/’
and
R65COO micro-
The Control Register controls the number of stop bits, word
length, receiver clock source, and baud rate.
-The Status Register indicates the states of the IRQ, DSR, and
DCD lines. Transmitter and Receiver Data Registers, and
Overrun, Framing, and Parity Error conditions,
The Transmitter and Receiver Data Registers are used for temporary data storage by the ACIA Transmit and Receiver circuits.
ORDERING
INFORMATION
Part No.: R65C51
Temperature Range (TL to TH):
Blank = 0% to +70°C
E= -40% to +85%
-
Frequency Range:
1 = 1 MHz
2 = 2 MHz
Package:
C = Ceramic
P = Plastic
Figure 1.
Document
No. 29651 N60
R65C51 AClA Pin Configuration
Product
2-296
Description
Order No. 2157
Rev. 3, October 1984
Asynchronous Communications. Interface Adapter (ACIA)
RGSCEi’O
I
I
1
I
;
>
__c
,
&
t
TRANSMIT ’
DATA
REGISTER
STATUS
REGISTER
a
cI
CONTROL
REGISTER
cc
COMMAND
REGISTER
a
1
RSl ------
$2
TIMING
1
RES
>
.
*
+
’
__)
TxD
DSR
l
N
RxC
’ BAUD
-XTLt
c RATE
GENERATOR __c
XTl_O
L
tDTR
,RTS
RECEIVE
SHIFT
REGISTER
REGISTER
RxD
RECEIVE
CONTROL
1
TIMING AND CONTROL
The Timing and Control logic controls the timing of data transfers on the internal data bus and the registers, the Data Bus
Buffer, and the microprocessor data bus, and the hardware
reset features.
in Figure 2 followed
element of the device.
DATA BUS BUFFERS
The Data Bus Buffer interfaces the system data lines to the interIal data bus. The Data Bus Buffer is bidirectional.
When the
%i? line is low and the chip is selected, the Data Bus Buffer
.vntes the data from the system data lines to the ACIA internal
zata bus. When the Rfi line is high and the chip is selected,
:?e Data Bus Buffer drives the data from the internal data bus
‘3 the system data bus.
INTERRUPT
*
ACIA Internal Organization
FUNCTIONAL DESCRIPTION
: block diagram of the ACIA is presented
zy a descrtption of each functional
CTS
Dcd
I
Figure 2.
TRANSMIT
SHIFT
REGISTER
4p
t
L
TRANSMIT
CONTROL lI
Timing is controlled by the system 82 clock input. The chip WIII
perform data transfers to or from the microcomputer data bus
during the $2 high period when selected.
All registers will be initialized by the Timing and Control Logic
when the Reset (m)
line goes low. See the individual register
description for the state of the registers following a haraware
reset.
LOGIC
The Interrupt Logic will cause the IRQ line to the microprocessor
‘3 50 low when conditions are met that require the attention of
:ne mlcroprocessor. The conditions which can cause an inter‘uot will set bit 7 and the appropriate bit of bits 3 through 6 in
:ne Status Register, if enabled. Bits 5 and 6 correspond to the
3ata Carrier Detect (DCD) logic and the Data Set Ready (DSR)
ogle. Bits 3 and 4 correspond to the Receiver Data Register full
3na the Transmitter Data Register empty conditions. These conXons can cause an interrupt request if enabled by the Com-and Register.
TRANSMllTER
AND RECEIVER DATA REGISTERS
These registers are used as temporary data storage for the
ACIA Transmit and Receive Circuits. Both the Transmitter and
Receiver are selected by a Register Select 0 (RSO) and Register
Select 1 (RSl) low condition. The Read/Write (R/m) line determines which actually uses the internal data bus: the Transmitter
Data Register is write only and the Receiver Data Register 1s
read only.
Bit 0 is the first bit to be transmitted from the Transmttter Data
Register (least significant bit first). The higher order bits follow
in order. Unused bits in this register are “don’t care”.
110 CONTROL
The IO Control Logic controls the selectlon of internal registers
‘n Preparation for a data transfer on the Internal data bus and
!he direction of the transfer to or from the register.
The Receiver Data Regtster holds the first received data bit In
bit 0 (least significant bit first). Unused high-order bits are “0”.
Parity bits are not contained in the Receiver Data Register. They
are stripped off after being used for parity checking.
The registers are selected by the Receiver Select (RSl, RSO)
and Read Write (R/w) lines as described later in Table 1.
2-297
R&C51
Asynchronous Communications Interface Adapter (ACIA
Parity Error (Bit 0), Framing Error (Bit l), and
Overrun (2)
STATUS REGISTER
The Status Register indicates the state of interrupt conditions
and other non-interrupt status lines. The interrupt conditions are
the Data Set Ready, Data Carrier Detect, Transmitter Data Register Empty and Receiver Data Register Full as reported in bits
6 through 3, respectively. If any of these bits are set, the Interrupt (IRQ) indicator (bit 7) is also set. Overrun, Framing Error,
and Parity Enor are also reported (bits 2 through 0 respectively).
7
6
5
IRG
DSR
DCD
4
3
2
1
0
FE
PE
t
TDRE RDRE OVRN
None of these bits causes a processor interrupt to occur, t
they are normally checked at the time the Receiver Data Re
ister is read so that the validity of the data can be verified. The
bits are self clearing (i.e., they are automatically cleared at:
a read of the Receiver Data Register).
,
Receiver Data Register Full (Bit 3)
This bit goes to a 1 when the ACIA transfers data from :’
Receiver Shift Register to the Receiver Data Register. and go.
to a 0 (is cleared) when the processor reads the Receiver D;
Register.
4
Bit 7
0
1
Interrupt (IRQ)
No interrupt
Interrupt has occurred
Bit 6
0
1
Data Set Ready (DSR)
DSR low (ready)
DSR high (not ready)
Bit 5
0
1
Data Carrier Detect (DCD)
Bit 4
0
1
Transmitter
Not empty
Bit 3
0
1
Receiver Data Register Full
Not full
Full
Bit 2
0
1
Overrun*
No overrun
Overrun has occurred
Bit 1
0
1
Framing Error’
No framing error
Framing error detected
Bit 0
0
1
Parity Error*
No parity error
Parity error detected
Transmitter
Data Register Empty (Bit 4)
This bit goes to a 1 when the ACIA transfers data from tr
Transmitter Data Register to the Transmitter Shift Register, ar
goes to a 0 (is cleared) when the processor writes new daonto the Transmitter Data Register.
DCD low (detected)
DCD high (not detected)
Data Register Empty
Data Carrier Detect (Bit 5) and Data Set Ready
(Bit 6)
Empty
These bits reflect the levels of the DCD and DSR inputs to tt
ACIA. A 0 indicates a low level (true condition) and a 1 indicate
a high level (false). Whenever either of these inputs chant
state, an immediate processor interrupt (IRQ) occurs. unless :
1 of the Command Register (IRD) is set to a 1 to disable IR(
When the interrupt occurs, the status bits indicate the levels
the inputs immediately after the change of state occurred. SL
sequent level changes will not affect the status bits until t’
Status Register is interrogated by the processor. At that tirr
another interrupt will immediately occur and !he status !I
reflect the new input levels. These bits are not automatica
cleared (or reset) by an internal operation.
Interrupt (Bit 7)
‘No interrupt occurs for these conditions
This bit goes to a 1 whenever an interrupt condition occurs ar
goes to a 0 (is cleared) when the Status Register IS read.
Reset initialization
76543210
0 -1-I
-
-/-(-
1
1
0
0
-
0 -
0
0
Hardware reset
_ ’ Program reset
2-298
m
-
Asynchronous Communications Interface Adapter (ACIA)
R65C5 1
CONTROL REGISTER
Selected Baud Rate (Bits 0, 1, 2, 3)
Y
These bits select the Transmitter baud rate, which can be at
‘I16 an external clock rate or one of 15 other rates controlled by
the internal baud rate generator.
antrot Register
selects the desired baud rate, frequency
word length, and the number of stop bits.
-.
7
5
6
4
3
2
c
WLl
0
.
If the Receiver clock uses the same baud rate as the transmitter,
then RxC becomes an output and can be used to slave other
circuits to the ACIA. Figure 3 shows the Transmitter and Receiver
layout.
S8R
WL
SBN ’
1
1 RCS
SBR3 SBR2 SBRl SBRO
WLO
\
Stop Bit Number (SBN)
1 Stop bit
2 Stop bits
I 1:~Stop bits
For WL = 5 and no parity
1 Stop bit
For WL = 8 and parity
Bit 7
?
i
.
.
:
I
RECEIVER
I-_r
SHIFT REGISTER
1
Bits 6-5
_
‘3
3
3
.
.
r
-?
1
0
1
Word Length
No. Bits
8
7
6
5
(WL)
Receiver Clock Source
External receiver clock
Baud rate
Bit 4
0
1
.
*
0
0
9
:
1
1
7
1
0
0
0
0
1
?
1
1
1
1
1
1
t
4
CLOCK
DIVIDER e
(16)
SYNC
LOGIC
‘
RxC
(RCS)
BIT 4
XTU C
XTLOC
Bits 3-o
3
2
-Ti0
0
0
0
0
0
0
3
1
0
1
RxD
J
Selected Baud Rate (SBR)
1
0
Baud
0
016x
0
1
50
1
0
75
1
1
109.92
0
0
134.58
0
1
150
1
0
300
1
1
600
0
0
1200
0
1
1800
1
0
2400
1
1
3600
0
0
4800
0
1
7200
1
0
9600
1
1
19.200
.
BAUD RATE +
GENERATOR
f
t
t
t,
r;;T;;:”
REGISTER
Figure 3.
CLOCK
DIVIDER
(16)
1
TRANSMITTER
1 SHIFT REGISTER I--
Transmitter/Receiver
TxD
Clock Circuits
Receiver Clock Source (Bit 4)
This bit controls the clock source to the Receiver. A 0 causes
the Receiver to operate at a baud rate of l/16 an external clock.
A 1 causes the Receiver to operate at the same baud rate as
is selected for the transmitter.
Word Length (Bits 5, 6)
?eset Initialization
76543210
o o o o 0 0 0
‘ZJZFQ$j
These bits determine the word length to be used (5, 6, 7 or 8
bits).
0
Hardware reset (i%%)
Stop Bit Number (Bit 7)
Program reset
This bit determines the number of stop bits used. A 0 always
indicates one stop bit. A 1 indicates 1% stop bits if the word
length is 5 with no parity selected, 1 stop bit if the word length
is 8 with parity selected, and 2 stop bits in all other configurations.
2-299
Asynchronous Communications Interface Adapter (ACIA
R65C51
COMMAND
Data Terminal Ready (Bit 0)
REGISTER
This bit enables all selected interrupts and controls the state o*
the Data Terminal Ready (m)
line. A 0 indicates the microcomputer system is not ready by setting the DTR line high. b
1 indicates the microcomputer system is ready by setting the
DTR line low. fi
line low. m
also enables and disables
the transmitter and receiver.
The Command Register controls specific modes and functions.
76543210
TIC
- IRD DTR
PME REM 1
TIC1 TIC0
PNCl PNCO
PMC
Bits 7-6
7
6
‘i;j- 0
0
1
1
0
1
1
Bit 5
0
1
Bit 4
0
1
Bits 3-2
3
2
00
0
1
1
0
1
1
Receiver
Parity Mode Control (PMC)
Transmitter
RTS
RTS
RTS
I?%
=
=
=
=
Interrupt Control (Bits 2, 3)
line an’
Receiver Echo Mode (Bit 4)
A 1 enables the Receiver Echo Mode and a 0 disables the
Receiver Echo Mode. When bit 4 is a 1 bits 2 and 3 must be
0. In the Receiver Echo Mode, the Transmitter returns eact
transmission received by the Receiver delayed by one-half bitime.
will
Parity Mode Enable (Bit 5)
This bit enables parity bit generation and checking. A 0 disable:
parity bit generation by the Transmitter and parity bit checking
by the Receiver. A 1 bit enables generation and checking c
parity bits.
Interrupt Control (TIC)
High, transmitter disabled
Low, transmit interrupt enabled
Low, transmit interrupt disabled
Low, transmit interrupt disabled
transmit break on TxD
Bit 1
0
1
Receiver Interrupt Request Disabled (IRD)
IRQ enabled (receiver)
IRQ disabled (receiver)
Bit 0
0
1
Data Terminal Ready (DTR)
Data terminal
Data terminal
(Bit 1)
These bits control the state of the Ready to Send (m)
the Transmitter interrupt.
Parity Mode Enabled (PME)
Parity mode disabled
No parity bit generated
Parity check disabled
.
Parity mode enabled
Transmitter
Control
This bit disables the Receiver from generating an interrupt whee
set to a 1. The Receiver interrupt is enabled when this bit is SE
to a 0 and Bit 0 is set to a 1.
Odd parity transmitted/received
Even parity transmitted/received
Mark parity bit transmitted
Parity check disabled
Space parity bit transmitted
Parity check disabled
Receiver Echo Mode (REM)
Receiver normal mode
Receiver echo mode bits 2 and 3
Must be zero for receiver echo mode, m
be low.
Interrupt
Parity Mode Control (Bits 6, 7)
These bits determine the type of parity generated by the Trans
mitter, (even, odd, mark or space) and the type of parity chec
done by the Receiver (even. odd, or no check).
Reset Initialization
76543210
I
~olololo~o~o~o~o~
1.
--1-1-t
]ojo~O~O~o,
not ready (m
high)’
ready (fi
low)
NOTE
‘The transmitter is disabled immediately. The receiver is
disabled but will first complete receiving a byte in process
of being received.
2-300
Hardware reset (m)
Program reset
5s
Asynchronous Communications Interface Adapter (ACIA)
Interrupt Request (m)
SIGNALS
NTERFACE
_2. *e-a srows
the ACIA interface signals associated with the
-&zrocessor
and the modem.
The iis1s pin is an interrupt output from the interrupt control logic.
It is an open drain output, permitting several devices to be connected to the common m
microprocessor input. Normally a
high level, m
goes low when an interrupt occurs.
1
a--m
TRANSMIT
DATA &
SHIFT
REGISTERS
cl
-_)
Data Bus (00-07)
The eight data line (DO-D7) pins transfer data between the processor and the ACIA. These lines are bi-directional and are normally high-impedance except during Read cycles when the
ACIA is selected.
TxD
c-OCD
.--iz%
I/O
CONTROL
BAUD
RATE
GENERATOR
Chip Selects (CSO, a)
W
RxC
*
XTLI
--c
XTLO
The two chip select inputs are normally connected to the processor address lines either directly or through decoders. The
ACIA is selected when CSO is high and C%i is low. When the
ACIA is selected, the internal registers are addressed in accordance with the register select lines (RSO, RSl).
62
I
RES
COMMAND
REGISTER
Register Selects (RSO, RSl)
I
C
Figure 4.
ACIA Interface
The two register select lines are normally connected to the processor address lines to allow the processor to select the various
ACIA internal registers. Table 1 shows the internal register
select coding.
Rx0
Diagram
Table 1.
ICROPROCESSOR
eset
Register Operation
INTERFACE
(RES)
mng system initialization a low on the RES input causes a
irdware reset to occur. Upon reset, the Command Register
Id the Control Register are cleared (all bits set to 0). The
atus Register is cleared with the exception of the indications
Data Set Ready and Data Carrier Detect, which are externally
)ntrolled by the DSR and DCD lines, and the transmitter Empty
:. which is set. RES must be held low for one 82 clock cycle
r a reset to occur.
Iput Clock
ACIA Register Selection
RSl
RSO
Rl%ij=Low
L
L
Write Transmit Data
Resister
Rm = High
Read Recewer
Data Reaister
Programmed Reset
l-l
H
Write Control
Register
Read Control
Register
I
(82)
ie input clock is the system 82 clock and clocks all data trans! ‘ers between the system microprocessor and the ACIA.
i Read/Write
Only the Command and Control registers can both be read and
written. The programmed Reset operation does not cause any
data transfer, but is used to clear bits 4 through 0 in the Command register and bit 2 in the Status Register. The Control Register is unchanged by a programmed Reset. It should be noted
that the programmed Reset is slightly different from the hardware Reset (m);
refer to the register description.
(RN)
1 The R/W input. generated by the microprocessor controls the
i direction of data transfers. A high on the FUfi pin allows the
i Xocessor to read the data supplied by the ACIA, a low allows
i a write to the ACIA.
2-301
Asynchronous Communications Interface Adapter (ACIA
R65C51
ACIA/MODEM
Clear to Send (m)
INTERFACE
The Cm input pin controls the transmitter operation. The enabl
state is with CTS low. The transmitter is automatically disable
if CTS is high.
Crystal Pins (XTLI, XTLO)
These pins are normally directly connected to the parallel mode
external crystal (1.8432 MHz) to derive the various baud rates.
Alternatively, an externally generated clock can drive the XTLI
pin, in which case the XTLO pin must float. XTLI is the input
pin for the transmit clock.
Data Terminal Ready (m)
This output pin indicates the status of the ACIA to the moderr
A low on DTR indicates the ACIA is enabled, a high indicate:
it is disabled. The processor controls this pin via bit 0 of the
Command Register.
Transmit Data (TxD)
The TxD output line transfers serial nonreturn-to-zero (NRZ)
data to the modem. The least significant bit (LSB) of the Transmit
Data Register is the first data bit transmitted and the rate of data
transmission is determined by the baud rate selected or under
control of an external clock. This selection is made by programming the Control Register.
Data Set Ready
The m
input pin indicates to the ACIA the status of the
modem. A low indicates the “ready” state and a high, “not.
ready. ”
Data Carrier Detect (DCb)
Receive Data (RxD)
The m
input pin indicates to the ACIA the status of the carrierdetect output of the modem. A low indicates that the modem
carrier signal is present and a high, that it is not.
The RxD input line transfers serial NRZ data into the ACIA from
‘the modem, LSB first. The receiver data rate is either the programmed baud rate or under the control of an externally generated receiver clock. The selection is made by programming
the Control Register.
TRANSMITTER
Continuous
Receive Clock (RxC)
to Send
The m
output pin controls the modem from the processor.
The state of the RTS pin is determined by the contents of the
Command Register.
PROCESSOR
INTERRUPT
(TRANSMIT
REGISTER
CHAR=n+l
CHAR
\
/
\
PROCESSOR.REAOSSTATUS
OATA
EMPTY)
REGISTER,
CAUSES
=n+2
PROCESSOR
MUST
LOAONEWOATA
IN THIS TIME
INTERVAL;
CONTINUOUS
IRO
TO CLEAR
Figure 5.
Data Transmit
The processor must then identify that the Transmit Data Register is ready to be loaded and must then load it with the next
data word. This must occur before the end of the Stop Bit, otherwise a continuous “MARK” will be transmitted. Figure 5 shows
the continuous Data Transmit timing relationship.
(m)
CHAR=n
AND RECEIVER OPERATION
In the normal operating mode, the interrupt request output (m)
signals when the ACIA is ready to accept the next data word to
be transmitted. This interrupt occurs at the beginning of the Start
Bit. When the processor reads the Status Register of the ACIA,
the interrupt is cleared.
The RxC is a bi-directional pin which is either the receiver 16x
clock input or the receiver 16x clock output. The latter mode
results if the internal baud rate generator is selected for receiver
data clocking.
Request
(m)
OTHERWISE,
“MARK”
IS TRANSMITTED
Continuous
2-302
Data Transmit
CHAR
=cn+3
Asynchronous Communications Interface Adapter (ACIA)
-
---
continuous
Data Receive
read the data word before the next interrupt, otherwise the
condition occurs. Figure 6 shows the continuous
Data
Receive Timing Relationship,
5,mliar to the Continuous Data Trasit
case, the normal
Jperatlon of this mode is to assert IRQ when the ACIA has
--led
a full data word. This occurs at about ‘116 point through
:m Stop Bit. The processor must read the Status Register and
CHAR
#
n
PROCISSOR
INtERRUrT
ABOUT
/
*II*1
CHAR
\
Cn*Rpn+3
Sn+2
1
\
OCCURS/
0110
INTO
LAST STOP SIT.
PARITY.
OVERRUN.
AND FRAMING
ERROR
ALSO,
CHAR
OVerWI
\
PROCESSOR
RECEIVER
\
PROCPSIOR
READS
REGISTER.
TO CLEAR
CAUSES
STATUS
TIME
%8
OVERRUN
I
MUST READ
DATA
IN THIS
INTERVAL;
OTblERWISE.
OCCURS
UPOATED
Figure6. Continuous Data Receive
Transmit Data Register Not Loaded by Processor
If the processor is unable to load the Transmit Data Register in
the allocated time, then the TxD line goes to the “MARK” condition until the data is loaded. IRQ interrupts continue to occur
at the same rate as previously, except no data is transmitted.
CONTINUOUS
CHAR#n
TX0
FJz-
,m,
When the processor finally loads new data, a Start Bit immediateiy occurs, the data word transmission is started, and another
interrupt is initiated, signaling for the next data word. Figure 7
shows the timing relationship for this mode of operation.
“MARK”
CHAR
-_
CHARACTER
TIME
,mqq$5f
s:art
So
CklAR
5tn+l
8,
_
I
/
IRa
Iu
,
I
PROCESSOR
INTERRUPT
FOR
DATA
REGISTER
EMPTY
’
,&j
PROCESSOR
READS
NO DATA
IS
TRANSMITTEO
STATUS
REGISTER
NEW DATA,
IMMEDIATELY
TRANShllSSION
STARTS
AND INTERRUPT
OCCURS,
INDICATING
TRANSMIT
DATA
REGISTER
EMPTY
I
Flgure 7.
TransmitDataRegisterNot Loadedby Processor
2-303
Ill
=n+2
Asynchronous Communications Interface Adapter @CIA)
R65C5 1
Effect of CTS on Transmitter
?f% is the Clear-to-Send
normally low (true
modem problems.
MARK” condition
nd stop bit) have
signal generated by the modem. It is
state) but may go high in the event of some
When this occurs, the TxD line goes to the
after the entire last character (including parity
been transmitted. Bit 4 in the Status Register
CHAR
indicates that the Transmitter Data Register is not empty and
i% is not asserted. CTS is a transmit control line only, and has
no effect on the ACIA Receiver Operation. Figure 8 shows the
timing relationship for this mode of operation.
CHAR=n+l
tn
CONTINUOUS
“MARK”
TX0
I
IRQ
f
I n-l
m
IS NOT ASSERTED
AGAIN UNTIL m
NOT
CLEAR-TO-SEND
GOES
‘Ow
t
CLEAR-TO-SEND
Ffs
GOES HIGH.
INDICATING
MODEM
IS NOT READY TO
RE?%ibE
DATA. TxO
GOES TO “MARK”
CONDITION
AFTER COMPLETE
CHARACTER
IS TRANSMITTED.
Figure 8.
c Effect
of Overrun
Effect of CTS on Transmitter
on Receiver
lf the processor does not read the Receiver data Register in the
; allocated time, then, when the following interrupt occurs, the
’ new data word is not transferred to the Receiver Data Register,
CHARfin+
CHAR=n
Rx0
but the Overrun status bit is set. Thus, the Data Register will
contain the last valid data word received and all following data
is lost. Figure 9 shows the timing relationship for this mode.
CHAR
=n+2
CHAR
~,~~,~I~lr~
PROCESSOR
INTERRUPT
FOR RECEIVER
DATA
FULL
\
PROCESSOR
RECEIVER
REGISTER
PREVIOUS
REGISTER
BIT SET
I
REGISTER
DATA,
OVERRUN
IN STATUS
REGISTER
OVERRUN
STATUS
Figure 9.
DATA
NOT UPDATED.
BECAUSE
PROCESSOR
DID NOT READ
Effect of Overrun on Receiver
StT
SET
REGISTER
IN
In+3
RfjSCSf
EcnoMode
Asynchronous Communications Interface Adapter (ACIA)
Timing
p 2_w a,!oce.the TxD line re-transmits the data on the RxD
xoaved by ‘? of the bit time, as shown in Figure 10.
-.
112 DATA
BIT
DELAY
Figure 10.
Effect
Echo Mode Timing
of CTS on Echo Mode Operation
‘n Echo Mode, the Receiver operation is unaffected by m,
qowever. the Transmitter is affected when CTS goes high, i.e.,
:he TxD line immediately goes to a continuous “MARK” con31t!on. In this case, however, the Status Request indicates that
CHAR#n+l
CHAR#tn
Rx0
the Receiver Data Register is full in response to an R,
so the
processor has no way of knowing that the Transmitter has
ceased to echo. See Figure 11 for the timing relationship of this
mode.
CHARtin+
CHARtin+
$‘l~~l:_I~,~,~
I
III
I
I
I III
t
I III
1
NOTCLEAR-TO-SENO
I
I
J
I
CONTINUOUS
1
TxO
p
Ist&=tl
S,,
1 S,
1
1 ‘N
1
r
.
‘I
.
/
“MARK”
I
I
..
P
3
GOES
TO
“FALSE”
CONDITION
-
NORMAL
RECEIVER
DATA
REGISTER
FULL
INTERRUPTS
Figure 11.
Effect of CTS on Echo Mode
2-305
t
UNTIL
I
Ffs
GOES
I
1
I
LOW
,
\
a
R65CSl
Asynchronous Communications Interface Adapter (ACM
Overrun in Echo Mode
If Overrun occurs in Echo Mode, the Receiver is affected the
same way as a normal overrun in Receive Mode. For the retransmitted data, when overrun occurs, the TxD line goes to the
/ i
) I
\
IRQ
“MARK” condition until the first Start Bit after the Receiver Dar
Register is read by the processor. Figure 12 shows the timir
relationship for this mode.
\ nJ
1 RI
1
t
A
b
t
PROCESSOR
INTERRuFT
FOR RECEIVER
OATA
REGISTER
TxO
PROCESSOR
FINALLY
READS
RECEIVER
DATA
REAO
RECEIVER
PROCESSOR
REAOS
STATUS
REGISTER
REGISTER.
LAST VALIO
CHARACTER
(=nb
PROCESSOR
INTERRUPT
FOR CHAR *JI
IN RECEIVER
DATA
REGISTER
OVERRUNOCCURS
TxO GOES
“MARK”
DATA
RESUMES
To
CONDITION
Figure 12.
Overrun in Echo Mode
Framing Error
Framing
received
4 in the
Register
to m,
Error is caused by the absence of Stop Bit(s) on
data. A Framing Error is indicated by the setting of bit
Status Register at the same time the Receiver Data
Full bit is set, also in the Status Register. In response
generated by RDRF, the Status Register can also be
checked for the Framing Error. Subsequent
data words a
tested for Framing Error separately, so the status bit will alwa
reflect the last data word received. See Figure 13 for Framl
Error timing relationship.
RX0
(EXPECTED)
RR0
(ACTUAL)
cl
MISSING
STOP
NOTES:
1.
FRAMING
ERROR
INHISIT
RECEIVER
IF NEXT
DATA
DOES
NOT
OPERATION.
SIT
/
I
PROCESSOR
INTERRUPT,
FRAMING
ERROR
2.
FRAMING
WORD
ERROR
IS OK.
BIT SET
IS CLEARED.
Figure 13.
Framing Error
Asynchronous Communications Interface Adapter (ACIA)
fq6sCSf
gmt
:z
of
J
i
-ccem
_;s;ec:.on
on Receiver
output Indicating the status of the carrier-freclrcult of the modem.
This line goes
Once such a change of state occurs, subsequent transitions will
not cause interrupts or changes in the Status Register until the
first intermpt is serviced. When the Status Register is read by
the processor, the ACIA automatically checks the level of the
DCD line, and if it has changed, another ii% occurs (see Figure
14).
high for
I-arr:er. Normally, when this occurs, the modem will
.- c:ng data some time later. The ACIA asserts IRQ
72
changes state and indicates this condition via
_
*he
Status
Register.
-.Js -9.
, I=Q :!
s
L.5,
-be?
CONTINUOUS
‘MARK”
x
1
’
III--T--
t
NORMAL
t
AS LONG AS
cicD IS HIGH.
PROCESSOR
INTSRRupT
NO INTERRUPT
WILL
PROCESSOR
NO FURTHER
INTERRUPT
INTERRUPTS
PROCESSOR
INTERRUPT
FOR
FOR
RECEIVER
FOR
WILL
OCCUR
GOING
m
HIGH
DC0
GOING
LOW
HERE.
OCCUR
SINCE
RECEIVER
IS NOT
ENAELEO
UNTIL
FIRST START
BIT
PROCESSOR
INTERRUPT
FOR
RECEIVER
DATA
DETECTED
Figure 14.
iming
with
Effect of DCD on Receiver
1% Stop Bits
‘s possible to select 1% Stop Bits, but this occurs only for
.Dlt data words with no parity bit. In this case, the IRQ asserted
r Receiver Data Register Full occurs halfway through the
trailing half-Stop Bit. Figure 15 shows the timing relationship for
this mode.
CHARtin
1x1
CHARC~+I
m-1
m-L
t
PROCESSOR
INTERRUPT
OCCURS
HALFWAY
THROUGHT
THE 112
STOP
Figure 15.
BIT
Timing with 1 l/z Stop Bits
2-307
Asynchronous Communications Interface Adapter (ACIA)
R65C51
Transmit Continuous
“BREAK”
Note
This mode is selected via the ACIA Command Register and
causes the Transmitter to send continuous “BREAK” characters, beginning with the next character transmitted. At least one
full “BREAK” character will be transmitted, even if the processor
quickly re-programs the Command Register transmit mode.
Later, when the Command Register is programmed back to
normal transmit mode, an immediate Stop Bit will be generated
and transmission will resume. Figure 16 shows the timing relationship for this mode.
I
PERIOD
WHICH
-
-
-
If, while operating in the Transmit Continuous “BREAK”
mode, the CTS should go to a high, the TxD will be
overridden by the m
and will go to continuous “MARK”
at the beginning of the next character transmitted after the
CTS goes high.
DURING
PROCESSOR
SELECTS
CONTINUOUS
“BREAK”
POINT
MODE
AT wnlcn
‘PROCESSOR’
PROCESSOR
SELECTS
NORMAL
INTERRUPT
INTERRUPT
NORMAL
TO LOAD
TRANSMIT
TRANSMIT
DATA
MOGE
Figure 16.
Receive Continuous
Transmit Continuous “BREAK”
“BREAK”
shows the
characters.
In the event the modem transmits continuous “BREAK” characters, the ACIA will terminate receiving. Reception will resume
only after a Stop Bit is encountered by the ACIA. Figure 17
-_
RX0
CONTINUOUS
\
I
Sl
rl
-_
timing
relationship
for
continuous
“BREAK”
lsNl
p
lst~pli,,
1
I
I
PROCESSOR
INTERRUPT
FOR
PROCESSOR
BREAK
EVEN
RECEIVER
DATA
REGISTER
GIVE
FULL
AU
AND
INTERRUPT
FRAMING
PARITY
A
CHECK
PARITYERROR
ZEROS
REPRESENT
I
Figure 17.
MORE
INTERRUPTS
WITH
ERROR
WILL
\NOlNTERRUPT
SINCE RECEIVER
DISABLE0 UNTIL
FIRST STOP BIT
SET.
ALSO
BECAUSE
(CONTINUOUS
EVEN
/m-NO--j
BREAK)
PARITY.
Receive Continuous
“BREAK”
I
NORMAL
RECEIVER
INTERFltJPl
“BREAt
a
Asynchronous Communications Interface Adapter (ACIA)
~ATUS
REGISTER
MISCELLANEOUS
OPERATION
*-_2
Z’ r-0 soecial funCtiOnS of the various status bits, there
5 3 st;Sej:eo sequence for checking them. When an interrupt
Lz_‘s.
:“1 XIA
za;c
_..
should
be interrogated,
as follows:
5:&d-’ ‘s Register
Subsequent
-- 3 ,-:era!:on automatically clears Bit 7 (m).
..lrs: crs cn DSR and DCD will cause another interrupt.
sycK
m
(Bit 7) in the data read from the Status Register
1. If Echo Mode is selected, %!? goes low.
2. If Bit 0 of Command
Register (m)
is 0 (disabled), then:
a) All interrupts are disabled, including those caused by
DCD and DSR transitions.
b) Transmitter is disabled immediately.
c) Receiver is disabled. but a character currently being
received will be completed first.
3. Odd parity occurs when the sum of all the 1 bit? in the data
word (including the parity bit) is odd.
. not sel. :he interrupt source is not the ACIA.
4. In the receive mode, the received parity bit does not go into
:?eCK
=c3
the Receiver Data Register, but generates parity error or no
parity error for the Status Register.
and DSR
These must be compared to their previous levels, which must
lave oeen saved by the processor. If they are both 0 (modem
on-line I and they are unchanged then the remaining bits
qust be cnecked.
5. Transmitter
and Receiver may be in full operation simultaneously. This is “full-duplex” mode.
6. If the RxD line inadvertently
Cfieck RDRF (Bit 3)
Check ior Receiver Data Register Full.
Check Parity, Overrun, and Framing Error (Bits O-2) if the
Receiver Data Register is full.
goes low and then high right
after a Stop Bit, the ACIA does not interpret this as a Start
Bit, but samples the line again halfway into the bit to determine if it is a true Start Bit or a false one. For false Start Bit
detection, the ACIA does not begin to receive data, instead,
only a true Start Bit initiates receiver operation.
7. Precautions to consider with the crystal oscillator circuit:
Check TDRE (Bit 4)
ChecK ior Transmitter
Data Register Empty.
If none of the above conditions
gone to the false (high) state.
PROGRAM
RESET
exist, then 5
must have
a) The external crystal should be a “series” mode crystal.
b) The XTALI input may be used as an external clock input.
The unused pin (EXTALO) must be floating and may not
be used for any other function.
8. m
OPERATION
and DSR transitions, although causing immediate processor interrupts, have no affect on transmitter operation.
Data will continue to be sent, unless the processor forces
transmitter to turn off. Since these are high-impedance inputs.
they must not be permitted to float (un-connected). If unused,
they must be terminated either to GND or Vcc.
A program reset occurs when the processor performs a write
speration ro the ACIA with RSO low and RSl high. The program
‘eset operates somewhat different from the hardware reset
$RES pin) and is described as follows:
GENERATION
1. Internal
The internal counter/divider circuit selects the appropriate divisor for the crystal frequency by means of bits O-3 of the AClA
Control Register, as shown in Table 2.
formats
registers are not completely
cleared. Check register
for the effect of a program reset on internal registers.
2. The DTR line goes high immediately.
4. DCD and DSR interrupts are disabled immediately.
If IRQ is
-low and was caused by DCD or DSR. then it goes high, also
5. Overrun
cleared.
If set.
BAUD RATES
Divisors
Generating Other Baud Rates
3. Receiver and transmitter interrupts are disabled immediately.
If IRQ ;s low when the reset occurs. rt stays low until serviced. unless interrupt was caused by DCD or DSR transition.
DCD and DSR status bits subsequently
lines. although no interrupt will occur.
OF NON-STANDARD
will follow the input
By using a different crystal, other baud rates mav be generated.
These can be determined by:
Crystal Frequency
Baud Rate =
Divisor
Furthermore. it is possible to drive the ACIA with an offchIP
oscillator to achieve other baud rates. In this case, XTALI (pin
6) must be the clock input and XTALO (pin 7) must be a noconnect.
Asynchronous Communications Interface Adapter (ACIA)
R65C51-
Table 2
3
2
1
0
0
0
0
0
No Divisor Selected
I
I
/
I
0
0
0
Baud Rete Generated
with a crystal
of Frequency (F)
Baud Rete Genereted
With 1.6432 Mljz
Crtstrl
Dlviaor Selected
For The
Internel Counter
Control
Regieter
Bite
Divisor Selection
I
I
16 x External Clock
at
-. Pin RxC
..-
16 x External Clock
I
F
1.6432 x lad
1
36.064
36,864
= 50
36,864
1.8432 x 106
0
0
1
0
i
24,576
I
24.576
1
I I
II
0
1
1
t
1
f
I
i
1
= 109.92
I
I
I
16,769
I
1
0
1
0
0
= 134.51
13,704
13,704
13.704
1.8432 x 10
0
1
12,288
12,288
0
F
= 150
12,280
F
1.8432 x l@
1
1
0
6,144
6,144
f 300
6,144
1.8432 x 108
0
1
1
1
3,072
F
= 600
3,072
3,072
1.8432 x 106
0
10
0
1,536
1,536
F
= 1,200
1,536
1.6432 x 16
F
= 1,800
L
i
1
ItIlOl1I
I
I
766
l0l0
1
1
I
I
I
I
512
I
I
i
1,024
I
= 2.400
768
I
= 3,600
,
384
!D
i
E
11
1.8432 x 108
1
0
1
256
1
1
1
0
192
1
1
F
= 7,200
1.8432
256x 106
192
256
F
= 9,600
192
F
1.8432 x loa
1
1
1
1
1
96
512
F
1.8432 x 106
384
1
768
F
1.8432 x 10’
512
1.024
F
1.8432 x lO*
= 4,800
I
16,769
F
1.8432 x 106
0
24,576
F
1.8432 x 16
k
I
[
[
1
F
= 75
I
I
0
at Pin RxC
96
= 19,200
I
96
Asynchronous Communications Interface Adapter (ACIA)
&@,osflC LOOP-BACK
ii g-3
i) $.mil _~
:-
-ec
an ACIA
loop-back operation. In this way, the processor can easily perform local loop-back diagnostic testing.
Remote loop-back does not require this circuitry, so LLB must
be set low. However, the processor must select the following:
,=s-Back
_-~_~acK Yom the point of view of the processor.
_le :r,e ,Modem and Data Link must be effectively
--L::ec ?,?a :he ACIA transmitter connected back to
.yYtr~r ~3 fhat the processor can perform diagnostic
-- :l.e system. excluding the actual data channel.
,203-DaCK
’
for a system incorporating
XK diagram
x cesiraole to include in the system a facility for “loop.ss;,rg. =f which there are two kinds:
‘.- +To:e
’
MODES
? =$Lre 18.
_-1.
:
=
OPERATING
Control Register bit 4 must be 1, so that the transmitter clock
equals the receiver clock.
In this
disconits own
checks
Command Register bit 4 must be 1 to select Echo Mode.
Command Register bits 3 and 2 must be 1 and 0, respectively to disable IRQ interrupt to transmitter.
ioop-Back
Command Register bit 1 must be 0 to disable IRQ interrupt
for receiver.
!rom the point of view of the Data Link and
In rhis case, the processor, itself, is disconnected
gc al received data is immediately Tetransmitted, so the
sys;em on rhe other end of the Data Link may operate indexendent of !he local system.
t.@cem.
In this way, the system re-transmits received data without any
effect on the local system.
,
!“?.e XIA
does not contain automatic loop-back operating
;-zces. 3ut they may be implemented with the addition of a
ji,-a:l amount of external circuitry. Figure 19 indicates the necj!ssarl; logic to be used with the ACIA. The LLB line is the pos5.
:* ve-true signal to enable local loop-back operation. Essentially,
‘__3 = nigh does the following:
‘Disables
1. Disables
outputs TxD, fi,
inputs
RxD, z,
MICROPROCESSOR v
and RTS (to Modem).
CTS, DSR (from Modem).
!. Connects
II.e..
transmitter
outputs
TxD to RxD, DTR to m,
w
receiver inputs
to respective
I/O
ATS to m).
MODEM
r-l
I
I
TO DATA LINK
L
:-
LB may be tied to a peripheral control pin (from an R65C21
i
;: r R65C24. for example) to provide processor control of local
f_
Figure 18.
Simplified System Diagram
I
I
j
I
A6551
_-__
--
--Rx0 DC0 CTS DSR
I
*-
I,
1Y
2Y
STB
3Y
4Y -
74157
MODEM
TxD
DTR
SEL
1:
RfS
+5
i
1
NOTES: 1. HIGH ON LLB SELECTS LOCAL LOOP-BACK MODE.
2. HIGH ON 74157 SELECT INPUT GATES “B” INPUTS
-
48
1
,
c
TO “Y” OUTPUTS; LOW GATES “A” TO “Y”.
4A-
I
Figure 19.
Loop-Back Circuit Schematic
3_111
4
L
Asynchronous Communications Interface Adapter (AC
R65C51
READ TIMING DIAGRAM
kzCY
I
Timing diagrams for transmit with external clock, receive with
external clock, and m
generation are shown in Figures 20, 21
and 22, respectively. The corresponding timing characteristics
are listed in Table 3.
I-
XTLI
(TRANSMIT
CLOCK INPUT)
tCH __i
r
j---i
,c-
Table 3.
Transmit/Receive
tCL--
tDD -
Characteristics
TxD ‘K-
NOTE: TxD RATE IS 1116 TxC RATE
Figure 20.
Transmit/Receive
Clock High Time
fcli
175
-
175
-
ns
Transmit/ Receive
Clock Low Time
tCL
175
-
175
-
ns
500
-
500
ns
I 500 I
ns
500
ns
XTLI to TxD
Propagation Delay
RTS
t0D
l
Propagation
-
fmy I - l
500 I -
tlR0
500
Transmit Timing with External Clock
kCY
-
-.tcH
--a
RxC
(INPUT)
1
IF---
tcL---
Delay
IRQ Propagation
Delay (Clear)
-
-
NOTE: Rx0 RATE IS 1116 RxC RATE
Figure 21.
Notes:
[tR. tF = 10 to 30 ns)
Receive External Clock Timing
1
‘The baud rate
with
external
clocking
is:
B&d
Rate =
16 x tccv
*tlRQ’
IRQ
(CLEAR)
Figure 22.
Interrupt and Output Timing
f
Asynchronous
irr;sCSl
CHARACTERISTICS
1 MHz
parameter
-
.
22 :,c:e
Yme
:2 -‘,.se
.Vldth
Set-Up
:c:.5~s
Aold Time
zala
Access
leaa
rold
BUS
%rfve
-
0
-
120
-
tclcw
Hold Time
3~s
tACW
120
Time (Valid Data)
Unit
ns
200
ns
60
-
ns
0
-
ns
60
-
nS
0
-
nS
120
60
-
20
4+W
’
Max
500
0
kwn
3~s Set-Up Time
aeac
400
twcw
Min
-
tc
bAl+
Time
Time
= a.5 -Oq
~3~3
Time
2 MHz
Max
1000
bYC
a:,~
a*,? +I-tip
Mln
Symbol
-
km
Time
b!R
20
Time (Invalid Data)
(CDA
40
200
-
ns
10
-
-
100
10
-
ns
llS
flS
20
ns
Notes:
* v-z = 5.ov iwo.
2. T, = T, to T,.
3. t= ana tr = 10 to 30 ns.
#-
CSO,B,,
VIH
VIH
RSo, AS,
VIL
I
tDCW _!_---
/
tHW--.+i
VIL
tVIH
DATA BUS
VIL
Figure 23.
Write Timing Diagram
/I
I--WCR-
It----
I
tCQR-’
DATA BUS
Figure 24.
Read Timing Characteristics
2-313
“IL
r
q
”
f
i; R65C51
ABSOLUTE
Asynchronous Communications Interface Adapter (ACIA
MAXIMUM
RATINGS’
‘NOTE: Stresses above those listed may cause permaner
damage to the device. This is a stress rating only and functionc
operation of the device at these or any other conditions abov
those indicated in other sections of this document is not implies
Exposure to absolute maximum rating conditions for extende
periods may affect device reliability.
OPERATING CONDITIONS
DC CHARACTERISTICS
(Vcc = 5.OV f5%,
Vss = 0, TA = TL to T”, unless otherwise noted)
I
I
j Input High Voltage
Parameter
Symbol
: Input Low Voltage
! Input Leakage Current:
I
02, Rm. !?i%. CSO. a,
:
j Output High Voltage:
m.
;
1
Vcc
V
VI,
-0.3
-
+0.8
V
fl
f2.5
fi
v,, = ov to vcc
V,, = 5.25V
it2
f10
lLA
V,, = 0.4V to 2.4V
V,, = 5.25V
-
V
RxD, bFB, DSR
-
ITSI
2.4
Output Low Current (Sinking):
--DO-07. TxD, RxC, RTS. DTR. IRQ
IOL
1.6
Output Leakage Current (off state): IRQ
IOFF
02
Output Capacitance
-
v,,
= 4.75v
TBd
-200
Input Capacitance
All except 02
Test Conditlons
-
‘OH
Power Dissipation
Unit
1 ILOAD= -loo
Output High Current (Sourcing):
00-07. TxD, RxC, m.
m
’
Max
2.0
Von
-DO-07, TxD. RxC. RTS. DTR
TYP
VIH
IIN
RSO, RSI. i5fs,
Input Leakage Current (Three State Off)
DO-07
1 Output Low Voltage:
00-07. TxD. RxC. m.
Mln
PO
1 -400
-
-
-
7
-
I
/.A
VOH = 2.4V
-
mA
v,,
10
d
VOuT
10
mW/MHz
-
20
10
PF
PF
-
10
PF
0.4v
=
=
5.0V
vcc = 5.ov
CCLK
GIN
COUT
Notes:
1. All units are direct current (dc) except for capacitance.
2. Negative sign indicates outward current flow, positive indicates inward flow.
3. Tvolcal values are shown for Vrr = 5.OV and TA = 25°C.
-
vlN
=
ov
f = 2 MHz
T, 3: 25%
d