ICS ICS853014

ICS853014
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-5
2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS853014 is a low skew, high performance
1-to-5, 2.5V/3.3V Differential-to-LVPECL/ECL
HiPerClockS™
Fanout Buffer and a member of the HiPerClockS™
family of High Performance Clock Solutions
from ICS. The ICS853014 has two selectable
clock inputs.
• 5 differential LVPECL/ECL outputs
Guaranteed output and par t-to-part skew characteristics
make the ICS853014 ideal for those applications
demanding well defined performance and repeatability.
• Output skew: 13ps (typical)
ICS
• 2 selectable differential LVPECL clock inputs
• PCLKx, nPCLKx pairs can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
• Maximum output frequency: > 2GHz
• Part-to-part skew: 60ps (typical)
• Propagation delay: 460ps (typical)
• LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.8V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.8V to -2.375V
• -40°C to 85°C ambient operating temperature
• Lead-Free package fully RoHS compliant
BLOCK DIAGRAM
PIN ASSIGNMENT
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
D
nEN
Q
LE
PCLK0
nPCLK0
PCLK1
nPCLK1
00
11
Q0
nQ0
Q1
nQ1
CLK_SEL
Q2
nQ2
V BB
20
19
18
17
16
15
14
13
12
11
VCC
nEN
VCC
nPCLK1
PCLK1
VBB
nPCLK0
PCLK0
CLK_SEL
VEE
ICS853014
Q3
nQ3
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm package body
G Package
Top View
Q4
nQ4
853014BG
1
2
3
4
5
6
7
8
9
10
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1
REV. C MAY 13, 2005
ICS853014
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-5
2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
1, 2
Q0, nQ0
Output
Type
Differential output pair. LVPECL / ECL interface levels.
Description
3, 4
Q1, nQ1
Output
Differential output pair. LVPECL / ECL interface levels.
5, 6
Q2, nQ2
Output
Differential output pair. LVPECL / ECL interface levels.
7, 8
Q3, nQ3
Output
Differential output pair. LVPECL / ECL interface levels.
9, 10
Q4, nQ4
Output
Differential output pair. LVPECL / ECL interface levels.
11
VEE
Power
12
CLK_SEL
Input
13
PCLK0
Input
14
nPCLK0
Input
15
VBB
Output
16
PCLK1
Input
17
nPCLK1
Input
18, 20
VCC
Power
Negative supply pin.
Clock select input. When HIGH, selects CLK1, nCLK1 inputs.
Pulldown When LOW, selects CLK0, nCLK0 inputs.
LVTTL / LVCMOS interface levels.
Pulldown Non-inver ting differential LVPECL clock input.
Inver ting differential LVPECL clock input. VCC/2 default when left floating.
Bias voltage.
Pulldown Non-inver ting differential LVPECL clock input.
Inver ting differential LVPECL clock input. VCC/2 default when left floating.
Positive supply pins.
Synchronizing clock enable. When LOW, clock outputs follow clock input.
19
nEN
Input
Pulldown When HIGH, Q outputs are forced low, nQ outputs are forced high.
LVTTL / LVCMOS interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
RPULLDOWN
Input Pulldown Resistor
75
kΩ
RVCC/2
Pullup/Pulldown Resistors
50
kΩ
853014BG
Test Conditions
Minimum
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2
Typical
Maximum
Units
REV. C MAY 13, 2005
ICS853014
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-5
2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs
Outputs
nEN
CLK_SEL
Selected Source
Q0:Q4
nQ0:nQ4
1
0
PCLK0, nPCLK0
Disabled; LOW
Disabled; HIGH
1
1
PCLK1, nPCLK1
Disabled; LOW
Disabled; HIGH
0
0
PCLK0, nPCLK0
Enabled
Enabled
0
1
PCLK1, nPCLK1
Enabled
Enabled
After nEN switches, the clock outputs are disabled or enabled following a falling input clock edge as shown in Figure 1.
In the active mode, the state of the outputs are a function of the PCLK0, nPCLK0 and PCLK1, nPCLK1 inputs as
described in Table 3B.
Enabled
Disabled
nPCLK0, nPCLK1
PCLK0, PCLK1
nEN
nQ0:nQ4
Q0:Q4
FIGURE 1. nEN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
PCLK0 or PCLK1
nPCLK0 or nPCLK1
Q0:Q4
nQ0:nQ4
0
1
LOW
HIGH
Input to Output Mode
Polarity
Differential to Differential
Non Inver ting
1
0
HIGH
LOW
Differential to Differential
Non Inver ting
0
Biased; NOTE 1
LOW
HIGH
Single Ended to Differential
Non Inver ting
1
Biased; NOTE 1
HIGH
LOW
Single Ended to Differential
Non Inver ting
Biased; NOTE 1
0
HIGH
LOW
Single Ended to Differential
Inver ting
Biased; NOTE 1
1
LOW
HIGH
Single Ended to Differential
Inver ting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
853014BG
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3
REV. C MAY 13, 2005
Integrated
Circuit
Systems, Inc.
ICS853014
LOW SKEW, 1-TO-5
2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
Negative Supply Voltage, VEE
Inputs, VI (LVPECL mode)
Inputs, VI (ECL mode)
Outputs, IO
Continuous Current
Surge Current
VBB Sing/Source, IBB
4.6V (LVPECL mode, VEE = 0) NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
-4.6V (ECL mode, VCC = 0)
to the device. These ratings are stress specifi-0.5V to VCC + 0.5V
cations only. Functional operation of product at
0.5V to VEE - 0.5V
these conditions or any conditions beyond those
listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect product reliability.
50mA
100mA
± 0.5mA
Operating Temperature Range, TA -40°C to +85°C
Storage Temperature, TSTG
-65°C to 150°C
Package Thermal Impedance, θJA
73.2°C/W (0 lfpm)
(Junction-to-Ambient)
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375V TO 3.8V; VEE = 0V
Symbol
Parameter
VCC
Positive Supply Voltage
IEE
Power Supply Current
Test Conditions
Minimum
Typical
Maximum
Units
2.375
3.3
3.8
V
75
mA
TABLE 4B. DC CHARACTERISTICS, VCC = 3.3V, VEE = 0V
Min
-40°C
Typ
Max
Min
25°C
Typ
Max
Min
85°C
Typ
Max
Output High Voltage; NOTE 1
2.175
2.275
2.38
2.225
2.295
2.375
2.22
2.295
2.365
V
VOL
Output Low Voltage; NOTE 1
1.405
1.545
1.68
1.425
1.52
1.615
1.44
1.535
1.63
V
VIH
Input High Voltage(Single-Ended)
2.075
2.36
2.075
2.36
2.075
2.36
V
VIL
Input Low Voltage(Single-Ended)
1.43
1.765
1.43
1.765
1.43
1.765
V
VBB
Output Voltage Reference; NOTE 2
Input High Voltage
Common Mode Range; NOTE 3, 4
Input
D0, D1, D2, D3
High Current nD0, nD1,n D2, nD3
D0, D1, D2, D3
Input
Low Current nD0, nD1,n D2, nD3
1.86
1.98
1.86
1.98
1.86
1.98
V
1.2
3.3
1.2
3.3
1.2
3. 3
V
150
µA
Symbol
Parameter
VOH
VCMR
IIH
IIL
150
150
Units
-10
-10
-10
µA
-150
-150
-150
µA
Input and output parameters var y 1:1 with VCC. VEE can var y +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
NOTE 2: Single-ended input operation is limited. VCC ≥ 3V in LVPECL mode.
NOTE 3: Common mode voltage is defined as VIH.
NOTE 4: For single-ended applications, the maximum input voltage for PCLK0, nPLCK0 and PCLK1, nPCLK1
is VCC + 0.3V.
853014BG
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4
REV. C MAY 13, 2005
Integrated
Circuit
Systems, Inc.
ICS853014
LOW SKEW, 1-TO-5
2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 2.5V; VEE = 0V
Symbol
Parameter
VOH
-40°C
25°C
85°C
Units
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Output High Voltage; NOTE 1
1.375
1.475
1.58
1.425
1.495
1.57
1.42
1.495
1.565
VOL
Output Low Voltage; NOTE 1
0.605
0.745
0.88
0.625
0.72
0.815
0.64
0.735
0.83
V
VIH
Input High Voltage(Single-Ended)
1.275
1.56
1.275
1.56
1.275
-0.83
V
VIL
0.63
0.965
0.63
0.965
0.63
0.965
V
1.2
2.5
1.2
2.5
1. 2
2.5
V
IIH
Input Low Voltage(Single-Ended)
Input High Voltage
Common Mode Range; NOTE 2, 3
Input
PCLK0, PCLK1
High Current nPCLK0, nPCLK1
150
µA
IIL
Input
Low Current
VCMR
PCLK0, PCLK1
150
150
-10
-10
-10
V
µA
-150
-150
-150
nPCLK0, nPCLK1
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
NOTE 2: Common mode voltage is defined as VIH.
NOTE 3: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1
is VCC + 0.3V.
µA
TABLE 4D. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -5.25V TO -2.375V
Symbol
Parameter
VOH
-40°C
25°C
85°C
Min
Typ
Max
Min
Typ
Output High Voltage; NOTE 1
-1.125
-1.025
-0.92
-1.075
-1.005
VOL
Output Low Voltage; NOTE 1
-1.895
-1.755
-1.62
-1.875
-1.78
VIH
Input High Voltage(Single-Ended)
-1.225
-0.94
-1.225
-0.94
VIL
-1.87
-1.535
-1.87
-1.44
-1.32
VEE+1.2V
0
IIH
Input Low Voltage(Single-Ended)
Output Voltage Reference;
NOTE 2
Input High Voltage
Common Mode Range;
NOTE 3, 4
Input
PCLK0, PCLK1
High Current nPCLK0, nPCLK1
IIL
Input
Low Current
VBB
VCMR
PCLK0, PCLK1
-10
Typ
Max
-0.93
-1.08
-1.005
-0.935
V
-1.685
-1.86
-1.765
-1.67
V
-1.225
-0.94
V
-1.535
-1.87
-1.535
V
-1.44
-1.32
-1.44
-1.32
V
VEE+1.2V
0
VEE+1.2V
0
V
150
µA
150
-10
-10
µA
-150
-150
-150
nPCLK0, nPCLK1
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
NOTE 2: Single-ended input operation is limited. VCC ≥ 3V in LVPECL mode.
NOTE 3: Common mode voltage is defined as VIH.
NOTE 4: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1
is VCC + 0.3V.
853014BG
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5
Units
Min
150
Max
µA
REV. C MAY 13, 2005
ICS853014
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-5
2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
TABLE 5. AC CHARACTERISTICS, VCC = 2.375V TO 3.8V, TA = -40°C TO 85°C
-40°C
Symbol
Parameter
fMAX
Output Frequency
tPD
Propagation Delay; NOTE 1
Min
Typ
25°C
Max
Min
>2
355
440
Typ
85°C
Max
Min
>2
525
37 6
460
550
40 0
Output Skew; NOTE 2, 5
tsk(pp)
Par t-to-Par t Skew; NOTE 3, 5
V PP
Peak-to-Peak Input Voltage; NOTE 4
150
800
1800
15 0
800
1800
150
tR/tF
Output Rise/Fall Time
90
15 0
210
90
150
210
tS
Clock Enable Setup Time
100
50
100
tH
Clock Enable Hold Time
20 0
140
200
25
13
500
25
12
Units
GHz
595
ps
25
ps
130
ps
800
1800
mV
90
150
210
ps
50
100
50
ps
140
200
140
ps
105
20% to 80%
Max
>2
tsk(o)
13
Typ
105
All parameters tested ≤ 1GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: The VCMR and VPP levels should be such that input low voltage never goes below VEE.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
853014BG
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6
REV. C MAY 13, 2005
Integrated
Circuit
Systems, Inc.
ICS853014
LOW SKEW, 1-TO-5
2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
2V
VCC
Qx
VCC
SCOPE
nPCLK0,
nPCLK1
LVPECL
V
Cross Points
PP
V
CMR
PCLK0,
PCLK1
nQx
VEE
V EE
-0.375V to -1.8V
OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx
nQx
PART 1
Qx
Qx
nQy
nQy
PART 2
Qy
Qy
tsk(pp)
tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
nPCLK0,
nPCLK1
80%
80%
PCLK0,
PCLK1
VSW I N G
Clock
Outputs
nQ0:nQ4
20%
20%
tF
tR
Q0:Q4
tPD
OUTPUT RISE/FALL TIME
PROPAGATION DELAY
nPCLK0,
nPCLK1
PCLK0,
PCLK1
nEN
SETUP
AND
853014BG
t HOLD
t SET-UP
HOLD TIME
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7
REV. C MAY 13, 2005
ICS853014
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-5
2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows an example of the differential input that can be
wired to accept single ended levels. The reference voltage level
VBB generated from the device is connected to the negative input.
The C1 capacitor should be located as close as possible to the
input pin.
VDD(or VCC)
CLK_IN
+
VBB
-
C1
0.1uF
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION
FOR
3.3V LVPECL OUTPUTS
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 3A and 3B show two different layouts which
are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
3.3V
Zo = 50Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
FOUT
50Ω
1
RTT =
Z
((VOH + VOL) / (VCC – 2)) – 2 o
FIN
50Ω
Zo = 50Ω
VCC - 2V
RTT
84Ω
FIGURE 3A. LVPECL OUTPUT TERMINATION
853014BG
125Ω
84Ω
FIGURE 3B. LVPECL OUTPUT TERMINATION
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8
REV. C MAY 13, 2005
ICS853014
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-5
2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
TERMINATION FOR 2.5V LVPECL OUTPUT
ground level. The R3 in Figure 4B can be eliminated and the
termination is shown in Figure 4C.
Figure 4A and Figure 4B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to
2.5V
VCC=2.5V
2.5V
2.5V
VCC=2.5V
R1
250
Zo = 50 Ohm
R3
250
+
Zo = 50 Ohm
+
Zo = 50 Ohm
-
Zo = 50 Ohm
2,5V LVPECL
Driv er
-
R1
50
2,5V LVPECL
Driv er
R2
62.5
R2
50
R4
62.5
R3
18
FIGURE 4B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 4A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCC=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
2,5V LVPECL
Driv er
R1
50
R2
50
FIGURE 4C. 2.5V LVPECL TERMINATION EXAMPLE
853014BG
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9
REV. C MAY 13, 2005
ICS853014
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-5
2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
LVPECL CLOCK INPUT INTERFACE
The PCLKx /nPCLKx accepts LVPECL, CML, SSTL and other
differential signals. Both VSWING and VOH must meet the VPP and
VCMR input requirements. Figures 5A to 5E show interface
examples for the HiPerClockS PCLKx/nPCLKx input driven
by the most common driver types. The input interfaces sug-
gested here are examples only. If the driver is from another
vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the
driver termination requirements.
2.5V
3.3V
3.3V
3.3V
2.5V
3.3V
R1
50
CML
R3
120
R2
50
SSTL
Zo = 50 Ohm
R4
120
Zo = 60 Ohm
PCLK
PCLK
Zo = 60 Ohm
Zo = 50 Ohm
nPCLK
nPCLK
HiPerClockS
PCLK/nPCLK
R1
120
FIGURE 5A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A CML DRIVER
HiPerClockS
PCLK/nPCLK
R2
120
FIGURE 5B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY AN SSTL DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125
3.3V
R4
125
Zo = 50 Ohm
Zo = 50 Ohm
C1
LVDS
R3
1K
R4
1K
PCLK
PCLK
R5
100
Zo = 50 Ohm
nPCLK
LVPECL
R1
84
C2
nPCLK
Zo = 50 Ohm
HiPerCloc kS
Input
R1
1K
R2
84
FIGURE 5C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
HiPerClockS
PC L K/n PCL K
R2
1K
FIGURE 5D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
3.3V
3.3V
3.3V
3.3V LVPECL
Zo = 50 Ohm
C1
Zo = 50 Ohm
C2
R3
84
R4
84
PCLK
nPCLK
R5
100 - 200
R6
100 - 200
R1
125
HiPerClockS
PCLK/nPCLK
R2
125
FIGURE 5E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL D RIVER WITH AC COUPLE
853014BG
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10
REV. C MAY 13, 2005
ICS853014
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-5
2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
SCHEMATIC EXAMPLE
This application note provides general design guide using
ICS853014 LVPECL buffer. Figure 6 shows a schematic example
of the ICS853014 LVPECL clock buffer. In this example, the in-
put is driven by an LVPECL driver. CLK_SEL is set at logic high
to select PCLK1/nPCLK1 input.
Zo = 50
+
Zo = 50
-
R12
1K
3.3V
Zo = 50
3.3V
Zo = 50
R2
50
U1
3.3V
C2
11
12
13
14
15
16
17
18
19
3.3V 20
VEE
CLK_SEL
PCLK0
nPCLK0
VBB
PCLK1
nPCLK1
VCC
nEN
VCC
nQ4
Q4
nQ3
Q3
nQ2
Q2
nQ1
Q1
nQ0
Q0
10
9
8
7
6
5
4
3
2
1
R9
50
Zo = 50
+
R10
50
C1
0.1u
-
ICS853014
R5
50
C5
0.1u
R7
50
C3
0.1u
Zo = 50
0.1u
LVPECL Driv er
R3
50
R1
50
R4
50
R11
1K
R6
50
C4
0.1u
FIGURE 6. EXAMPLE ICS853014 LVPECL CLOCK OUTPUT BUFFER SCHEMATIC
853014BG
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REV. C MAY 13, 2005
Integrated
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ICS853014
LOW SKEW, 1-TO-5
2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS853014.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS853014 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.8V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 75mA = 285mW
Power (outputs)MAX = 30.94mW/Loaded Output pair
If all outputs are loaded, the total power is 5 * 30.94mW = 154.7mW
Total Power_MAX (3.8V, with all outputs switching) = 285mW + 154.7mW = 439.7mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used . Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.440W * 66.6°C/W = 114.3°C. This is well below the limit of 125°C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA
FOR
20-PIN TSSOP, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
200
500
98.0°C/W
66.6°C/W
88.0°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
853014BG
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REV. C MAY 13, 2005
ICS853014
Integrated
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Systems, Inc.
LOW SKEW, 1-TO-5
2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
3. Calculations and Equations.
LVPECL output driver circuit and termination are shown in Figure 7.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 7. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CC
•
For logic high, VOUT = V
OH_MAX
(V
CC_MAX
•
-V
OH_MAX
OL_MAX
CC_MAX
-V
OL_MAX
– 0.935V
CC_MAX
) = 0.935V
For logic low, VOUT = V
(V
=V
=V
CC_MAX
– 1.67V
) = 1.67V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
– (V
CC_MAX
- 2V))/R ] * (V
CC_MAX
L
-V
OH_MAX
) = [(2V - (V
CC_MAX
-V
OH_MAX
))/R ] * (V
CC_MAX
L
-V
)=
OH_MAX
[(2V - 0.935V)/50Ω] * 0.935V = 19.92mW
Pd_L = [(V
OL_MAX
– (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OL_MAX
) = [(2V - (V
CC_MAX
-V
OL_MAX
))/R ] * (V
L
CC_MAX
-V
OL_MAX
)=
[(2V - 1.67V)/50Ω] * 1.67V = 11.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
853014BG
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REV. C MAY 13, 2005
ICS853014
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-5
2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE
FOR
20 LEAD TSSOP
θ by Velocity (Linear Feet per Minute)
JA
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
114.5°C/W
73.2°C/W
98.0°C/W
66.6°C/W
88.0°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS853014 is: 373
Pin compatible with MC100LVEP14 and SY100EP14U
853014BG
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REV. C MAY 13, 2005
Integrated
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PACKAGE OUTLINE - G SUFFIX
FOR
ICS853014
LOW SKEW, 1-TO-5
2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
20 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
N
A
Maximum
20
--
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
6.40
6.60
E
E1
6.40 BASIC
4.30
e
4.50
0.65 BASIC
L
0.45
0.75
α
0°
8°
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
853014BG
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REV. C MAY 13, 2005
ICS853014
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-5
2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
ICS853014BG
ICS853014BG
20 lead TSSOP
tube
-40°C to 85°C
ICS853014BGT
ICS853014BG
20 lead TSSOP
2500 tape & reel
-40°C to 85°C
ICS853014BGLF
ICS853014BGL
20 lead "Lead-Free" TSSOP
tube
-40°C to 85°C
ICS853014BGLFT
ICS853014BGL
20 lead "Lead-Free" TSSOP
2500 tape & reel
-40°C to 85°C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The ICS logo is a registered trademark, and HiPerClockS is a trademark of Integrated Circuit Systems, Inc. All other trademarks are the property of their respective owners and
may be registered in certain jurisdictions.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
853014BG
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REV. C MAY 13, 2005
Integrated
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Systems, Inc.
ICS853014
LOW SKEW, 1-TO-5
2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
REVISION HISTORY SHEET
Rev
B
Table
T4B
Page
pg. 4
T4C
pg. 5
T4D
pg. 5
pg. 8
T4B - T4D
Description of Change
• 3.3V LVPECL table - VOH values changed @ 85° to 2.22V min. and
2.295V typical from 2.295V min. and 2.33V typical.
• 3.3V LVPECL table - VOH values changed @ 85° to 2.22V min. and
2.295V typical from 2.295V min. and 2.33V typical.
• 3.3V LVPECL table - VOH values changed @ 85° to 2.22V min. and
2.295V typical from 2.295V min. and 2.33V typical.
• Revised LVPECL Output Termination drawings.
Date
9/10/03
pg. 10
• Revised Figure 5D.
pgs. 4-5 • LVPECL & ECL tables - deleted VPP row.
C
C
853014BG
3/18/04
T9
pg. 6
1
16
• AC Table - added VPP row and changed max. value from 1200mV to 1800mV.
Features Section - added Lead-Free bullet.
Ordering Information Table - added Lead-Free par t number.
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REV. C MAY 13, 2005