ICS ICS889831

Integrated
Circuit
Systems, Inc.
ICS889831
LOW SKEW, 1-TO-4
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS889831 is a high speed 1-to-4 Differentialto-LVPECL/ECL Fanout Buffer and is a member
HiPerClockS™
of the HiPerClockS™ family of high performance
clock solutions from ICS. The ICS889831 is
optimized for high speed and very low output
skew, making it suitable for use in demanding applications
such as SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fibre
Channel. The internally terminated differential input and
VREF_ AC pin allow other differential signal families such as
LVDS, LVHSTL and CML to be easily interfaced to the input
with minimal use of external components. The device also has
an output enable pin which may be useful for system test
and debug purposes. The ICS889831 is packaged in a small
3mm x 3mm 16-pin VFQFN package which makes it ideal
for use in space-constrained applications.
• 4 differential LVPECL/ECL outputs
ICS
• IN, nIN pair can accept the following differential input levels:
LVPECL, LVDS, CML, SSTL
• 50Ω internal input termination to VT
• Maximum output frequency: > 2.1GHz
• Output skew: 30ps (maximum)
• Part-to-part skew: 185ps (maximum)
• Additive phase jitter, RMS: 0.27ps (typical)
• Propagation delay: 570ps (maximum)
• LVPECL mode operating voltage supply range:
VCC = 2.5V ± 5%, 3.3V ± 5%, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.3V ± 5%, 2.5V ± 5%
• -40°C to 85°C ambient operating temperature
• Lead-Free package fully RoHS compliant
Q0
nQ0
LE
5 0Ω
Q1
Q2
nQ2
VREF_AC
VEE
VCC
11
VT
Q2 3
10
VREF_AC
9
5
6
7
8
IN
nIN
ICS889831
16-Lead VFQFN
3mm x 3mm x 0.95 package body
K Package
Top View
Q3
nQ3
889831AK
nQ1 2
nQ2 4
nQ1
5 0Ω
16 15 14 13
12
EN
IN
VT
nIN
Q1 1
VCC
Q
nQ3
D
Q3
EN
Q0
PIN ASSIGNMENT
nQ0
BLOCK DIAGRAM
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1
REV. A JUNE 16, 2005
ICS889831
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-4
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 2
Q1, nQ1
Output
Differential output pair. LVPECL / ECL interface levels.
3, 4
Q2, nQ2
Output
Differential output pair. LVPECL / ECL interface levels.
5, 6
Q3, nQ3
Output
Differential output pair. LVPECL / ECL interface levels.
7, 14
VCC
Power
8
EN
Input
9
nIN
Input
Positive supply pins.
Synchronizing clock enable. When LOW, Q outputs will go LOW and nQ
outputs will go HIGH on the next LOW transition at IN inputs. Input
threshold is VCC/2V. Includes a 37kΩ pull-up resistor. Default state is
HIGH when left floating. The internal latch is clocked on the falling edge
of the input signal IN. LVTTL / LVCMOS interface levels.
Inver ting differential clock input. 50Ω internal input termination to VT.
10
VREF_AC
Output
11
VT
Input
Termination input.
12
IN
Input
Non-inver ting differential clock input. 50Ω internal input termination to VT.
13
VEE
Power
Negative supply pin.
Pullup
Reference voltage for AC-coupled applications.
15, 16
Q0, nQ0
Output
Differential output pair. LVPECL / ECL interface levels.
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
RPULLUP
Input Pullup Resistor
889831AK
Test Conditions
Minimum
Typical
37
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2
Maximum
Units
kΩ
REV. A JUNE 16, 2005
ICS889831
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-4
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Input
Outputs
EN
Q0:Q3
nQ0:nQ3
0
Disabled; LOW
Disabled; HIGH
1
Enabled
Enabled
After EN switches, the clock outputs are disabled or enabled
following a falling input clock edge as shown in Figure 1.
EN
VCC/2
VCC/2
tS
tH
nIN
IN
VIN
→
nQx
tPD
←
VOUT Swing
Qx
FIGURE 1. EN TIMING DIAGRAM
TABLE 3B. TRUTH TABLE
Inputs
Outputs
IN
nIN
EN
Q0:Q3
nQ0:nQ3
0
1
1
0
1
1
0
1
1
0
X
X
0
0(1)
1(1)
NOTE 1: On next negative transition of the input signal (IN).
889831AK
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3
REV. A JUNE 16, 2005
ICS889831
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-4
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
Negative Supply Voltage, VEE
Inputs, VI (LVPECL mode)
Inputs, VI (ECL mode)
Outputs, IO
Continuous Current
Surge Current
4.6V (LVPECL mode, VEE = 0) NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
-4.6V (ECL mode, VCC = 0)
to the device. These ratings are stress specifi-0.5V to VCC + 0.5 V
cations only. Functional operation of product at
0.5V to VEE - 0.5V
these conditions or any conditions beyond those
listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect product reliability.
50mA
100mA
Input Current, IN, nIN
±50mA
VT Current, IVT
±100mA
Input Sink/Source, IREF_AC
± 0.5mA
Operating Temperature Range, TA -40°C to +85°C
Storage Temperature, TSTG
-65°C to 150°C
Package Thermal Impedance, θJA
51.5°C/W (0 lfpm)
(Junction-to-Ambient)
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.5V ± 5%, 3.3V ± 5%; VEE = 0V
Symbol
Parameter
VCC
Positive Supply Voltage
IEE
Power Supply Current
Test Conditions
Minimum
Typical
Maximum
Units
2.375
3.3
3.465
V
60
mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = 2.5V ± 5%, 3.3V ± 5%; VEE = 0V
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
Test Conditions
IIH
Input High Current
VCC = VIN = 3.465V
IIL
Input Low Current
VCC = 3.465V, VIN = 0V
Minimum
Typical
Maximum
Units
2
VCC + 0.3
V
0
0.8
V
5
-150
µA
µA
TABLE 4C. DC CHARACTERISTICS, VCC = 2.5V ± 5%, 3.3V ± 5%; VEE = 0V
Symbol
Parameter
RIN
Differential Input Resistance
(IN, nIN)
VIH
Input High Voltage
(IN, nIN)
1.2
VCC
V
VIL
Input Low Voltage
(IN, nIN)
0
VIH - 0.15
V
VIN
Input Voltage Swing
VREF_AC
Reference Voltage
VDIFF_IN
Differential Input Voltage Swing
IIN
Input Current; NOTE 1
Test Conditions
Minimum
Typical
Maximum
Units
IN-to-VT
40
50
60
Ω
0.15
VCC - 1.42
0.3
(IN, nIN)
VCC - 1.37
2.8
V
VCC - 1.32
V
3.4
V
35
mA
NOTE 1: Guaranteed by design.
889831AK
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4
REV. A JUNE 16, 2005
ICS889831
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-4
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 2.375V TO 3.465V; VEE = 0V
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Units
VOH
Output High Voltage; NOTE 1
VCC - 1.125
VCC - 1.005
VCC - 0.935
V
VOL
Output Low Voltage; NOTE 1
VCC - 1.895
VCC - 1.78
VCC - 1.67
V
VOUT
Output Voltage Swing
0.6
1.0
V
VDIFF_OUT
Differential Output Voltage Swing
1.2
2.0
V
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
TABLE 5. AC CHARACTERISTICS, VCC = 0V; VEE = -3.3V ± 5%, -2.5V ± 5% OR VCC = 2.5 ± 5%, 3.3V ± 5%; VEE = 0V
Symbol
Parameter
fMAX
Maximum Output Frequency
tPD
Propagation Delay; (Differential);
NOTE 1
tsk(o)
Output Skew; NOTE 2, 4
tsk(pp)
Par t-to-Par t Skew; NOTE 3, 4
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section
tjit
Condition
Minimum
Output Swing ≥ 450mV
2.1
Typical
Maximum
Units
GHz
Input Swing: 100mV
300
435
570
ps
Input Swing: 800mV
255
370
485
ps
30
ps
185
ps
155.52MHz, Integration
Range: 12kHz - 20MHz
0.27
ps
tR/tF
Output Rise/Fall Time
tS
Clock Enable Setup Time
EN to IN, nIN
300
ps
tH
Clock Enable Hold Time
EN to IN, nIN
300
ps
20% to 80%
100
250
ps
All parameters characterized at ≤ 1GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
889831AK
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5
REV. A JUNE 16, 2005
Integrated
Circuit
Systems, Inc.
ICS889831
LOW SKEW, 1-TO-4
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
ADDITIVE PHASE JITTER
the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
0
-10
Additive Phase Jitter @ 155.52MHz
-20
(12kHz to 20MHz)
= 0.27ps typical
-30
-40
-50
SSB PHASE NOISE dBc/HZ
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
889831AK
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
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6
REV. A JUNE 16, 2005
Integrated
Circuit
Systems, Inc.
ICS889831
LOW SKEW, 1-TO-4
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
2V
VCC
VCC
Qx
SCOPE
nIN
LVPECL
V
Cross Points
IN
V
IH
IN
nQx
VEE
V
IL
V EE
-0.375V to -1.465V
OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx
PART 1
Qx
nQx
nQy
nQy
Qx
PART 2
Qy
Qy
tsk(pp)
tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
nIN
80%
80%
IN
VSW I N G
Clock
Outputs
20%
20%
nQ0:nQ3
tF
tR
Q0:Q3
tPD
OUTPUT RISE/FALL TIME
PROPAGATION DELAY
nIN
IN
EN
t HOLD
VDIFF_IN, VDIFF_OUT
1600mV
(typical)
t SET-UP
SINGLE ENDED & DIFFERENTIAL INPUT VOLTAGE SWING
SETUP & HOLD TIME
889831AK
VIN, VOUT
800mV
(typical)
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7
REV. A JUNE 16, 2005
ICS889831
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-4
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
APPLICATION INFORMATION
TERMINATION FOR 3.3V LVPECL OUTPUTS
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 2A and 2B show two different layouts which
are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
3.3V
Zo = 50Ω
125Ω
FOUT
125Ω
FIN
Zo = 50Ω
Zo = 50Ω
FOUT
50Ω
RTT =
1
Z
((VOH + VOL) / (VCC – 2)) – 2 o
VCC - 2V
Zo = 50Ω
RTT
84Ω
FIGURE 2A. LVPECL OUTPUT TERMINATION
889831AK
FIN
50Ω
84Ω
FIGURE 2B. LVPECL OUTPUT TERMINATION
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8
REV. A JUNE 16, 2005
ICS889831
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-4
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
TERMINATION FOR 2.5V LVPECL OUTPUTS
Figure 3A and Figure 3B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to
ground level. The R3 in Figure 3B can be eliminated and the
termination is shown in Figure 3C.
2.5V
VCC=2.5V
2.5V
2.5V
VCC=2.5V
Zo = 50 Ohm
R1
250
R3
250
+
Zo = 50 Ohm
Zo = 50 Ohm
+
Zo = 50 Ohm
2,5V LVPECL
Driv er
-
R1
50
2,5V LVPECL
Driv er
R2
62.5
R2
50
R4
62.5
R3
18
FIGURE 3A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 3B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCC=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
2,5V LVPECL
Driv er
R1
50
R2
50
FIGURE 3C. 2.5V LVPECL TERMINATION EXAMPLE
889831AK
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REV. A JUNE 16, 2005
ICS889831
Integrated
Circuit
Systems, Inc.
2.5V LVPECL INPUT
WITH
LOW SKEW, 1-TO-4
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
Ω TERMINATION INTERFACES
BUILT-IN 50Ω
The IN /nIN with built-in 50Ω terminations accepts LVDS,
LVPECL, LVHSTL, CML, SSTL and other differential signals.
Both V OUT and V OH must meet the V PP and V CMR input
requirements.Figures 4A to 4D show interface examples for the
HiPerClockS IN/nIN input with built-in 50Ω terminations driven
3.3V or 2.5V
by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with
the vendor of the driver component to confirm the driver termination requirements.
2.5V
2.5V
2.5V
Zo = 50 Ohm
Zo = 50 Ohm
IN
IN
VT
Zo = 50 Ohm
nIN
LVDS
nIN
Receiver
With
Built-In
50 Ohm
Receiver
With
Built-In
50 Ohm
2.5V LVPECL
R1
18
FIGURE 4A. HIPERCLOCKS IN/nIN INPUT WITH
Ω DRIVEN BY AN LVDS DRIVER
BUILT-IN 50Ω
2.5V
VT
Zo = 50 Ohm
FIGURE 4B. HIPERCLOCKS IN/nIN INPUT WITH
Ω DRIVEN BY AN LVPECL DRIVER
BUILT-IN 50Ω
2.5V
2.5V
2.5V
Zo = 50 Ohm
Zo = 50 Ohm
IN
IN
VT
Zo = 50 Ohm
nIN
CML - Open Collector
Zo = 50 Ohm
VT
nIN
Receiver
With
Built-In
50 Ohm
CML - Built-in 50 Ohm Pull-up
FIGURE 4C. HIPERCLOCKS IN/nIN INPUT WITH
Ω DRIVEN BY AN OPEN COLLECTOR
BUILT-IN 50Ω
CML DRIVER
Receiver
With
Built-In
50 Ohm
FIGURE 4D. HIPERCLOCKS IN/nIN INPUT WITH
Ω DRIVEN BY A CML DRIVER
BUILT-IN 50Ω
Ω PULLUP
WITH BUILT-IN 50Ω
2.5V
2.5V
R1
25
Zo = 50 Ohm
IN
Zo = 50 Ohm
R2
SSTL
25
VT
nIN
Receiver With Built-In 50Ω
FIGURE 4E. HIPERCLOCKS IN/nIN INPUT WITH
Ω DRIVEN BY AN SSTL DRIVER
BUILT-IN 50Ω
889831AK
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REV. A JUNE 16, 2005
Integrated
Circuit
Systems, Inc.
3.3V LVPECL INPUT
WITH
ICS889831
LOW SKEW, 1-TO-4
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
Ω TERMINATION INTERFACES
BUILT-IN 50Ω
The IN /nIN with built-in 50Ω terminations accepts LVDS,
LVPECL, LVHSTL, CML, SSTL and other differential signals.
Both VOUT and VOH must meet the VPP and VCMR input requirements. Figures 5A to 5E show interface examples for the
HiPerClockS IN/nIN input with built-in 50Ω terminations driven
3.3V
by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with
the vendor of the driver component to confirm the driver termination requirements.
3.3V
3.3V
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
IN
IN
Zo = 50 Ohm
VT
nIN
nIN
Receiver
With
Built-In
50 Ohm
LVDS
3.3V
Receiver
With
Built-In
50 Ohm
LVPECL
R1
50
FIGURE 5A. HIPERCLOCKS IN/nIN INPUT WITH
Ω DRIVEN BY AN LVDS DRIVER
BUILT-IN 50Ω
FIGURE 5B. HIPERCLOCKS IN/nIN INPUT WITH
Ω DRIVEN BY AN LVPECL DRIVER
BUILT-IN 50Ω
3.3V
3.3V
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
IN
IN
Zo = 50 Ohm
VT
Zo = 50 Ohm
VT
Zo = 50 Ohm
nIN
CML- Open Collector
nIN
Receiver
With
Built-In
50 Ohm
CML- Built-in 50 Ohm Pull-Up
Receiver
With
Built-In
50 Ohm
FIGURE 5D. HIPERCLOCKS IN/nIN INPUT WITH
Ω DRIVEN BY A CML DRIVER
BUILT-IN 50Ω
Ω PULLUP
WITH BUILT-IN 50Ω
FIGURE 5C. HIPERCLOCKS IN/nIN INPUT WITH
Ω DRIVEN BY A CML DRIVER
BUILT-IN 50Ω
WITH OPEN COLLECTOR
3.3V
VT
3.3V
R1
25
Zo = 50 Ohm
IN
Zo = 50 Ohm
VT
nIN
SSTL
R2
25
Receiver
With
Built-In
50 Ohm
FIGURE 5E. HIPERCLOCKS IN/nIN INPUT WITH
Ω DRIVEN BY AN SSTL DRIVER
BUILT-IN 50Ω
889831AK
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REV. A JUNE 16, 2005
Integrated
Circuit
Systems, Inc.
3.3V DIFFERENTIAL INPUT
WITH
ICS889831
LOW SKEW, 1-TO-4
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
Ω TERMINATION UNUSED INPUT HANDLING
BUILT-IN 50Ω
To prevent oscillation and to reduce noise, it is recommended to
have pullup and pulldown connect to true and compliment of the
unused input as shown in Figure 6.
3.3V
3.3V
R1
1K
IN
VT
nIN
Receiver
with
Built-In
50 Ohm
R2
1K
FIGURE 6. UNUSED INPUT HANDLING
2.5V DIFFERENTIAL INPUT
WITH
Ω TERMINATION UNUSED INPUT HANDLING
BUILT-IN 50Ω
To prevent oscillation and to reduce noise, it is recommended to
have pullup and pulldown connect to true and compliment of the
unused input as shown in Figure 7.
2.5V
2.5V
R1
680
IN
VT
nIN
Receiver
with
Built-In
50 Ohm
R2
680
FIGURE 7. UNUSED INPUT HANDLING
889831AK
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REV. A JUNE 16, 2005
ICS889831
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-4
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
SCHEMATIC EXAMPLE
Figure 8 shows a schematic example of the ICS889831. This
schematic provides examples of input and output handling. The
ICS889831 input has built-in 50Ω termination resistors. The input can directly accept various types of differential signal without AC couple. For AC couple termination, the ICS889831 also
provides the VREF_AC pin for proper offset level after the AC
couple. This example shows the ICS889831 input driven by a
2.5V LVPECL driver with AC couple. The ICS889831 outputs
are LVPECL driver. In this example, we assume the traces are
long transmission line and the receiver is high input impedance
without built-in matched load. An example of 3.3V LVPECL termination is shown in this schematic. Additional termination approaches are shown in the LVPECL Termination Application Note.
3.3V
3.3V
C2
3.3V
Zo = 50
R3
133
R5
133
0.1u
8
7
6
5
-
Zo = 50
9
10
11
12
nQ2
Q2
nQ1
Q1
nIN
VREF_AC
VT
IN
R4
82.5
VEE
VCC
Q0
nQ0
C6
4
3
2
1
R2
100
R6
82.5
3.3V
3.3V
13
14
15
16
R1
100
+
C5
Zo = 50
LVPECL
Zo = 50
EN
VCC
nQ3
Q3
U1
ICS889831
2.5V
Zo = 50
R7
133
R9
133
-
3.3V
Zo = 50
+
C1
0.1u
R8
82.5
R10
82.5
FIGURE 8. ICS889831 APPLICATION SCHEMATIC EXAMPLE
889831AK
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REV. A JUNE 16, 2005
ICS889831
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-4
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS839831.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS889831 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.63V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.63V * 60mA = 217.8mW
Power (outputs)MAX = 30.94mW/Loaded Output pair
If all outputs are loaded, the total power is 4 * 30.94mW = 123.8mW
•
Power Dissipation at built-in terminations: Assume the input is driven by a 3.3V SSTL driver as shown in Figure 5E
and estimated approximately 1.75V drop across IN and nIN.
Total Power Dissipation for the two 50Ω built-in terminations is: (1.75V)2 / (50Ω + 50Ω) = 30.6mW
Total Power_MAX (3.63V, with all outputs switching) = 217.8mW + 123.8mW + 30.6mW = 372.2mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 0 linear feet per minute and a multi-layer board, the appropriate value is 51.5°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.372W * 51.5°C/W = 104°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA
FOR
16-PIN VFQFN, FORCED CONVECTION
θJAvs. 0 Velocity (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards
889831AK
51.5°C/W
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14
REV. A JUNE 16, 2005
ICS889831
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-4
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 9.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 9. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CC
•
For logic high, VOUT = V
OH_MAX
=V
– 0.935V
CC_MAX
(VCC_MAX - VOH_MAX) = 0.935V
•
For logic low, VOUT = V
OL_MAX
(V
CC_MAX
-V
OL_MAX
=V
CC_MAX
– 1.67V
) = 1.67V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
– (V
CC_MAX
- 2V))/R ] * (V
CC_MAX
L
-V
OH_MAX
) = [(2V - (V
CC_MAX
-V
OH_MAX
))/R ] * (V
CC_MAX
L
-V
)=
OH_MAX
[(2V - 0.935V)/50Ω] * 0.935V = 19.92mW
Pd_L = [(V
OL_MAX
– (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OL_MAX
) = [(2V - (V
CC_MAX
-V
OL_MAX
))/R ] * (V
L
CC_MAX
-V
OL_MAX
)=
[(2V - 1.67V)/50Ω] * 1.67V = 11.02mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
889831AK
www.icst.com/products/hiperclocks.html
15
REV. A JUNE 16, 2005
ICS889831
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-4
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE
FOR
16 LEAD VFQFN
θJA vs. 0 Air Flow (Linear Feet per Minute)
Multi-Layer PCB, JEDEC Standard Test Boards
51.5°C/W
TRANSISTOR COUNT
The transistor count for ICS889831 is: 234
Pin compatible with SY89831U
889831AK
www.icst.com/products/hiperclocks.html
16
REV. A JUNE 16, 2005
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - K SUFFIX
FOR
ICS889831
LOW SKEW, 1-TO-4
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
16 LEAD VFQFN
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
SYMBOL
MINIMUM
MAXIMUM
16
N
A
0.80
1.0
A1
0
0.05
0.25 Reference
A3
b
0.18
0.30
e
0.50 BASIC
ND
4
NE
4
3.0
D
D2
0.25
1.25
3.0
E
E2
0.25
1.25
L
0.30
0.50
Reference Document: JEDEC Publication 95, MO-220
889831AK
www.icst.com/products/hiperclocks.html
17
REV. A JUNE 16, 2005
ICS889831
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-4
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
ICS889831AK
831A
16 Lead VFQFN
tube
-40°C to 85°C
ICS889831AKT
831A
16 Lead VFQFN
3500 tape & reel
-40°C to 85°C
ICS889831AKLF
TBD
16 Lead "Lead-Free" VFQFN
tube
-40°C to 85°C
ICS889831AKLFT
TBD
16 Lead "Lead-Free" VFQFN
3500 tape & reel
-40°C to 85°C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
889831AK
www.icst.com/products/hiperclocks.html
18
REV. A JUNE 16, 2005