TI TPIC1502

TPIC1502
QUAD AND HEX POWER DMOS ARRAY
SLIS054 – OCTOBER 1996
D
D
D
D
Low rDS(on):
0.25 Ω Typ (Full H-Bridge)
0.4 Ω Typ (Triple Half H-Bridge)
Pulsed Current . . . 4 A Per Channel
Matched Sense Transistors for Class A-B
Linear Operation
Fast Commutation Speed
DW PACKAGE
(TOP VIEW)
OUTPUT3
SOURCE
GND
GATE3B
GATE2B
GATE2C
OUTPUT2
GATE4B
GATE2A
GATE5B
VDD2
SOURCE
description
The TPIC1502 is a monolithic power DMOS array
that consists of ten electrically isolated N-channel
enhancement-mode power DMOS transistors,
four of which are configured as a full H-bridge and
six as a triple half H-bridge. The lower stage of the
full H-bridge is provided with an integrated
sense-FET to allow biasing of the bridge in class
A-B operation.
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
VDD3
GND
GATE3A
GATE1B
SENSE
OUTPUT1
GATE4A
GATE1A
GATE5A
VDD1
OUTPUT4
OUTPUT5
The TPIC1502 is offered in a 24-pin wide-body surface-mount (DW) package and is characterized for operation
over the case temperature range of – 40°C to 125°C.
schematic
VDD1
VDD2
15
11
Q2A
Q1A
17
GATE1A
Q3A
22
GATE3A
9
GATE2A
19
OUTPUT1
D1
D2
Q1B
21
GATE1B
7
OUTPUT2
1
OUTPUT3
Q2B
5
GATE2B
SENSE
6
VDD3
24
D3
Q3B
4
GATE3B
20
Q4A
18
GATE4A
Q5A
16
GATE5A
14
OUTPUT4
13
OUTPUT5
Q4B
8
GATE4B
Q5B
10
GATE5B
2, 12
SOURCE
Q2C
GATE2C
6V
3, 23
GND
NOTES: A. Terminals 3 and 23 must be externally connected.
B. Terminals 2 and 12 must be externally connected.
C. No output may be taken greater than 0.5 V below GND.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
TPIC1502
QUAD AND HEX POWER DMOS ARRAY
SLIS054 – OCTOBER 1996
absolute maximum ratings, TC = 25°C (unless otherwise noted)†
Supply-to-GND voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 V
Source-to-GND voltage (Q3A, Q4A, Q5A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 V
Output-to-GND voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 V
Sense-to-GND voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 V
Gate-to-source voltage range, VGS (Q1A, Q1B, Q2A, Q2B, Q3A, Q3B, Q4A, Q4B, Q5A, Q5B) . . . . . ± 20 V
Gate-to-source voltage, VGS (Q2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.7 V to 6 V
Continuous gate-to-source zener-diode current (Q2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA
Pulsed gate-to-source zener-diode current (Q2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous drain current, each output (Q1A, Q1B, Q2A, Q2B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 A
Continuous drain current, each output (Q3A, Q3B, Q4A, Q4B, Q5A, Q5B) . . . . . . . . . . . . . . . . . . . . . . . . 1.5 A
Continuous drain current (Q2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA
Continuous source-to-drain diode current (Q1A, Q1B, Q2A, Q2B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 A
Continuous source-to-drain diode current (Q3A, Q3B, Q4A, Q4B, Q5A, Q5B) . . . . . . . . . . . . . . . . . . . . . 1.5 A
Continuous source-to-drain diode current (Q2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA
Pulsed drain current, each output, Imax (Q1A, Q1B, Q2A, Q2B) (see Note 1 and Figure 24) . . . . . . . . . . 4 A
Pulsed drain current, each output, Imax (Q3A, Q3B, Q4A, Q4B, Q5A, Q5B)
(see Note 1 and Figure 25) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 A
Pulsed drain current, each output, Imax (Q2C) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Continuous total power dissipation, TC = 70°C (see Note 2 and Figures 24 and 25) . . . . . . . . . . . . . . 2.86 W
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 150°C
Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Pulse duration = 10 ms, duty cycle = 2%
2. Package mounted in intimate contact with infinite heat sink.
2
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TPIC1502
QUAD AND HEX POWER DMOS ARRAY
SLIS054 – OCTOBER 1996
electrical characteristics, Q1A, Q1B, Q2A, Q2B, TC = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
V(BR)DSX
Drain-to-source breakdown voltage
VGS(th)
Gate-to-source threshold voltage
VGS(th)match
Gate-to-source threshold voltage matching
V(BR)
Reverse drain-to-GND breakdown voltage
V(BR)GS
V(BR)SG
Gate-to-source breakdown voltage, Q2C
Source-to-gate breakdown voltage, Q2C
ID = 250 µA,
ID = 1 mA,
See Figure 5
VGS = 0
VDS = VGS,
ID = 1 mA,
VDS = VGS
Drain-to-GND current = 250 µA
(D1, D2)
IGS = 100 µA
IGS = 100 µA
V(DS)on
Drain-to-source on-state voltage
ID = 1.5 A,
See Notes 3 and 4
VF
Forward on-state voltage, GND-to-VDD1,
GND-to-VDD2
ID = 1.5 A (D1, D2)
See Notes 3 and 4
VF(SD)
Forward on-state voltage, source-to-drain
IS = 1.5 A,
VGS = 0,
See Notes 3 and 4 and Figure 19
IDSS
Zero gate voltage drain current
Zero-gate-voltage
VDS = 16 V,,
VGS = 0
TC = 25°C
TC = 125°C
IGSSF
Forward gate current, drain short-circuited
to source
VGS = 16 V,
IGSSR
Reverse gate current, drain short-circuited
to source
Ilk
lkg
rDS(on)
DS( )
MIN
TYP
MAX
20
1.5
UNIT
V
1.85
2.2
V
40
mV
20
V
6
V
0.7
V
VGS = 10 V,
0.375
0.45
1.5
0.93
V
V
1.2
V
0.05
1
0.5
10
VDS = 0
10
100
nA
VSG = 16 V,
VDS = 0
10
100
nA
Leakage
g current,, VDD1-to-GND,,
VDD2-to-GND, gate shorted to source
VDGND = 16 V
TC = 25°C
TC = 125°C
0.05
1
0.5
10
VGS = 10 V,
ID = 1.5 A,,
See Notes 3 and 4
and Figure 9
TC = 25°C
0.25
0.3
drain to source on-state
on state resistance
Static drain-to-source
TC = 125°C
0.38
0.51
VDS = 14 V,
ID = 750 mA,
See Notes 3 and 4 and Figure 13
gfs
Forward transconductance
Ciss
Short-circuit input capacitance, common
source
Coss
Short-circuit output capacitance, common
source
Crss
Short-circuit reverse transfer capacitance,
common source
µA
µA
Ω
0.75
1.2
S
98
VDS = 14 V,
f = 1 MHz,
VGS = 0,
See Figure 17
70
pF
54
αs
Sense-FET drain current ratio
VDS = 6 V,
ID(Q2B) = 1.5 mA
100
150
NOTES: 3. Technique should limit TJ – TC to 10°C maximum.
4. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
200
source-to-drain diode characteristics, Q1A, Q2A, TC = 25°C
PARAMETER
trr
Reverse-recovery time
QRR
Total diode charge
TEST CONDITIONS
IS = 750 mA,
VGS = 0,
VDS = 14 V,
V
di/dt = 100 A/µs
A/µs,
See Figures 1 and 23
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MIN
TYP
MAX
UNIT
18
ns
14
nC
3
TPIC1502
QUAD AND HEX POWER DMOS ARRAY
SLIS054 – OCTOBER 1996
resistive-load switching characteristics, Q1A, Q1B, Q2A, Q2B, TC = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
td(on)
td(off)
Turn-on delay time
tr
tf
Rise time
Qg
Total gate charge
Qgs(th)
Threshold gate-to-source charge
Qgd
Gate-to-drain charge
LD
LS
Internal drain inductance
7
Internal source inductance
7
Rg
Internal gate resistance
MAX
UNIT
12
Turn-off delay time
VDD = 14 V,,
tdis = 10 ns,
RL = 18.7 Ω,,
See Figure 3
13
ten = 10 ns,,
ns
2.2
Fall time
6
VDS = 14 V,
V
ID = 750 mA,
A
See Figure 4 and Figure 21
VGS = 10 V,
V
1.7
2.1
0.3
0.4
0.4
0.5
nC
nH
Ω
0.25
electrical characteristics, Q3A, Q3B, Q4A, Q4B, Q5A, Q5B, TC = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ID = 250 µA,
ID = 1 mA,
See Figure 6
TYP
Drain-to-source breakdown voltage
VGS(th)
Gate-to-source threshold voltage
V(BR)
Reverse drain-to-GND breakdown voltage
Drain-to-GND current = 250 µA (D3)
V(DS)on
Drain-to-source on-state voltage
ID = 1.5 A,
VGS = 10 V,
See Notes 3 and 4
0.6
VF
Forward on-state voltage, GND-to-VDD3
ID = 1.5 A (D3),
4
1.5
VF(SD)
Forward on-state voltage, source-to-drain
IS = 1.5 A,
VGS = 0
See Notes 3 and 4 and Figure 20
IDSS
Zero gate voltage drain current
Zero-gate-voltage
VDS = 16 V,,
VGS = 0
TC = 25°C
TC = 125°C
IGSSF
Forward gate current, drain short-circuited to
source
VGS = 16 V,
IGSSR
Reverse gate current, drain short-circuited to
source
Ilk
lkg
rDS(
DS(on))
VGS = 0
VDS = VGS,
MIN
V(BR)DSX
1.5
V
1.85
2.2
20
See Notes 3 and
UNIT
V
V
1
0.75
V
V
1.2
V
0.05
1
0.5
10
VDS = 0
10
100
nA
VSG = 16 V,
VDS = 0
10
100
nA
Leakage
g current,, VDD3-to-GND,, g
gate shorted to
source
VDGND = 16 V
TC = 25°C
TC = 125°C
0.05
1
0.5
10
TC = 25°C
0.4
0.5
drain to source on-state
on state resistance
Static drain-to-source
VGS = 10 V,
ID = 1.5 A,
See Notes 3
and 4 and
Figure 10
TC = 125°C
0.61
0.85
Forward transconductance
Ciss
Short-circuit input capacitance, common source
Coss
Short-circuit output capacitance, common source
Crss
Short-circuit reverse transfer capacitance,
common source
µA
µA
Ω
VDS = 14 V,
ID = 750 mA,
See Notes 3 and 4 and Figure 14
gfs
0.4
0.74
S
73
VDS = 14 V,
f = 1 MHz,
VGS = 0,
See Figure 18
65
43
NOTES: 3: Technique should limit TJ – TC to 10°C maximum.
4: These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
4
MAX
20
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pF
F
TPIC1502
QUAD AND HEX POWER DMOS ARRAY
SLIS054 – OCTOBER 1996
source-to-drain diode characteristics, Q3A, Q4A, Q5A, TC = 25°C
PARAMETER
trr
Reverse-recovery time
QRR
Total diode charge
TEST CONDITIONS
IS = 750 mA,
VDS = 14 V
V,
See Figures 2 and 23
MIN
VGS = 0,
di/dt = 100 A/µs
A/µs,
TYP
MAX
UNIT
26
ns
17
nC
resistive-load switching characteristics, Q3A, Q3B, Q4A, Q4B, Q5A, Q5B, TC = 25°C
PARAMETER
td(on)
td(off)
Turn-on delay time
tr
tf
Rise time
Qg
Total gate charge
TEST CONDITIONS
MIN
TYP
MAX
UNIT
13
Turn-off delay time
VDD = 14 V,,
tdis = 10 ns,
RL = 18.7 Ω,,
See Figure 3
13
ten = 10 ns,,
ns
3
Fall time
7
VDS = 14 V,
V
ID = 750 mA,
A
See Figure 4 and Figure 22
VGS = 10 V,
V
1
1.3
0.2
0.25
0.2
0.25
Qgs(th)
Threshold gate-to-source charge
Qgd
Gate-to-drain charge
LD
LS
Internal drain inductance
7
Internal source inductance
7
Rg
Internal gate resistance
nC
nH
Ω
0.25
thermal resistance
PARAMETER
TEST CONDITIONS
MIN
TYP
RθJA
Junction-to-ambient thermal resistance
See Notes 5 and 8
90
RθJB
Junction-to-board thermal resistance
See Notes 6 and 8
52
See Notes 7 and 8
28
RθJP Junction-to-pin thermal resistance
NOTES: 5. Package mounted on a FR4 printed-circuit board with no heatsink.
6. Package mounted on a 24 in2, 4-layer FR4 printed-circuit board.
7. Package mounted in intimate contact with infinite heatsink.
8. All outputs with equal power
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MAX
UNIT
°C/W
5
TPIC1502
QUAD AND HEX POWER DMOS ARRAY
SLIS054 – OCTOBER 1996
PARAMETER MEASUREMENT INFORMATION
2
VDS = 14 V
VGS =0
TJ = 25°C
Q1A and Q2A
I S – Source-to-Drain Diode Current – A
1.5
1
Reverse di/dt = 100 A/µs
0.5
0
– 0.5
25% of IRM†
–1
Shaded Area = QRR
IRM†
– 1.5
trr(SD)
–2
0
10
20
30
40
† IRM = maximum recovery current
60
50
Time – ns
70
80
90
100
Figure 1. Reverse-Recovery-Current Waveform of Source-to-Drain Diodes
6
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TPIC1502
QUAD AND HEX POWER DMOS ARRAY
SLIS054 – OCTOBER 1996
PARAMETER MEASUREMENT INFORMATION
2
VDS = 14 V
VGS =0
TJ = 25°C
Q3A, Q4A, and Q5A
I S – Source-to-Drain Diode Current – A
1.5
1
Reverse di/dt = 100 A/µs
0.5
0
– 0.5
25% of IRM†
Shaded Area = QRR
–1
IRM†
– 1.5
trr(SD)
–2
0
10
20
30
40
50
60
Time – ns
70
80
90
100
† IRM = maximum recovery current
Figure 2. Reverse-Recovery-Current Waveform of Source-to-Drain Diodes
VDD = 14 V
RL
Pulse Generator
ten
VDS
10 V
VGS
VGS
0V
DUT
Rgen
tdis
50 Ω
50 Ω
td(off)
td(on)
CL 30 pF
(see Note A)
tr
tf
VDD
VDS
VDS(on)
VOLTAGE WAVEFORMS
TEST CIRCUIT
NOTE A: CL includes probe and jig capacitance.
Figure 3. Resistive-Switching Test Circuit and Voltage Waveforms
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7
TPIC1502
QUAD AND HEX POWER DMOS ARRAY
SLIS054 – OCTOBER 1996
PARAMETER MEASUREMENT INFORMATION
Current
Regulator
12-V
Battery
0.2 µF
Qg
Same Type
as DUT
50 kΩ
10 V
0.3 µF
Qgs(th)
VDD = 14 V
VDS
VGS
DUT
IG = 100 µA
0
Qgd
Gate Voltage
Time
IG CurrentSampling Resistor
ID CurrentSampling Resistor
VOLTAGE WAVEFORM
TEST CIRCUIT
Figure 4. Gate-Charge Test Circuit and Voltage Waveform
TYPICAL CHARACTERISTICS
GATE-TO-SOURCE THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
2.5
VDS = VGS
Q1A, Q1B, Q2A, Q2B
ID = 10 mA
2
1.5
ID = 100 µA
ID = 1 mA
1
0.5
0
– 40 – 20
0
20
40
60
80 100 120 140 160
TJ – Junction Temperature – °C
2.5
VGS(th) – Gate-to-Source Threshold Voltage – V
VGS(th) – Gate-to-Source Threshold Voltage – V
GATE-TO-SOURCE THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
ID = 10 mA
2
ID = 100 µA
1.5
ID = 1 mA
1
0.5
VDS = VGS
Q3A, Q3B, Q4A, Q4B, Q5A, Q5B
0
– 40 – 20
20
40
60
Figure 6
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80 100 120 140 160
TJ – Junction Temperature – °C
Figure 5
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TPIC1502
QUAD AND HEX POWER DMOS ARRAY
SLIS054 – OCTOBER 1996
TYPICAL CHARACTERISTICS
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
0.400
VGS = 10 V
0.250
VGS = 12 V
0.200
VGS = 15 V
0.150
0.100
0.50
On-State Resistance – Ω
0.300
r DS(on) – Static Drain-to-Source
On-State Resistance – Ω
r DS(on) – Static Drain-to-Source
0.350
0.60
ID = 1.5 A
Q1A, Q1B, Q2A, Q2B
VGS = 10 V
0.40
VGS = 15 V
0.30
VGS = 12 V
0.20
0.10
ID = 1.5 A
Q3A, Q3B, Q4A, Q4B, Q5A, Q5B
0.050
0
– 40 – 20
0
20
40
60
0
– 40 – 20
80 100 120 140 160
20
40
60
80 100 120 140 160
Figure 8
Figure 7
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
DRAIN CURRENT
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
DRAIN CURRENT
1
1
TJ = 25°C
Q3A, Q3B, Q4A
Q4B, Q5A, Q5B
VGS = 10 V
VGS = 15 V
VGS = 12 V
0.1
0.1
1
ID – Drain Current – A
10
On-State Resistance – Ω
r DS(on) – Static Drain-to-Source
On-State Resistance – Ω
TJ = 25°C
Q1A, Q1B, Q2A, Q2B
r DS(on) – Static Drain-to-Source
0
TJ – Junction Temperature – °C
TJ – Junction Temperature – °C
VGS = 10 V
VGS = 15 V
0.1
0.1
Figure 9
VGS = 12 V
1
ID – Drain Current – A
10
Figure 10
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9
TPIC1502
QUAD AND HEX POWER DMOS ARRAY
SLIS054 – OCTOBER 1996
TYPICAL CHARACTERISTICS
DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
4
DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
∆VGS = 1 V
(unless otherwise noted)
TJ = 25°C
Q1A, Q1B, Q2A, Q2B
3.5
4
VGS = 7 V
3.5
I D – Drain Current – A
2.5
VGS = 4 V
2
1.5
1
∆VGS = 1 V
(unless otherwise noted)
TJ = 25°C
Q3A, Q3B, Q4A, Q4B,
Q5A, Q5B
3
2.5
2
VGS = 5 V
1.5
1
VGS = 3 V
0.5
VGS = 3 V
0.5
0
0
7
8
9
2
3
4
5
6
VDS – Drain-to-Source Voltage – V
1
0
10
0
1
2
3
4
5
6
7
8
9
VDS – Drain-to-Source Voltage – V
Figure 11
DISTRIBUTION OF
FORWARD TRANSCONDUCTANCE
DISTRIBUTION OF
FORWARD TRANSCONDUCTANCE
40
Total Number of Units = 30
VDS = 14V
TJ = 25°C
ID = 750 mA
Q1A, Q1B, Q2A, Q2B
Percentage of Units – %
20
10
20
gfs – Forward Transconductance – S
Figure 14
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0.79
0.78
0.77
0.76
0.75
0.74
gfs – Forward Transconductance – S
Figure 13
10
0.72
0
0.71
1.24
1.23
1.22
1.2
1.21
1.19
1.18
1.17
1.16
1.15
1.14
10
1.13
0
30
Total Number of Units = 30
VDS = 14V
TJ = 25°C
ID = 750 mA
Q3A, Q3B, Q4A,
Q4B, Q5A, Q5B
0.7
Percentage of Units – %
40
30
10
Figure 12
0.73
I D – Drain Current – A
3
TPIC1502
QUAD AND HEX POWER DMOS ARRAY
SLIS054 – OCTOBER 1996
TYPICAL CHARACTERISTICS
DRAIN CURRENT
vs
GATE-TO-SOURCE VOLTAGE
DRAIN CURRENT
vs
GATE-TO-SOURCE VOLTAGE
4
4
Q1A, Q1B, Q2A, Q2B
TJ = – 40°C
TJ = – 40°C
TJ = 25°C
TJ = 25°C
3
I D – Drain Current – A
I D – Drain Current – A
3
TJ = 125°C
2
1
TJ = 125°C
2
1
Q3A, Q3B, Q4A, Q4B,
Q5A, Q5B
0
0
0
1
2
3
4
5
6
7
8
9
0
2
VGS – Gate-to-Source Voltage – V
4
6
10
12
14
VGS – Gate-to-Source Voltage – V
Figure 16
Figure 15
CAPACITANCE
vs
DRAIN-TO-SOURCE VOLTAGE
CAPACITANCE
vs
DRAIN-TO-SOURCE VOLTAGE
115
84
79
108
Ciss
Ciss
74
101
94
VGS = 0
f = 1 MHz
TJ = 25°C
Q1A, Q1B,
Q2A, Q2B
87
Coss
80
Capacitance – pF
Capacitance – pF
8
73
69
Coss
64
VGS = 0
f = 1 MHz
TJ = 25°C
Q3A, Q3B, Q4A,
Q4B, Q5A, Q5B
59
54
49
66
Crss
Crss
59
44
39
52
45
34
0
2
4
6
8
10
12
14
16
0
2
VDS – Drain-to-Source Voltage – V
4
6
8
10
12
14
16
VDS – Drain-to-Source Voltage – V
Figure 18
Figure 17
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
TPIC1502
QUAD AND HEX POWER DMOS ARRAY
SLIS054 – OCTOBER 1996
TYPICAL CHARACTERISTICS
SOURCE-TO-DRAIN DIODE CURRENT
vs
SOURCE-TO-DRAIN VOLTAGE
SOURCE-TO-DRAIN DIODE CURRENT
vs
SOURCE-TO-DRAIN VOLTAGE
10
VGS = 0
Q1A, Q1B, Q2A, Q2B
TJ = 150°C
TJ = 25°C
TJ = – 40°C
1
0.1
1
TJ = 25°C
TJ = – 40°C
10
Figure 20
DRAIN-TO-SOURCE VOLTAGE AND
GATE-TO-SOURCE VOLTAGE
vs
GATE CHARGE
DRAIN-TO-SOURCE VOLTAGE AND
GATE-TO-SOURCE VOLTAGE
vs
GATE CHARGE
14
14
12
12
10
10
VDD = 10 V
8
8
6
6
VDD = 12 V
4
4
VDD = 14 V
2
VDD = 12 V
0
0.2 0.4
0.6
0.8
1
1.2
1.4 1.6 1.8
VDS – Drain-to-Source Voltage – V
16
VGS – Gate-to-Source Voltage – V
14
16
10
14
12
10
VDD = 10 V
8
8
6
6
VDD = 14 V
4
2
0
0
4
VDD = 12 V
VDD = 12 V
VDD = 10 V
0
0.1 0.2
0.3
0
0.4
0.5 0.6
0.7 0.8
Qg – Gate Charge – nC
Figure 21
Figure 22
• DALLAS, TEXAS 75265
2
VDD = 14 V
Qg – Gate Charge – nC
POST OFFICE BOX 655303
16
ID = 0.75 A
TJ = 25°C
See Figure 4
Q3A, Q3B,
Q4A, Q4B,
Q5A, Q5B
12
2
2
10
1
VSD – Source-to-Drain Voltage – V
Figure 19
ID = 0.75 A
TJ = 25°C
Q1A, Q1B, Q2A, Q2B
See Figure 4
0
0.1
0.9
1
VGS – Gate-to-Source Voltage – V
1
VSD – Source-to-Drain Voltage – V
16
VDS – Drain-to-Source Voltage – V
TJ = 150°C
0.1
0.1
12
VGS = 0
Q3A, Q3B, Q4A, Q4B,
Q5A, Q5B
I SD – Source-to-Drain Diode Current – A
I SD – Source-to-Drain Diode Current – A
10
TPIC1502
QUAD AND HEX POWER DMOS ARRAY
SLIS054 – OCTOBER 1996
TYPICAL CHARACTERISTICS
REVERSE RECOVERY TIME
vs
REVERSE di/dt
70
trr – Reverse Recovery Time – ns
TJ = 25°C
See Figures 1 and 2
60
50
IS = 750 mA
Q3A, Q4A, Q5A
40
30
20
IS = 750 mA
Q1A, Q1B
10
0
0
20
40
60
80 100 120 140 160 180 200
Reverse di/dt – A/µs
Figure 23
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
TPIC1502
QUAD AND HEX POWER DMOS ARRAY
SLIS054 – OCTOBER 1996
THERMAL INFORMATION
MAXIMUM DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
100
I D – Maximum Drain Current – A
TC = 25°C
Q1A, Q1B, Q2A, Q2B
500 µs†
10 ms¶
1 ms†
1
ÁÁ
ÁÁ
θJC§
0.1
0.1
DC Conditions
θJA‡
1
10
100
VDS – Drain-to-Source Voltage – V
Figure 24
MAXIMUM DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
100
I D – Maximum Drain Current – A
TC = 25°C
Q3A, Q3B, Q4A, Q4B, Q5A, Q5B
500 µs†
10 ms¶
1 ms†
1
ÁÁ
ÁÁ
θJC§
θJA‡
DC Conditions
0.1
0.1
1
10
VDS – Drain-to-Source Voltage – V
Figure 25
† Less than 10% duty cycle
‡ Device is mounted on a 24 in2, 4 layer FR4 printed-circuit board.
§ Device is mounted in intimate contact with infinite heatsink.
¶ Less than 2% duty cycle
14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
100
TPIC1502
QUAD AND HEX POWER DMOS ARRAY
SLIS054 – OCTOBER 1996
THERMAL INFORMATION
DW PACKAGE†
JUNCTION-TO-BOARD THERMAL RESISTANCE
vs
PULSE DURATION
100
DC Conditions
RθJB – Junction-to-Board Thermal Resistance – °C/W
d = 0.5
d = 0.2
10
d = 0.1
d = 0.05
d = 0.02
d = 0.01
1
Single Pulse
tc
tw
ID
0
0.1
0.0001
0.001
0.01
0.1
1
10
100
tw – Pulse Duration – s
† Device is mounted on 24 in2, 4-layer FR4 printed circuit board with no heat sink.
NOTE A: ZθB(t) = r(t) RθJB
tw = pulse duration
tc = cycle time
d = duty cycle = tw/tc
Figure 26
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
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