Advance Technical Information Standard Power MOSFET IXTH 50P10 P-Channel Enhancement Mode Avalanche Rated RDS(on) Symbol Test Conditions Maximum Ratings VDSS TJ = 25°C to 150°C -100 V VDGR TJ = 25°C to 150°C; RGS = 1 MΩ -100 V VGS Continuous ±20 V VGSM Transient ±30 V ID25 TC = 25°C IDM TC = 25°C, pulse width limited by TJ IAR -50 A -200 A TC = 25°C -50 A EAR TC = 25°C 30 mJ PD TC = 25°C 300 W -55 ... +150 °C TJ TJM 150 °C Tstg -55 ... +150 °C 300 °C TL Maximum lead temperature for soldering 1.6 mm (0.062 in.) from case for 10 s Md Mounting torque VDSS ID25 1.13/10 Nm/lb.in. 6 Weight g TO-247 AD D (TAB) G = Gate, S = Source, Test Conditions Characteristic Values (TJ = 25°C, unless otherwise specified) min. typ. max. VDSS V GS = 0 V, ID = -250 µA -100 VGS(th) V DS = VGS, ID = -250 µA -3.0 IGSS V GS = ±20 VDC, VDS = 0 IDSS V DS = 0.8 VDSS V GS = 0 V RDS(on) V GS = -10 V, ID = 0.5 ID25 © 2002 IXYS All rights reserved TJ = 25°C TJ = 125°C V -5.0 V ±100 nA -25 -1 µA mA 55 mΩ D = Drain, TAB = Drain Features • International standard package JEDEC TO-247 AD • Low RDS (on) HDMOSTM process • • • Symbol = -100 V = -50 A Ω = 55 mΩ Rugged polysilicon gate cell structure Unclamped Inductive Switching (UIS) rated Low package inductance (<5 nH) - easy to drive and to protect Applications High side switching • • • • Push-pull amplifiers DC choppers Automatic test equipment Advantages • Easy to mount with 1 screw (isolated mounting screw hole) • Space savings • High power density 98905 (2/02) IXTH 50P10 Symbol Test Conditions Characteristic Values (TJ = 25°C, unless otherwise specified) min. typ. max. gfs V DS = -10 V; ID = ID25, pulse test Ciss 16 S 4200 pF 1720 pF Crss 750 pF td(on) 46 ns Coss V GS = 0 V, VDS = -25 V, f = 1 MHz 8 tr V GS = -10 V, VDS = 0.5 VDSS, ID = 0.5 ID25 39 ns td(off) RG = 4.7 Ω (External) 86 ns 38 ns 150 nC 36 nC 70 nC tf Qg(on) Qgs V GS = -10 V, VDS = 0.5 VDSS, ID = 0.5 ID25 Qgd 0.42 RthJC 0.25 RthCS Source-Drain Diode K/W K/W Characteristic Values (TJ = 25°C, unless otherwise specified) min. typ. max. Symbol Test Conditions IS V GS = 0 ISM Repetitive; pulse width limited by TJM VSD IF = IS, VGS = 0 V, Pulse test, t ≤ 300 µs, duty cycle d ≤ 2 % t rr IF = IS, di/dt = 100 A/µs, VR = -50 V -50 A -200 A -3 V 180 TO-247 AD Outline 1 2 3 Terminals: 1 - Gate 3 - Source Dim. 2 - Drain Tab - Drain Millimeter Min. Max. A 4.7 5.3 2.2 2.54 A1 A2 2.2 2.6 b 1.0 1.4 b1 1.65 2.13 b2 2.87 3.12 C .4 .8 D 20.80 21.46 E 15.75 16.26 e 5.20 5.72 L 19.81 20.32 L1 4.50 ∅P 3.55 3.65 Q 5.89 6.40 R 4.32 5.49 S 6.15 BSC Inches Min. Max. .185 .209 .087 .102 .059 .098 .040 .055 .065 .084 .113 .123 .016 .031 .819 .845 .610 .640 0.205 0.225 .780 .800 .177 .140 .144 0.232 0.252 .170 .216 242 BSC ns IXYS reserves the right to change limits, test conditions, and dimensions. IXYS MOSFETS and IGBTs are covered by one or more of the following U.S. patents: 4,835,592 4,850,072 4,881,106 4,931,844 5,017,508 5,034,796 5,049,961 5,063,307 5,187,117 5,237,481 5,486,715 5,381,025 6,306,728B1