TI CDC304

CDC304
OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER
SCAS325A – JULY 1990 – REVISED NOVEMBER 1995
D
D
D
D
D
D
D OR N PACKAGE
(TOP VIEW)
Replaces SN74AS304
Maximum Output Skew of 1 ns
Maximum Pulse Skew of 1.5 ns
TTL-Compatible Inputs and Outputs
Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
Package Options Include Plastic
Small-Outline (D) Package and Standard
Plastic (N) 300-mil DIPs
Q3
Q4
GND
GND
GND
Q5
Q6
Q7
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
Q2
Q1
CLR
VCC
VCC
CLK
PRE
Q8
description
The CDC304 contains eight flip-flops designed to have low skew between outputs. The eight outputs (in-phase
with CLK) toggle on successive CLK pulses. Preset (PRE) and clear (CLR) inputs are provided to set the Q
outputs high or low independent of the clock (CLK) input.
The CDC304 has output and pulse-skew parameters tsk(o) and tsk(p) to ensure performance as a clock driver
when a divide-by-two function is required.
The CDC304 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
OUTPUTS
Q1– Q8
CLR
PRE
CLK
L
H
X
L
H
L
X
L
L
X
H
L†
H
H
↑
Q0
H
H
L
Q0
† This configuration does not persist
when PRE or CLR returns to its
inactive (high) level.
logic symbol‡
15
16
PRE
10
1
S
2
CLK
11
6
T
7
CLR
14
8
R
9
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
‡ This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
CDC304
OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER
SCAS325A – JULY 1990 – REVISED NOVEMBER 1995
logic diagram (positive logic)
15
16
PRE
CLK
CLR
1
10
S
11
2
C1
14
6
R
Q1
Q2
Q3
Q4
Q5
1D
7
8
9
Q6
Q7
Q8
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Maximum power dissipation at TA = 55°C (in still air) (see Note 1): D package . . . . . . . . . . . . . . . . . . 0.77 W
N package . . . . . . . . . . . . . . . . . . . 1.2 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 300 mils,
except for the N package, which has a trace length of zero. For more information, refer to the Package Thermal Considerations
application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B.
recommended operating conditions
VCC
VIH
Supply voltage
VIL
IOH
Low-level input voltage
IOL
fclock
TA
Operating free-air temperature
2
High-level input voltage
MIN
NOM
MAX
4.5
5
5.5
2
UNIT
V
V
0.8
V
High-level output current
– 24
mA
Low-level output current
48
mA
80
MHz
70
°C
Input clock frequency
0
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
CDC304
OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER
SCAS325A – JULY 1990 – REVISED NOVEMBER 1995
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
VOH
VOL
II
IIH
IIL
IO‡
MIN
VCC = 4.5 V,
VCC = 4.5 V,
II = – 18 mA
IOH = – 2 mA
VCC = 4.5 V,
VCC = 4.5 V,
IOH = – 24 mA
IOL = 48 mA
VCC = 5.5 V,
VCC = 5.5 V,
VI = 7 V
VI = 2.7 V
VCC = 5.5 V,
VCC = 5.5 V,
VI = 0.4 V
VO = 2.25 V
VCC – 2
2
TYP†
MAX
UNIT
– 1.2
V
V
2.8
0.3
– 50
0.5
V
0.1
mA
20
µA
– 0.5
mA
– 150
mA
ICC
VCC = 5.5 V,
See Note 2
45
75
mA
† All typical values are at VCC = 5 V, TA = 25°C.
‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
NOTE 2: ICC is measured with CLK and PRE grounded, then with CLK and CLR grounded.
timing requirements
fclock
Clock frequency
tw
Pulse duration
tsu
Setup time before CLK↑
MIN
MAX
UNIT
0
80
MHz
CLR or PRE low
5
CLK high
4
CLK low
6
CLR or PRE inactive
6
ns
ns
switching characteristics over recommended operating free-air temperature range (see Figure 1)
PARAMETER
fmax§
tPLH
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
Q
Ω
RL = 500 Ω,
CL = 50 pF
PRE or CLR
Q
RL = 500 Ω,
Ω
CL = 50 pF
tsk(o)
CLK
Q
RL = 500 Ω,
See Figure 2
CL = 10 pF to 30 pF,
tsk(p)
k( )
CLK
RL = 500 Ω,
Ω
CL = 10 pF to 30 pF
tPHL
MAX
2
6
9
2
6
9
3
7
12
3
7
12
80
CLK
tPHL
tPLH
TYP†
MIN
Q1, Q8
Q2 – Q7
tr
tf
UNIT
MHz
1
1
1.5
ns
ns
ns
ns
4.5
ns
3.5
ns
† All typical values are at VCC = 5 V, TA = 25°C.
§ fmax minimum values are at CL = 0 to 30 pF.
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• DALLAS, TEXAS 75265
3
CDC304
OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER
SCAS325A – JULY 1990 – REVISED NOVEMBER 1995
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
Test Point
RL
CL
(see Note A)
LOAD CIRCUIT
3.5 V
CLR
or
PRE
1.3 V
0.3 V
tsu
tw
CLK
3.5 V
1.3 V
1.3 V
0.3 V
tPLH
tPHL
VOH
Q
1.3 V
1.3 V
VOL
NOTES: A. CL includes probe and jig capacitance.
B. Input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, tr = 2.5 ns, tf = 2.5 ns.
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
CDC304
OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER
SCAS325A – JULY 1990 – REVISED NOVEMBER 1995
PARAMETER MEASUREMENT INFORMATION
1
CLR, PRE
0
CLK
tPHL1
tPLH1
Q1
tPLH2
tPHL2
tPLH3
tPHL3
tPLH4
tPHL4
tPLH5
tPHL5
tPLH6
tPHL6
tPLH7
tPHL7
tPLH8
tPHL8
Q2
Q3
Q4
Q5
Q6
Q7
Q8
NOTES: A. tsk(o), CLK to Q, is calculated as the greater of the following:
– The difference between the fastest and slowest of tPLHn ( n = 1, 2, 3 . . ., 8 )
– The difference between the fastest and slowest of tPHLn ( n = 1, 2, 3 . . ., 8 )
B. tsk(p) is defined at the greater of | tPLHn – tPHLn | ( n = 1, 2, 3, . . ., 8 ).
Figure 2. Waveforms for Calculation of tsk(o) and tsk(p)
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5
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