CDC3S04 SCAS883B – OCTOBER 2009 – REVISED MAY 2011 www.ti.com Quad Sine-Wave Clock Buffer With LDO Check for Samples: CDC3S04 FEATURES DESCRIPTION • • The CDC3S04 is a four-channel low-power low-jitter sine-wave clock buffer. It can be used to buffer a single master clock to multiple peripherals. The four sine-wave outputs (CLK1–CLK4) are designed for minimal channel-to-channel skew and ultralow additive output jitter. 1 • • • • • • • • 1:4 Low-Jitter Clock Buffer Single-Ended Sine-Wave Clock Input and Outputs Ultralow Phase Noise and Standby Current Individual Clock Request Inputs for Each Output On-Chip Low-Dropout Output (LDO) for Low-Noise TCXO Supply Serial I2C Interface (Compatible With High-Speed Mode, 3.4 Mbit/s) 1.8-V Device Power Supply Wide Temperature Range, –30°C to 85°C ESD Protection: 2 KV HBM, 750 V CDM, and 100 V MM Small 20-Pin Chip-Scale Package: 0.4-mm Pitch WCSP (1.6 mm × 2 mm) Each output has its own clock request inputs which enables the dedicated clock output. These clock requests are active-high (can also be changed to be active-low via I2C), and an output signal is generated that can be sent back to the master clock to request the clock (MCLK_REQ). MCKL_REQ is an open-source output and supports the wired-OR function (default mode). It needs an external pulldown resistor. MCKL_REQ can be changed to wired-AND or push-pull functionality via I2C. The CDC3S04 also provides an I2C interface (Hs-mode) that can be used to enable or disable the outputs, select the polarity of the REQ inputs, and allow control of internal decoding. APPLICATIONS • • • • • The CDC3S04 features an on-chip high-performance LDO that accepts voltages from 2.3 V to 5.5 V and outputs a 1.8-V supply. This 1.8-V supply can be used to power an external 1.8-V TCXO. It can be enabled or disabled for power saving at the TCXO. Cellular Phones Smart Phones Mobile Handsets Portable Systems Wireless Modems Including GPS, WLAN, W-BT, D-TV, DVB-H, FM Radio, WiMAX, and System Clock VDD_DIG VDD_ANA WCSP LDO VBAT VLDO REQ1 RESET Reset A CLK1 B REQ2 MCLK_IN CLK2 CLK3 REQ4 SCLH SDAH ADR_A0 2 CLK2 MCLK_ RESET IN REQ1 CLK1 VDD_ ANA GND_ ANA C REQ4 CLK4 REQ3 CLK3 D VDD_ DIG GND_ MCLK_ REQ DIG ADR_ A0 E VLDO VBAT SDAH SCLH 1 2 3 4 REQ3 MCLK_REQ REQ2 CLK4 I C Control Register Top View (Solder Ball Underneath) Decoder GND_DIG GND_ANA 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009–2011, Texas Instruments Incorporated CDC3S04 SCAS883B – OCTOBER 2009 – REVISED MAY 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. DESCRIPTION (CONTINUED) A low signal at the RESET input switches the outputs CLK1 and CLK4 into the default state. In this configuration, CLK1 and CLK4 are ON (see Table 1); the remaining device function is not affected. Also, the RESET input provides a glitch filter which rejects spikes of typical 300 ns on the RESET line to preserve false reset. A complete device reset to the default condition can be initiated by a power-up cycle of VDD_DIG. The CDC3S04 operates from two 1.8-V supplies. There is a core supply (VDD_DIG/GND_DIG) for the core logic and a low-noise analog supply (VDD_ANA/GND_ANA) for the sine-wave outputs. The CDC3S04 is designed for sequence-less power up. Both supply voltages may be applied in any order. The CDC3S04 is offered in a 0.4-mm pitch WCSP package (1.6 mm × 2 mm) and is optimized for low standby current (0.5 µA). It is characterized for operation from –30°C to 85°C. DEVICE INFORMATION PIN FUNCTIONS NAME BALL NO. TYPE FUNCTION ADR_A0 D4 Input Selectable address bit A0 of slave-address register; internal 500-kΩ pulldown resistor CLK1 A4 Output Clock output 1 CLK2 A2 Output Clock output 2 CLK3 C4 Output Clock output 3 CLK4 C2 Output Clock output 4 GND_ANA B4 Ground Ground for sine-wave buffer GND_DIG D2 Ground Ground for core logic MCLK_IN B1 Input Master clock input MCLK_RE Q D3 Output Clock request to the master clock source; active-high; open-source output for wired-OR connection (default condition). Can be changed to push-pull output or wired-AND output via I2C. REQ1 A3 Input Clock request from peripheral 1; internal 500-kΩ pulldown resistor REQ2 A1 Input Clock request from peripheral 2; internal 500-kΩ pulldown resistor REQ3 C3 Input Clock request from peripheral 3; internal 500-kΩ pulldown resistor REQ4 C1 Input Clock request from peripheral 4; internal 500-kΩ pulldown resistor RESET B2 Input Peripheral reset signal provided by application processor. The signal is active-low and switches CLK1 and CLK4 outputs to ON (see Table 1). On-chip LDO is enabled. Internal 1-MΩ pullup resistor and 300-ns (typ) glitch filter. SCLH E4 Input I2C clock input – Hs-mode. Internal 1-MΩ pullup resistor SDAH E3 Input/output I2C data input/output – Hs-mode. Internal 1-MΩ pullup resistor VBAT E2 Power Supply pin to internal LDO VDD_ANA B3 Power 1.8-V power supply for sine-wave buffer VDD_DIG D1 Power 1.8-V power supply for core logic. Power up of VDD_DIG resets the whole device to the default condition. VLDO E1 Output 1.8-V supply for external TCXO; LDO is enabled if RESET (default mode) or REQx is active. LDO is not enabled if only VBAT is on. 2 Copyright © 2009–2011, Texas Instruments Incorporated CDC3S04 SCAS883B – OCTOBER 2009 – REVISED MAY 2011 www.ti.com FUNCTION SELECTION TABLES Table 1. Reset and Request (REQx) Conditions for Clock Outputs (1) RESET (2) PRIORITY BIT (3) 0 (3) On 1 1 (1) (2) CLK1 0 CLK2 CLK3 Controlled by REQ2 Controlled by REQ3 CLK4 Controlled by REQ2INT Controlled by REQ3INT On 0 Controlled by REQ1 Controlled by REQ2 Controlled by REQ3 Controlled by REQ4 1 Controlled by REQ1INT Controlled by REQ2INT Controlled by REQ3INT Controlled by REQ4INT Shaded cells show the default setting after power up. RESET resets REQ1PRIO/REQ4PRIO and REQ1INT/REQ4INT bits to their default values (CLK1/4 is ON) but does not change the remaining internal SW bits. During RESET, any I2C operation is blocked until RESET is deactivated. A minimum pulse duration of 500 ns must be applied to activate RESET (the internal glitch-filter suppresses spikes of typical 300 ns). Priority bit defines if the external control pins (HW controlled) or the SW bits (SW controlled) have priority. It can be set in the configuration register, Byte 2, Bits 0–3. Table 2. Request Signal Condition for Clock Outputs (1) REQ-Signals (2) REQx (REQ1/2/3/4) CLKx (CLK1/2/3/4) MCLK_REQ LDO (3) Active-low 0 Clock High On 1 Disabled to high Low (if all REQx are high) Off (if all REQx are high) 0 Disabled to high (4) Low (if all REQx are low) Off (if all REQx are low) 1 Clock (4) High On Active-high (1) (2) (3) (4) Shaded cells show the default setting after power up. Polarity of REQ1, REQ2, REQ3, and REQ4 are register-configurable via I2C (see Table 3, Byte 0, Bits 0–3). Default setting is active-high. The LDO is controlled by an on-chip decoder, but can also be SW controlled (see Table 3, Byte 2, Bits 4–5). CLK1 and CLK4 are ON after device power up (default condition). CLK2 and CLK3 are controlled by external REQ2 and REQ3, respectively. POWER GROUPS NAME DESCRIPTION VBAT Supply pin for LDO provided by main battery. LDO is not working if only VBAT is on. VLDO 1.8-V low-drop output voltage for external TCXO. LDO is enabled if VBAT and VDD_DIG are on and REQx or RESET is active (see Table 2). VDD_DIG 1.8-V power supply for core logic and I2C logic. VDD_DIG must be supplied for correct device operation. Power up of VDD_DIG resets the whole device to the default condition. VDD_ANA 1.8-V power supply for sine-wave buffers. For correct sine-wave buffer function, all three power supplies (VBAT, VDD_DIG and VDD_ANA) must be on. But, VDD_ANA can be switched on and off at any time. If off, the sine-wave outputs are switched to high-impedance. POWER-UP SEQUENCE The CDC3S04 is designed for sequence-less power up. VBAT, VDD_DIG, and VDD_ANA may be applied in any order. Recommended power-on sequence is VBAT first, followed by VDD_DIG and VDD_ANA. Recommended power-off sequence is in reverse order. Copyright © 2009–2011, Texas Instruments Incorporated 3 CDC3S04 SCAS883B – OCTOBER 2009 – REVISED MAY 2011 www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) VDD_ANA VDD_DIG Supply voltage range VBAT Battery supply voltage range VI Input voltage range (2) VO Output voltage range VLDO Output voltage range (1) (3) (2) (3) VALUE UNIT –0.5 to 2.5 V –0.5 to 6.5 V –0.5 to VDD + 0.5 V –0.5 to VDD + 0.5 V –0.5 to VBAT + 0.5 V Input current (Vi < 0, Vi > VDD) ±20 mA IO Continuous output current ±20 mA ILDO Continuous output current ±20 mA Tstg Storage temperature range –65 to 150 °C (1) (2) (3) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed. The input VI and output VO positive voltages are limited to the absolute maximum rating for VDD = 2.5 V. THERMAL CHARACTERISTICS for 20-pin WCSP (YFF) (1) PARAMETER AIRFLOW (lfm) 20-PIN WCSP 0 71 200 62 UNIT °C/W TJA Thermal resistance, junction-to-ambient 400 59 TJC Thermal resistance, junction-to- case – 17.5 °C/W TJB Thermal resistance, junction-to-board – 20.5 °C/W TJ Maximum junction temperature – 125 °C (1) The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board). RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT VDD_ANA Device supply voltage 1.65 1.8 1.95 V VDD_DIG Device supply voltage 1.65 1.8 1.95 V VIH Input voltage ADR_A0, REQx, RESET VIL 0.65 VDD_DIG VIS Sine-wave input voltage – MCLK_IN; ac-coupled amplitude CL Sine-wave output load (1) COUT LDO output capacitance (stabilize the internal control loop) 0.8 TA Operating free-air temperature –30 (1) 4 V 0.35 VDD_DIG 0.5 10 V 1.2 VPP 30 pF µF 2.2 85 °C 2 10 pF is the typical load-driving capability. The drive capability can be optimized for 30 pF by the I C register (Byte 3, Bits 7–4). Copyright © 2009–2011, Texas Instruments Incorporated CDC3S04 SCAS883B – OCTOBER 2009 – REVISED MAY 2011 www.ti.com ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 0.1 0.2 2 2.6 UNIT OVERALL PARAMETER IDD_ANA VBAT = 5.5 V; VDD_ANA = 1.95 V; Analog supply current (1) LDO is on; VIS = 1 VPP; (seeFigure 8 through Figure 12) fMCLK_IN = 38.4 MHz; RL = 10 kΩ; CL = 10 pF (2) IDD_DIG Digital supply current (see Figure 8 through Figure 12) VBAT = 5.5 V; VDD_DIG = 1.95 V; VDD_ANA = off; LDO = off; VIS = 1 Vpp; fMCLK_IN = 38.4 MHz; CL= 10 pF; RL= 10 kΩ ISB Standby current VBAT = 5.5 V; VDD_DIG/VDD_ANA = 1.95 V; All outputs disabled (no input clock; LDO off; no REQ; RESET is inactive; I2C is in idle mode); includes 1-MΩ pullup at I2C and RESET fMCLK_IN Input frequency Sine wave VOH VOL VIK IIH IIL MCLK_REQ high-level output voltage MCLK_REQ low-level output voltage LVCMOS input voltage Input current ADR_A0, REQx (500-kΩ pulldown) Input current RESET (1-MΩ pullup) Input current ADR_A0, REQx (500-kΩ pulldown) Input current RESET (1-MΩ pullup) Off (no REQ) Per output 0.01 Wired-OR output; IOH = –2 mA; VDD_DIG = 1.65 V (See Figure 3.) VDD_DIG – 0.45 Push-pull output; VDD_DIG = 1.65 V, IOH = –2 mA VDD_DIG – 0.45 mA 0.1 mA 0.5 10 µA 38.4 52 MHz V Wired-AND output; IOL = 2 mA VDD_DIG = 1.65 V 0.45 Push-pull output; VDD_DIG = 1.65 V, IOL = 2 mA 0.45 VDD_DIG = 1.65 V; II = –18 mA –1.2 V V 6 µA VI = VDD_DIG; VDD_DIG = 1.95 V 2 –2 µA VI = 0 V; VDD_DIG = 1.95 V –3 CI Input capacitance ADR_A0, REQx, RESET VIK SCLH/SDAH input clamp voltage VDD_DIG = 1.65 V; II = –18 mA II SCLH/SDAH input current 0.1 VDD_DIG < VI < 0.9 VDD_DIG VIH SDA/SCL input high voltage VIL SDAH/SCLH input low voltage Vhys Hysteresis of Schmitt-trigger inputs VOL SDAH low-level output voltage IOL = 3 mA, VDD_DIG = 1.65 V SCLH input capacitance VI = 0 V or VI = VDD_DIG (3) 3 5 SDAH input capacitance VI = 0 V or VI = VDD_DIG (3) 8 10 VI = 0 V or VDD_DIG 3 pF SDAH/SCLH PARAMETER (Hs-Mode) CI (1) (2) (3) –1.2 V 10 µA 0.7 VDD_DIG V 0.3 VDD_DIG 0.1 VDD_DIG V V 0.2 VDD_DIG V pF The total current consumption when no output is active is calculated by IDD_ANA(off) + IDD_DIG. For CL = 30 pF, the typical current for one output is 2.2 mA (see Figure 8). The I2C standard specifies a maximum CI of 10 pF. Copyright © 2009–2011, Texas Instruments Incorporated 5 CDC3S04 SCAS883B – OCTOBER 2009 – REVISED MAY 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 52 MHz SINE-WAVE PARAMETER (MCLK_IN is sine-wave signal, CL = 10 pF) fOUT Output frequency VOS Output gain level (see Figure 17) MCLK_IN-to-CLKx; 10 kΩ, 0.5 ≤ VIS ≤ 1.2 VPP 10 pF; ac-coupled; fMCLK_IN > 1 MHz VIS = 0.5 VPP Output voltage tjitadd(rms) Additive rms jitter (4) pnadd Additive phase noise at fOUT = 38.4 MHz (5) RIN Input resistance CIN Input capacitance –1 –0.3 0 dB 445 mVPP 490 500 10 Hz to 10 MHz; fOUT = 38.4 MHz 0.3 0.6 10 kHz to 10 MHz; fOUT = 38.4 MHz 0.1 0.2 At offset = 1 kHz –142 –135 At offset = 10 kHz –152 –145 At offset = 100 kHz –157 –150 At dc level 12 fMCLK_IN = 38.4 MHz 15 5 psRMS dBc/Hz kΩ 7 pF 5.5 V 1.9 V ELECTRICAL CHARACTERISTIC of LDO (COUT = 0.8 to 2.7 µF) (6) VBAT VLDO Input voltage range LDO output voltage 2.3 (7) 2.3 V < VBAT < 5.5 V, lLOAD = 5 mA 1.72 1.8 Maximum line regulation 2.3 V < VBAT ≤ 5.5 V, lLOAD = 5 mA 0.5% Maximum load regulation 0 < ILOAD < 5 mA, VBAT = 2.3 V or 5.5 V; TJ = 25°C 0.5% ILOAD Load current COUT = 0.8 µF to 2.7 µF 0 ILCL LDO output current limit VLDO = 0.9 × VLDO(TYP) 10 ILGND LDO ground pin current (8) VBAT = 3.6 V; 0 < ILOAD < 5 mA ILSHDN LDO shutdown current 2.3 V < VBAT < 5.5 V ΔVLDO PSRR VN (4) (5) (6) (7) (8) 6 VBAT = 2.3 V (for min) VBAT = 2.5 V (for typ) Power-supply rejection ratio (ripple rejection) (see Figure 20) VLDO = 1.8 V ILOAD = 5 mA Vripple = 0.1 Vpp Output noise voltage (see Figure 21) 5 50 100 Hz 60 68 1 kHz 55 62 10 kHz 45 52 100 kHz 33 40 1 MHz 37 46 10 MHz 60 67 BW = 10 Hz to 100 kHz; VLDO = 1.8 V; ILOAD= 5 mA mA 60 mA 150 µA 0.2 µA dB 30 µVRMS Additive rms jitter is the integrated rms jitter that the device adds to the signal chain. It is calculated by t jitadd(rms) = (t jitout(rms)2 - t jitin(rms)2 ) . Specified with the supply ripple noise of 30 µV(rms) from 10 Hz to 100 kHz. Additive phase noise is the amount of phase noise that the device adds to the signal chain. It is calculated by Ladd (dB) = 10 log (100.1 Lout – 100.1 Lin). Minimum COUT should be 100 nF to allow for stable LDO operation. LDO output voltage includes maximum line and load regulation. LDO ground pin current does not change over VBAT. Copyright © 2009–2011, Texas Instruments Incorporated CDC3S04 SCAS883B – OCTOBER 2009 – REVISED MAY 2011 www.ti.com TIMING REQUIREMENTS over operating free-air temperature range (unless otherwise noted) VLDO = 1.8 V; CL = 10 pF; RL = 10 kΩ PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT TIMING PARAMETER tPD tLH Propagation delay time MCLK_IN-to-CLKx; fMCLK_IN = 38.4 MHz Propagation delay time, low-to-high REQx-to-MCLK_REQ (wired-OR, CL= 15 pF, RL= 10 kΩ); CLKx on-time – REQ-to-CLKx CLKx on-time – RESET-to-CLKx (3) tCLK (2) CLKx off-time – REQ-to-CLKx CLKx on-time – VDD_ANA to-CLKx tSP Pulse duration of spikes that must be suppressed by the input filter for RESET (3) tsk(o) Output skew (4) fMCLK_IN = 38.4 MHz; VVDD_ANA is on; VIS = 1 V; VOS = –1 dB (see Figure 5 and Figure 6) fMCLK_IN = 38.4 MHz ; VIS = 1 V; VOS = –1 dB; measurement starts when VDD_ANA is 90% of 1.7 V (see Figure 7) 3 ns 15 ns 0.3 0.4 µs 0.6 0.8 µs 25 ns 50 µs 100 ns 20 fMCLK_IN = 38.4 MHz; CLK1-to-CLK4 25 50 ps VLDO = 1.7 V, ILDO = 5 mA, 2.3 V < VBAT < 5.5 V; COUT = 2.7 µF 100 300 µs (5) LDO on-time – REQ-to-LDO; – RESET-to-LDO tLDO (1) (2) (3) (4) (5) All typical values are at nominal VDD_ANA and VDD_DIG. CLK on-time is measured with valid input signal (VIS = 1 Vpp). In case a TXCO is used, the LDO and TCXO are already on. Pulses above 500 ns are interpreted as a valid reset signal. Total time from RESET-to-CLKx is the sum of tSP + tCLK_/RESET. Output skew is calculated as the greater of the difference between the fastest and the slowest tPLH or the difference between the fastest and the slowest tPHL. LDO off-time depends on the discharge time of the R-C components (seeFigure 4). PARAMETER MIN MAX UNIT SDAH/SCLH TIMING REQUIREMENTS, Hs-Mode (CBUS = 100 pF for each I2C line; see Figure 24 and Figure 25) fSCLH SCLH clock frequency tsu(START) START setup time (SCLH high before SDAH low) 160 ns th(START) START hold time (SCLH low after SDAH low) 160 ns tLOW Low period of the SCLH clock 160 ns tHIGH High period of the SCLH clock 60 th(SDAH) SDAH hold time (SDAH valid after SCLH low) tsu(SDAH) SDAH setup time 10 SCLH rise time 10 40 SDAH rise time 10 80 SCLH fall time 10 40 10 80 tr tf SDAH fall time tsu(STOP) STOP setup time tSP Pulse duration of spikes that must be suppressed by the input filter for SDAH and SCLH (1) 0 0 (1) 3.4 ns 70 ns ns 160 0 MHz ns ns ns 10 ns A device must internally provide a data hold time to bridge the undefined period between VIH and VIL of the falling edge of the SCLH signal. An input circuit with a threshold as low as possible for the falling edge of the SCLH signal minimizes this hold time. Copyright © 2009–2011, Texas Instruments Incorporated 7 CDC3S04 SCAS883B – OCTOBER 2009 – REVISED MAY 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION Measuring Point 10 nF 100 nF 15 K TCXO 15 K 10 pF Figure 1. Input Circuit 10 kW Figure 2. Output Circuit LDO 200 W VLDO 10 kW Figure 3. Wired OR 8 TCXO 2.2 mF i.e. time constant(RxC) is 440 ms for 63% discharge. Figure 4. LDO Output Circuit Copyright © 2009–2011, Texas Instruments Incorporated CDC3S04 SCAS883B – OCTOBER 2009 – REVISED MAY 2011 www.ti.com TYPICAL CHARACTERISTICS CLKx on Time RESET CLKx 90% of Final Amplitude Figure 5. CLKx On-Time From RESET Off-to-On REQx CLKx on Time CLKx 90% of Final Amplitude Figure 6. CLKx On-Time From REQ Off-to-On 90% of 1.7 V VDD_ANA CLKx on Time CLKx 90% of Final Amplitude 100 ms 200 ms 300 ms 400 ms 500 ms 600 ms 700 ms 800 ms 900 ms Figure 7. CLKx On-Time From VDD_ANA Off-to-On Copyright © 2009–2011, Texas Instruments Incorporated 9 CDC3S04 SCAS883B – OCTOBER 2009 – REVISED MAY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) SUPPLY CURRENT (IDD_ANA, IDD_DIG) vs OUTPUT LOAD (CL) AT 38.4 MHz INPUT CLOCK 10 9 IDD_ANA / CLK1&CLK2&CLK3&CLK4 Supply Current – mA 8 7 IDD_ANA / CLK1&CLK2&CLK3 6 5 IDD_ANA / CLK1&CLK2 4 3 IDD_ANA / CLK1 2 1 IDD_ANA / CLKx off IDD_DIG 0 0 5 10 15 20 25 30 Output Load – pF 35 40 45 50 Figure 8. SUPPLY CURRENT (IDD_ANA, IDD_DIG) vs OUTPUT LOAD (CL) AT 26 MHz INPUT CLOCK 10 9 IDD_ANA / CLK1&CLK2&CLK3&CLK4 Supply Current – mA 8 7 IDD_ANA / CLK1&CLK2&CLK3 6 5 IDD_ANA / CLK1&CLK2 4 3 IDD_ANA / CLK1 2 1 IDD_ANA / CLKx off IDD_DIG 0 0 5 10 15 20 25 30 Output Load – pF 35 40 45 50 Figure 9. SUPPLY CURRENT (IDD_ANA, IDD_DIG) vs INPUT FREQUENCY (MCLK_IN) 9 IDD_ANA / CLK1&CLK2&CLK3&CLK4 8 Supply Current – mA 7 IDD_ANA / CLK1&CLK2&CLK3 6 5 IDD_ANA / CLK1&CLK2 4 3 IDD_ANA / CLK1 2 1 IDD_ANA / CLKx off IDD_DIG 0 0 1 10 Input Frequency – MHz 100 Figure 10. 10 Copyright © 2009–2011, Texas Instruments Incorporated CDC3S04 SCAS883B – OCTOBER 2009 – REVISED MAY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) SUPPLY CURRENT (IDD_ANA, IDD_DIG) vs INPUT VOLTAGE LEVEL AT 38.4 MHz INPUT CLOCK 9 IDD_ANA / CLK1&CLK2&CLK3&CLK4 8 Supply Current – mA 7 IDD_ANA / CLK1&CLK2&CLK3 6 5 IDD_ANA / CLK1&CLK2 4 3 IDD_ANA / CLK1 2 1 IDD_ANA / CLKx off 0 0.5 0.6 IDD_DIG 0.7 0.8 0.9 Input Voltage Level – VPP 1.0 1.1 1.2 Figure 11. SUPPLY CURRENT (IDD_ANA, IDD_DIG) vs INPUT VOLTAGE LEVEL AT 26 MHz INPUT CLOCK 9 IDD_ANA / CLK1&CLK2&CLK3&CLK4 8 Supply Current – mA 7 IDD_ANA / CLK1&CLK2&CLK3 6 5 IDD_ANA / CLK1&CLK2 4 3 IDD_ANA / CLK1 2 1 IDD_ANA / CLKx off 0 0.5 0.6 IDD_DIG 0.7 0.8 0.9 Input Voltage Level – VPP 1.0 1.1 1.2 Figure 12. Copyright © 2009–2011, Texas Instruments Incorporated 11 CDC3S04 SCAS883B – OCTOBER 2009 – REVISED MAY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) TCXO INPUT CLOCK vs OUTPUT CLOCK AT 38.4 MHz MCLK_IN input signal from TCXO CDC3S04 output signal at CLKx Figure 13. TCXO INPUT CLOCK vs OUTPUT CLOCK AT 26 MHz MCLK_IN input signal from TCXO CDC3S04 output signal at CLKx Figure 14. 12 Copyright © 2009–2011, Texas Instruments Incorporated CDC3S04 SCAS883B – OCTOBER 2009 – REVISED MAY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) SINE WAVE INPUT CLOCK vs OUTPUT CLOCK AT 38.4 MHz MCLK_IN sinusoidal input signal CDC3S04 output signal at CLKx Figure 15. SINE WAVE INPUT CLOCK vs OUTPUT CLOCK AT 26 MHz MCLK_IN sinusoidal input signal CDC3S04 output signal at CLKx Figure 16. Copyright © 2009–2011, Texas Instruments Incorporated 13 CDC3S04 SCAS883B – OCTOBER 2009 – REVISED MAY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) OUTPUT GAIN vs INPUT FREQUENCY (MCLK_IN) 1 0 VIS = 1 VPP VDD_ANA = 1.8 V Output Gain – dB -1 –2 –3 –4 –5 –6 –7 1k 10k 100k 1M 10M 100M Input Frequency – Hz Figure 17. INPUT vs OUTPUT PHASE-NOISE PERFORMANCE WITH 38.4-MHz TCXO CLKx Output CLKx Output Highdrive MCLK_IN Input Figure 18. 14 Copyright © 2009–2011, Texas Instruments Incorporated CDC3S04 SCAS883B – OCTOBER 2009 – REVISED MAY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) INPUT vs OUTPUT PHASE-NOISE PERFORMANCE WITH 26-MHz TCXO CLKx Output CLKx Output Highdrive MCLK_IN Input Figure 19. LDO POWER SUPPLY REJECTION vs FREQUENCY (PSRR) REF 50.000 dB 5.000 dB/div 80 dB 75 dB 70 dB 65 dB 60 dB 55 dB 50 dB 45 dB 40 dB START 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz STOP 10 MHz Figure 20. Copyright © 2009–2011, Texas Instruments Incorporated 15 CDC3S04 SCAS883B – OCTOBER 2009 – REVISED MAY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) LDO OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY 1800 Spectral Noise Density – nV/ Hz 1600 1400 1200 1000 800 600 400 200 0 10 100 1k 10k 100k Frequency – Hz Figure 21. 16 Copyright © 2009–2011, Texas Instruments Incorporated CDC3S04 SCAS883B – OCTOBER 2009 – REVISED MAY 2011 www.ti.com DETAILED DESCRIPTION SDAH/SCLH SERIAL INTERFACE (Hs-Mode) This section describes the SDAH/SCLH interface of the CDC3S04 device. The CDC3S04 operates as a slave device of the two-wire serial SDAH/SCLH bus, compatible with the popular I2C specification (UM10204-I2C-bus specification and user manual Rev. 03–19 June 2007). It operates in the high-speed mode (up to 3.4 Mbit/s) and supports 7-bit addressing. The CDC3S04 is fully downward compatible with fast- and standard-mode (F/S) devices for bidirectional communication in a mixed-speed bus system. Data Protocol The device supports byte-write and byte-read operations only. There is no block-write or block-read operation supported; therefore, no command code byte is needed. When a byte has been sent, it is written into the internal register and is immediately effective. Slave Receiver Address (7 bits) Device A6 A5 A4 A3 A2 A1 A0 (1) R/W CDC3S04 1 1 0 1 1 0 0 1/0 (1) Address bit A0 is selectable by the ADR_A0 input (pin D1). This allows addressing of two devices connected to the same I2C bus. The default value is 0, set by an internal pulldown resistor. Byte-Write Programming Sequence F/S-Mode S Master Code Hs-Mode A Sr Slave Address 0000 1XXX (Hs-Mode Master Code) R/W A 0 (Write) Data A Data A P Data Transferred (n Bytes + Acknowledge) A = Acknowledge (SDAH LOW) A = Acknowledge (SDAH HIGH) S = START Condition P = STOP Condition From Master to Slave From Slave to Master Figure 22. Byte-Write Protocol Byte-Read Programming Sequence F/S-Mode S Master Code Hs-Mode A 0000 1XXX (Hs-Mode Master Code) Sr Slave Address R/W A 1 (Read) From Master to Slave From Slave to Master Data A Data A P Data Transferred (n Bytes + Acknowledge) A = Acknowledge (SDAH LOW) A = Acknowledge (SDAH HIGH) S = START Condition P = STOP Condition Figure 23. Byte-Read Protocol Copyright © 2009–2011, Texas Instruments Incorporated 17 CDC3S04 SCAS883B – OCTOBER 2009 – REVISED MAY 2011 www.ti.com Sr Sr P tr(DA) tf(DA) SDAH tsu(STA) th(DAT) th(STA) tsu(DAT) tsu(STO) SCLH tr(CL1) (1) t(Low) t(High) (1) tr(CL) tf(CL) tr(CL1) t(Low) t(High) = MCS current source pull-up = Rp resistor pull-up T0451-01 (1) First rising edge of the SCLH signal after Sr and after each acknowledge bit. Figure 24. Definition of Timing for a Complete Hs-Mode Transfer The following diagram shows how the CDC3S04 clock buffer is connected to the SDAH/SCLH serial interface bus. Multiple devices can be connected to the bus, but the speed may need to be reduced (3.4 MHz is the maximum) if many devices are connected. Note that the pullup resistors (RP) depend on the supply voltage, bus capacitance, and number of connected devices. For more details, see the I2C bus specification. CDC3S04 Rp Rp Master Slave SDAH SCLH CBUS CBUS Figure 25. SDAH/SCLH Hardware Interface SDAH/SCLH Configuration Registers The output stages are user configurable. Table 3 explains the programmable functions of the CDC3S04. 18 Copyright © 2009–2011, Texas Instruments Incorporated CDC3S04 SCAS883B – OCTOBER 2009 – REVISED MAY 2011 www.ti.com Table 3. Configuration Register (Shaded Cells Marks Power-Up/Default Setting) Offset 00h 01h BIT (1) Acronym Default (2) 0 1 7 REQ4INT 1b 1b CLK4 off/on (4) Off On 6 REQ3INT 0b – CLK3 off/on (4) Off On 5 REQ2INT 0b – CLK2 off/on (4) Off On 4 REQ1INT 1b 1b CLK1 off/on (4) Off On 3 REQ4POL 1b – Selects polarity of REQ4 Active-low Active-high 2 REQ3POL 1b – Selects polarity of REQ3 Active-low Active-high 1 REQ2POL 1b – Selects polarity of REQ2 Active-low Active-high 0 REQ1POL 1b – Selects polarity of REQ1 Active-low Active-high Not used for decoding Used for decoding 03h 04h–Bh (5) (1) (2) (3) (4) (5) (3) Description 7 MREQ4 1b – Defines if REQ4 is used to decode MCLK_REQ 6 MREQ3 1b – Defines if REQ3 is used to decode MCLK_REQ 5 MREQ2 1b – Defines if REQ2 is used to decode MCLK_REQ 4 MREQ1 1b – Defines if REQ1 is used to decode MCLK_REQ 3 MCLKOUT1 00b – Selects MCLK_REQ output type 00 = wired-OR (default setting) 01 = wired-AND 1x = push-pull 00b – Reserved 00b – MCLK_REQ generation (see Figure 27) 0x = decoder controlled (default setting) 10 = low 11 = high 00b – Switches LDO on or off: 00 = LDO is on (default setting) 01 = LDO is off 1x = decoder controlled (see Figure 27) 2 02h RESET MCLKOUT0 0–1 – 7 MREQCTRL1 6 MREQCTRL0 5 LDOEN1 R/W R/W 4 LDOEN0 3 REQ4PRIO 1b 1b Defines external vs internal REQ4 priority REQ4 REQ4INT 2 REQ3PRIO 0b – Defines external vs internal REQ3 priority REQ3 REQ3INT 1 REQ2PRIO 0b – Defines external vs internal REQ2 priority REQ2 REQ2INT 0 REQ1PRIO 1b 1b Defines external vs internal REQ1 priority REQ1 REQ1INT 7 HIGHDRIVE4 0b – Enables high-drive capability CLK4 Typical High 6 HIGHDRIVE3 0b – Enables high-drive capability CLK3 Typical High 5 HIGHDRIVE2 0b – Enables high-drive capability CLK2 Typical High 4 HIGHDRIVE1 0b – Enables high-drive capability CLK1 Typical High 0–3 – 0b – Reserved – Reserved – Type R/W R/W R/W All data is transferred with the MSB first. A device reset to default condition is initiated by a VDD_DIG power-up sequence. "–" means that dedicated bits do not change at RESET. Inactive as long as the REQxPRIO bit is low, external REQx pins are valid (see Figure 26) Writing data beyond 03h may affect device function. Copyright © 2009–2011, Texas Instruments Incorporated 19 CDC3S04 SCAS883B – OCTOBER 2009 – REVISED MAY 2011 www.ti.com REQ1PRIO REQ1POL ‘1’ REQ1 active-high XNOR REQ3POL ‘1’ REQ3 ‘x’ XNOR REQ2 CLK1 enabled signal from externel pin 0 REQ2INT 1 CLK2 enabled if REQ2=’1' disabled if REQ2=’0' internal signals or bits from configuration register REQ3PRIO XNOR REQ3 0 REQ3INT active-high 1 CLK3 enabled if REQ3=’1' disabled if REQ3=’0' REQ4PRIO REQ4POL ‘1’ REQ4 active-high 0 REQ1INT 1 ‘1’ REQ2PRIO REQ2POL ‘1’ REQ2 ‘x’ active-high REQ1 XNOR REQ4 0 REQ4INT 1 ‘1’ CLK4 enabled Figure 26. Clock Output Enable Signal (Shaded Line Marks Power-Up/Default Setting) REQ1PRIO REQ1POL ‘1’ REQ1 active-high XNOR REQ2PRIO REQ2POL ‘1’ REQ2 ‘x’ REQ1 0 REQ1INT 1 ‘1’ XNOR REQ2 REQ2INT active-high REQ3 ‘x’ XNOR REQ3INT active-high REQ4POL ‘1’ REQ4 active-high REQ3 XNOR REQ4PRIO REQ4 internal signals or bits from configuration register AND MREQ2 ‘1’ 0 LDOEN1 AND LDOEN0 ‘0’ 0 1 REQ3PRIO REQ3POL ‘1’ signal from/to externel pin MREQ1 ‘1’ AND 0 0 MREQ CTRL0 1 MREQ4 ‘1’ 0 1 OR MREQ3 ‘1’ ‘1’ ‘1’ 1 LDO is enabled MCLK_REQ MREQCTRL1 AND REQ4INT 1 ‘1’ Figure 27. Decoding Scheme for MCLK_REQ and LDOEN (Shaded Line Marks Power-Up/Default Setting) 20 Copyright © 2009–2011, Texas Instruments Incorporated CDC3S04 SCAS883B – OCTOBER 2009 – REVISED MAY 2011 www.ti.com APPLICATION INFORMATION VDD_DIG VDD_ANA VLDO LDO VBAT REQ1 CLK1 TCXO REQ2 MCLK_IN 38.4MHz Battery Peripheral 1 Peripheral 2 CLK2 MCLK_REQ REQ3 CLK3 RESET 2 REQ4 I C (Hs-mode) GND_DIG CLK4 Peripheral 3 Peripheral 4 GND_ANA Figure 28. Clock Distribution Scheme Copyright © 2009–2011, Texas Instruments Incorporated 21 CDC3S04 SCAS883B – OCTOBER 2009 – REVISED MAY 2011 www.ti.com REVISION HISTORY Changes from Original (October 2009) to Revision A Page • Changed the format on page 1 (moved 2 paragraphs from page 2 to page 1) .................................................................... 1 • Changed the X axis from 0.1us to 100us....900us ............................................................................................................... 9 • Changed Offset 00h Bit 4 Default value from 0h to 1b ....................................................................................................... 19 Changes from Revision A (July 2010) to Revision B • 22 Page Changed Table 3 "Offset" values listed in "Default" and "RESET" columns from "h" to "b". ............................................. 19 Copyright © 2009–2011, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 12-Apr-2011 PACKAGING INFORMATION Orderable Device CDC3S04YFFR Status (1) ACTIVE Package Type Package Drawing DSBGA YFF Pins Package Qty 20 3000 Eco Plan (2) Green (RoHS & no Sb/Br) Lead/ Ball Finish SNAGCU MSL Peak Temp (3) Samples (Requires Login) Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 23-Nov-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device CDC3S04YFFR Package Package Pins Type Drawing SPQ DSBGA 3000 YFF 20 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 180.0 8.4 Pack Materials-Page 1 1.63 B0 (mm) K0 (mm) P1 (mm) 2.08 0.69 4.0 W Pin1 (mm) Quadrant 8.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 23-Nov-2011 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CDC3S04YFFR DSBGA YFF 20 3000 210.0 185.0 35.0 Pack Materials-Page 2 D: Max = 1.99 mm, Min = 1.93 mm E: Max = 1.59 mm, Min = 1.53 mm IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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