DATA SHEET MOS FIELD EFFECT TRANSISTOR 2SK3204 SWITCHING N-CHANNEL POWER MOS FET INDUSTRIAL USE • ORDERING INFORMATION DESCRIPTION The 2SK3204 is N-Channel MOS Field Effect Transistor designed for high current switching applications. • PART NUMBER PACKAGE 2SK3204 MP-10 FEATURES • Low on-state resistance : RDS(on)1 = 34 mΩ (MAX.) (VGS = 10 V, ID = 8 A) RDS(on)2 = 50 mΩ (MAX.) (VGS = 4 V, ID = 8 A) • Low Ciss : Ciss = 940 pF (TYP.) • Built-in gate protection diode. ABSOLUTE MAXIMUM RATINGS (TA = 25 °C) Drain to Source Voltage VDSS 60 V Gate to Source Voltage VGSS(AC) ±20 V Gate to Source Voltage VGSS(DC) +20, −10 V ID(DC) ±15 A ID(pulse) ±45 A Total Power Dissipation (TA = 25 °C) PT 1.8 W Channel Temperature Tch 150 °C Drain Current (DC) Drain Current (pulse) Note1 Tstg −55 to +150 °C Single Avalanche Current Note2 IAS 15 A Single Avalanche Energy Note2 EAS 22.5 mJ Storage Temperature • • Notes 1. PW ≤ 10 µs, Duty Cycle ≤ 1 % 2. Starting Tch = 25 °C, RG = 25 Ω, VGS = 20 V→0 V THERMAL RESISTANCE Channel to Ambient Rth(ch-A) 69.4 °C/W The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. D13796EJ1V0DS00 (1st edition) Date Published April 1999 NS CP (K) Printed in Japan The mark • shows major revised points. © 1998, 1999 2SK3204 • ELECTRICAL CHARACTERISTICS (TA = 25 °C) PARAMATERS SYMBOL Drain to Source On-state Resistance Gate to Source Cut-off Voltage MIN. TYP. MAX. UNIT RDS(on)1 VGS = 10 V, ID = 8 A 25 34 mΩ RDS(on)2 VGS = 4 V, ID = 8 A 35 50 mΩ VGS(off) VDS = 10 V, ID = 1 mA 1.0 1.5 2.0 V 8.0 14 Forward Transfer Admittance | yfs | VDS = 10 V, ID = 8 A Drain Leakage Current IDSS VDS = 60 V, VGS = 0 V 10 µA Gate to Source Leakage Current IGSS VGS = ±20 V, VDS = 0 V ±10 µA Input Capacitance Ciss VDS = 10 V, VGS = 0 V, f = 1 MHz S Output Capacitance 940 pF Coss 290 pF Reverse Transfer Capacitance Crss 120 pF Turn-on Delay Time td(on) ID = 8 A, VGS(on) = 10 V, VDD = 30 V, 17 ns RG = 10 Ω 150 ns td(off) 58 ns tf 52 ns 25 nC Rise Time tr Turn-off Delay Time Fall Time Total Gate Charge QG Gate to Source Charge QGS 2.9 nC Gate to Drain Charge QGD 7.5 nC Body Diode Forward Voltage • TEST CONDITIONS ID = 15 A, VDD = 48 V, VGS(on) = 10 V VF(S-D) IF = 15 A, VGS = 0 V 0.92 V Reverse Recovery Time trr IF = 15 A, VGS = 0 V, 45 ns Reverse Recovery Charge Qrr di/dt = 100 A/µs 81 nC TEST CIRCUIT 1 AVALANCHE CAPABILITY D.U.T. RG = 25 Ω PG. VGS = 20 → 0 V • TEST CIRCUIT 2 SWITCHING TIME D.U.T. L 50 Ω VGS RL RG RG = 10 Ω PG. VDD VGS Wave Form 0 VGS(on) 10 % 90 % VDD ID 90 % 90 % BVDSS IAS ID VGS 0 ID VDS ID τ VDD Starting Tch • τ = 1 µs Duty Cycle ≤ 1 % TEST CIRCUIT 3 GATE CHARGE D.U.T. IG = 2 mA PG. 2 50 Ω 0 10 % 10 % Wave Form RL VDD Data sheet D13796EJ1V0DS00 td(on) tr ton td(off) tf toff 2SK3204 PACKAGE DRAWING (Unit : mm) MP-10 4.5±0.2 EQUIVALENT CIRCUIT 8.0±0.2 13.0±0.2 Drain 2.5±0.2 1 1.4±0.2 0.5±0.1 Body Diode Gate 2 3 Gate Protection Diode Source 1.4±0.2 0.5±0.1 0.5±0.1 1.Gate 2.Drain 3.Source Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage may be applied to this device. Data sheet D13796EJ1V0DS00 3 2SK3204 • The information in this document is subject to change without notice. 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