DATA SHEET MOS FIELD EFFECT TRANSISTOR µ PA1856 P-CHANNEL MOS FIELD EFFECT TRANSISTOR FOR SWITCHING PACKAGE DRAWING (Unit : mm) DESCRIPTION The µPA1856 is a switching device which can be driven directly by a 2.5-V power source. The µPA1856 features a low on-state resistance and excellent switching characteristics, and is suitable for applications such as power switch of portable machine and so on. 8 5 1 2, 3 4 5 6, 7 8 :Drain1 :Source1 :Gate1 :Gate2 :Source2 :Drain2 1.2 MAX. 1.0±0.05 0.25 FEATURES 3° +5° –3° • Can be driven by a 2.5-V power source • Low on-state resistance RDS(on)1 = 45 mΩ MAX. (VGS = –4.5 V, ID = –2.5 A) RDS(on)2 = 48 mΩ MAX. (VGS = –4.0 V, ID = –2.5 A) RDS(on)3 = 72 mΩ MAX. (VGS = –2.7 V, ID = –2.5 A) RDS(on)4 = 77 mΩ MAX. (VGS = –2.5 V, ID = –2.5 A) 1 6.4 ±0.2 3.15 ±0.15 3.0 ±0.1 µPA1856GR-9JG Power TSSOP8 0.65 EQUIVALENT CIRCUIT Drain to Source Voltage VDSS –20 V Gate to Source Voltage VGSS ±12 V Drain Current (DC) ID(DC) ±4.5 A ID(pulse) ±18 A PT 2.0 W Channel Temperature Tch 150 °C Storage Temperature Tstg –55 to +150 °C Total Power Dissipation Note2 0.1 0.10 M ABSOLUTE MAXIMUM RATINGS (TA = 25°C) Drain Current (pulse) 1.0 ±0.2 0.8 MAX. 0.27 +0.03 –0.08 Note1 4.4 ±0.1 0.145 ±0.055 PACKAGE 0.6 +0.15 –0.1 4 ORDERING INFORMATION PART NUMBER 0.5 0.1±0.05 Drain1 Gate1 Gate Protection Diode Source1 Drain2 Body Diode Gate2 Body Diode Gate Protection Diode Source2 Notes 1. PW ≤ 10 µs, Duty Cycle ≤ 1 % 2 2. Mounted on ceramic substrate of 5000 mm x 1.1 mm Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage may be applied to this device. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. D13808EJ2V0DS00 (2nd edition) Date Published March 2000 NS CP(K) Printed in Japan The mark • shows major revised points. © 1998, 1999 µ PA1856 ELECTRICAL CHARACTERISTICS (TA = 25 °C) CHARACTERISTICS SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Zero Gate Voltage Drain Current IDSS VDS = –20 V, VGS = 0 V –10 µA Gate Leakage Current IGSS VGS = ±12 V, VDS = 0 V ±10 µA VGS(off) VDS = –10 V, ID = –1 mA –0.5 –1.1 –1.5 V | yfs | VDS = –10 V, ID = –2.5 A 3 8.8 RDS(on)1 VGS = –4.5 V, ID = –2.5 A 37 45 mΩ RDS(on)2 VGS = –4.0 V, ID = –2.5 A 39 48 mΩ RDS(on)3 VGS = –2.7 V, ID = –2.5 A 52 72 mΩ RDS(on)4 VGS = –2.5 V, ID = –2.5 A 57 77 mΩ Gate Cut-off Voltage Forward Transfer Admittance Drain to Source On-state Resistance S Input Capacitance Ciss VDS = –10 V 700 pF Output Capacitance Coss VGS = 0 V 208 pF Reverse Transfer Capacitance Crss f = 1 MHz 100 pF Turn-on Delay Time td(on) VDD = –10 V 300 ns tr ID = –2.5 A 528 ns VGS(on) = –4.0 V 242 ns RG = 10 Ω 698 ns Rise Time Turn-off Delay Time td(off) Fall Time tf Total Gate Charge QG VDS = –16 V 6.0 nC Gate to Source Charge QGS ID = –4.5 A 2.1 nC Gate to Drain Charge QGD VGS = –4.0 V 2.8 nC Diode Forward Voltage VF(S-D) IF = 4.5 A, VGS = 0 V 0.86 V • Reverse Recovery Time trr IF = 4.5 A, VGS = 0 V 32 ns • Reverse Recovery Charge Qrr di/dt = 10 A / µs 2.2 nC TEST CIRCUIT 1 SWITCHING TIME TEST CIRCUIT 2 GATE CHARGE D.U.T. D.U.T. RL RG PG. VGS (−) VGS Wave Form 0 10 % PG. 90 % 90 % ID VGS (−) 0 ID 10 % 0 10 % Wave Form τ τ = 1 µs Duty Cycle ≤ 1 % tr td(off) td(on) ton RL 50 Ω VDD 90 % VDD ID (−) 2 VGS(on) IG = −2 mA tf toff Data Sheet D13808EJ2V0DS00 µ PA1856 TYPICAL CHARACTERISTICS (TA = 25°C) • DERATING FACTOR OF FORWARD BIAS SAFE OPERATING AREA FORWARD BIAS SAFE OPERATING AREA −100 80 ID - Drain Current - A dT - Derating Factor - % 100 60 40 20 30 60 90 120 TA - Ambient Temperature - ˚C • V (@ PW PW =1 =1 0 ms ms =1 00 ms DC −0.1 TA = 25 ˚C −4.5 V −4.0 V −16 −12 −10 −1 VDS - Drain to Source Voltage - V −100 TRANSFER CHARACTERISTICS −100 −2.5 V −8 −4 VDS = −10 V −10 ID - Drain Current - A VGS = −10 V −1 −0.1 −0.01 TA = 125˚C 75˚C 25˚C −25˚C −0.001 −0.0001 0 0.0 −0.2 −0.6 −0.4 −0.8 −1.0 −0.00001 0 −0.5 GATE TO SOURCE CUT-OFF VOLTAGE vs. CHANNEL TEMPERATURE | yfs | - Forward Transfer Admittance - S 100 −1.0 0 50 100 −1.5 −2.0 −2.5 −3.0 FORWARD TRANSFER ADMITTANCE Vs. DRAIN CURRENT −1.5 VDS = −10 V ID = −1 mA −0.5 −50 −1.0 VGS - Gate to Sorce Voltage - V VDS - Drain to Source Voltage - V VGS(off) - Gate to Source Cut-off Voltage - V PW ID (DC) −1 −0.01 −0.1 150 DRAIN CURRENT vs. DRAIN TO SOURCE VOLTAGE −20 ID - Drain Current - A −10 Single Pulse Mounted on Ceramic Substrate of 5000 mm2x 1.1 mm PD(FET1) : PD(FET2) = 1:1 0 • ID (pulse) d ite V) im .5 )L 4 on = − S( RD GS 150 VDS = −10V 10 TA = −25˚C 25˚C 75˚C 125˚C 1 0.1 0.01 −0.01 Tch - Channel Temperature - ˚C −0.1 −1 −10 −100 ID - Drain Current - A Data Sheet D13808EJ2V0DS00 3 DRAIN TO SOURCE ON-STATE RESISTANCE vs. DRAIN CURRENT 100 VGS = −2.5 V 80 TA = 125˚C 75˚C 60 25˚C −25˚C 40 −0.01 −0.1 −1 −10 −100 RDS(on) - Drain to Source On-State Resistance - mΩ RDS(on) - Drain to Source On-State Resistance - mΩ µ PA1856 DRAIN TO SOURCE ON-STATE RESISTANCE vs. DRAIN CURRENT 100 VGS = −2.7 V 80 TA = 125˚C 75˚C 60 25˚C −25˚C 40 −0.01 60 TA = 125˚C 50 TA = 75˚C TA = 25˚C TA = −25˚C 30 −0.01 −0.1 −1 −10 −100 RDS(on) - Drain to Source On-State Resistance - mΩ RDS(on) - Drain to Source On-State Resistance - mΩ VGS = −4.0 V 40 60 VGS = −4.5 V TA = 125˚C 50 75˚C 40 25˚C −25˚C 30 20 −0.01 VGS = −2.5 V −2.7 V −4.0 V −4.5 V 40 20 −50 0 Tch 4 50 100 - Channel Temperature -˚C RDS (on) - Drain to Source On-state Resistance - mΩ RDS (on) - Drain to Source On-state Resistance - mΩ ID = −2.5 A 60 −1 −0.1 −10 −100 ID - Drain Current - A DRAIN TO SOURCE ON STATE RESISTANCE vs. CHANNEL TEMPERATURE 80 −100 DRAIN TO SOURCE ON-STATE RESISTANCE vs. DRAIN CURRENT ID - Drain Current - A 100 −10 ID - Drain Current - A DRAIN TO SOURCE ON-STATE RESISTANCE vs. DRAIN CURRENT 70 −1 −0.1 ID - Drain Current - A DRAIN TO SOURCE ON-STATE RESISTANCE vs. GATE TO SOURCE VOLTAGE 120 ID = −2.5 A 100 80 60 40 20 0 150 Data Sheet D13808EJ2V0DS00 −2 −4 −6 −8 −10 VGS - Gate to Source Voltage - V −12 µ PA1856 SWITCHING CHARACTERISTICS CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE f = 1 MHz VGS = 0V td(on), tr, td(off), tf - Switchig Time - ns Ciss, Coss, Crss - Capacitance - pF 10000 10000 1000 Ciss Coss Crss 100 10 −0.1 −1 −10 1000 tf tr td(on) td(off) 100 VDD = −10 V VGS(on) = −4.0 V RG = 10 Ω 10 −0.1 −100 −1 ID - Drain Current - A VDS - Drain to Source Voltage - V SOURCE TO DRAIN DIODE FORWARD VOLTAGE DYNAMIC INPUT CHARACTERISTICS −8 VGS - Gate to Source Voltage - V IF - Source to Drain Current - A 100 10 1 0.1 0.6 0.8 1.0 1.2 ID = −4.5 A −6 VDD = −16 V −10 V −4 −2 0 0.01 0.4 0 1 2 3 4 5 6 7 8 9 10 QG - Gate Charge - nC VF(S-D) - Source to Drain Voltage - V • −10 TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH rth(t) - Transient Thermal Resistance - ˚C/W 1000 100 62.5˚C/W 10 1 0.1 1m Mounted on ceramic substrate of 5000 mm2 x 1.1 mm Single Pulse PD(FET1) : PD(FET2) = 1:1 10m 100m 1 10 100 1000 PW - Pulse Width - S Data Sheet D13808EJ2V0DS00 5 µ PA1856 [MEMO] 6 Data Sheet D13808EJ2V0DS00 µ PA1856 [MEMO] Data Sheet D13808EJ2V0DS00 7 µ PA1856 • The information in this document is subject to change without notice. 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