TLC5928 www.ti.com ................................................................................................................................................. SBVS120A – JULY 2008 – REVISED SEPTEMBER 2008 16-Channel, Constant-Current LED Driver with LED Open Detection FEATURES APPLICATIONS • 16 Channels, Constant Current Sink Output with On/Off Control • 35-mA Capability (Constant Current Sink) • 10-ns High-Speed Constant Current Switching Transient Time • Low On-Time Error • LED Power-Supply Voltage up to 17 V • VCC = 3.0 V to 5.5 V • Constant Current Accuracy: – Channel-to-Channel = ±1% – Device-to-Device = ±1% • CMOS Logic Level I/O • 35-MHz Data Transfer Rate • 20-ns BLANK Pulse Width • Readable Error Information: – LED Open Detection (LOD) – Pre-Thermal Warning (PTW) • Operating Temperature: –40°C to +85°C • • • 1 23 VLED Controller The TLC5928 is a 16-channel, constant current sink LED driver. Each channel can be turned on/off by writing serial data to an internal register. The constant current value of all 16 channels is set by a single external resistor. The TLC5928 has two error detection circuits: one for LED open detection (LOD) and one for a pre-thermal warning (PTW). LOD detects a broken or disconnected LED and LEDs shorted to GND while the constant current output is on. PTW indicates a high temperature condition. ¼ ¼ ¼ ¼ ¼ OUT0 OUT15 VCC IREF OUT15 SOUT VCC SCLK LAT VCC VCC BLANK BLANK ERROR READ ¼ SIN SOUT LAT BLANK VLED ¼ SCLK LAT VLED ¼ SIN SCLK DESCRIPTION VLED OUT0 DATA LED Video Displays Message Boards Illumination TLC5928 IC1 RIREF IREF GND TLC5928 ICn GND RIREF 3 Typical Application Circuit (Multiple Daisy-Chained TLC5928s) 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments, Inc. All other trademarks are the property of their respective owners. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008, Texas Instruments Incorporated TLC5928 SBVS120A – JULY 2008 – REVISED SEPTEMBER 2008 ................................................................................................................................................. www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION (1) PRODUCT PACKAGE-LEAD TLC5928 SO-24 TLC5928 TSSOP-24 TLC5928 (2) TRANSPORT MEDIA, QUANTITY TLC5928DBQR Tape and Reel, 2500 TLC5928DBQ Tube, 50 TLC5928PWR Tape and Reel, 2000 HTSSOP-24 PowerPAD™ QFN-24 (2) TLC5928 (1) ORDERING NUMBER TLC5928PW Tube, 60 TLC5928PWPR Tape and Reel, 2000 TLC5928PWP Tube, 60 TLC5928RGER Tape and Reel, 3000 TLC5928RGE Tape and Reel, 250 For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Shaded cells indicate product preview device. ABSOLUTE MAXIMUM RATINGS (1) (2) Over operating free-air temperature range, unless otherwise noted. PARAMETER TLC5928 VCC Supply voltage: VCC IOUT Output current (dc) OUT0 to OUT15 VIN Input voltage range VOUT Output voltage range TJ(MAX) Operating junction temperature TSTG Storage temperature range (1) (2) V 40 mA SIN, SCLK, LAT, BLANK, IREF –0.3 to VCC + 0.3 V SOUT –0.3 to VCC + 0.3 V –0.3 to +18 V +150 °C OUT0 to OUT15 Human body model (HBM) ESD rating UNIT –0.3 to +6.0 Charged device model (CDM) –55 to +150 °C 2 kV 500 V Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported. All voltage values are with respect to network ground terminal. DISSIPATION RATINGS (1) (2) 2 PACKAGE OPERATING FACTOR ABOVE TA = +25°C TA < +25°C POWER RATING TA = +70°C POWER RATING TA = +85°C POWER RATING 927 mW SO-24 14.3 mW/°C 1782 mW 1140 mW TSSOP-24 9.6 mW/°C 1194 mW 764 mW 621 mW HTSSOP-24 (1) 28.9 mW/°C 3611 mW 2311 mW 1878 mW QFN-24 (2) 24.8 mW/°C 3106 mW 1988 mW 1615 mW With PowerPAD soldered onto copper area on printed circuit board (PCB); 2 oz. copper. For more information, see SLMA002 (available for download at www.ti.com). The package thermal impedance is calculated in accordance with JESD51-5. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TLC5928 TLC5928 www.ti.com ................................................................................................................................................. SBVS120A – JULY 2008 – REVISED SEPTEMBER 2008 RECOMMENDED OPERATING CONDITIONS At TA= –40°C to +85°C, unless otherwise noted. TLC5928 PARAMETER TEST CONDITIONS MIN NOM MAX UNIT DC Characteristics: VCC = 3 V to 5.5 V VCC Supply voltage VO Voltage applied to output 3.0 5.5 V 17 VIH High-level input voltage V 0.7 × VCC VCC V VIL Low-level input voltage IOH High-level output current SOUT GND 0.3 × VCC –1 mA IOL Low-level output current SOUT 1 mA IOLC Constant output sink current 2 35 mA TA Operating free-air temperature range –40 +85 °C TJ Operating junction temperature range –40 +125 °C OUT0 to OUT15 OUT0 to OUT15 V AC Characteristics: VCC = 3 V to 5.5 V fCLK (SCLK) Data shift clock frequency SCLK 35 MHz TWH0 SCLK 10 ns TWL0 SCLK 10 ns TWH1 LAT 20 ns TWH2 BLANK 20 ns TWL2 BLANK 20 ns TSU0 TSU1 TH0 TH1 Pulse duration Setup time Hold time SIN–SCLK↑ 4 ns 100 ns SIN–SCLK↑ 3 ns LAT↑–SCLK↑ 10 ns LAT↑–SCLK↑ Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TLC5928 3 TLC5928 SBVS120A – JULY 2008 – REVISED SEPTEMBER 2008 ................................................................................................................................................. www.ti.com ELECTRICAL CHARACTERISTICS At VCC = 3.0 V to 5.5 V and TA = –40°C to +85°C. Typical values at VCC = 3.3 V and TA = +25°C, unless otherwise noted. TLC5928 PARAMETER TEST CONDITIONS VOH High-level output voltage IOH = –1 mA at SOUT VOL Low-level output voltage IOL = 1 mA at SOUT IIN Input current VIN = VCC or GND at SIN, SCLK, LAT, and BLANK ICC1 ICC2 Supply current (VCC) MIN MAX UNIT VCC – 0.4 TYP VCC V 0 0.4 V –1 1 µA SIN/SCLK/LAT = low, BLANK = high, VOUTn = 1 V, RIREF = 27 kΩ 1 2 mA SIN/SCLK/LAT = low, BLANK = high, VOUTn = 1 V, RIREF = 3 kΩ 4.5 8 mA ICC3 SIN/SCLK/LAT/BLANK = low, VOUTn = 1 V, RIREF = 3 kΩ 7 18 mA ICC4 SIN/SCLK/LAT/BLANK = low, VOUTn = 1 V, RIREF = 1.5 kΩ 16 40 mA 34 37 mA 0.1 µA IOLC Constant output current All OUTn = ON, VOUTn = VOUTfix = 1 V, RIREF = 1.5 kΩ (see Figure 6), at OUT0 to OUT15 IOLKG Output leakage current All OUTn for constant current driver, all outputs off BLANK = high, VOUTn = VOUTfix = 17 V, RIREF = 1.5 kΩ (see Figure 6), at OUT0 to OUT15 ΔIOLC Constant current error (channel-to-channel) (1) All OUTn = ON, VOUTn = VOUTfix = 1 V, RIREF = 1.5 kΩ at OUT0 to OUT15 ±1 ±3 % ΔIOLC1 Constant current error (device-to-device) (2) All OUTn = ON, VOUTn = VOUTfix = 1 V, RIREF = 1.5 kΩ at OUT0 to OUT15 ±1 ±6 % ΔIOLC2 Line regulation (3) All OUTn = ON, VOUTn = VOUTfix = 1 V, RIREF = 1.5 kΩ at OUT0 to OUT15 ±0.5 ±1 %/V ΔIOLC3 Load regulation (4) All OUTn = ON, VOUTn = 1 V to 3V, VOUTfix = 1 V, RIREF = 1.5 kΩ, at OUT0 to OUT15 ±1 ±3 %/V T(PTW) Pre-thermal warning threshold Junction temperature (5) +125 +138 +150 °C VLOD LED open detection threshold All OUTn = ON 0.25 0.30 0.35 V VIREF Reference voltage output RIREF = 1.5 kΩ 1.16 1.20 1.24 V (1) The deviation of each output from the average of OUT0–OUT15 constant current. Deviation is calculated by the formula: D (%) = (2) 31 IOUTn -1 (IOUT0 + IOUT1 + ... + IOUT14 + IOUT15) ´ 100 16 . The deviation of the OUT0–OUT15 constant current average from the ideal constant current value. Deviation is calculated by the following formula: (IOUT0 + IOUT1 + ... IOUT14 + IOUT15) 16 D (%) = - (Ideal Output Current) ´ 100 Ideal Output Current Ideal current is calculated by the formula: IOUT(IDEAL) = 42 ´ (3) Line regulation is calculated by this equation: D (%/V) = (4) 4 (IOUTn at VCC = 5.5 V) - (IOUTn at VCC = 3.0 V) (IOUTn at VCC = 3.0 V) ´ 100 5.5 V - 3 V Load regulation is calculated by the equation: D (%/V) = (5) 1.20 RIREF (IOUTn at VOUTn = 3 V) - (IOUTn at VOUTn = 1 V) (IOUTn at VOUTn = 1 V) ´ 100 3V-1V Not tested. Specified by design. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TLC5928 TLC5928 www.ti.com ................................................................................................................................................. SBVS120A – JULY 2008 – REVISED SEPTEMBER 2008 SWITCHING CHARACTERISTICS At VCC = 3.0 V to 5.5 V, TA = –40°C to +85°C, CL = 15 pF, RL = 130 Ω, RIREF = 1.5 kΩ, and VLED = 5.5 V. Typical values at VCC = 3.3 V and TA = +25°C, unless otherwise noted. TLC5928 PARAMETER tR0 TEST CONDITIONS Rise time tR1 tF0 Fall time tF1 tD0 TYP MAX SOUT (see Figure 5) 5 15 ns OUTn (see Figure 4) 10 30 ns SOUT (see Figure 5) 5 15 ns OUTn (see Figure 4) 10 30 ns 8 20 ns LAT↑ or BLANK↓ to OUTn sink current on (see Figure 10) 12 30 ns LAT↑ or BLANK↑ to OUTn sink current off (see Figure 10) 12 30 ns +8 ns SCLK↑ to SOUT tD1 Propagation delay time tD2 tON_ERR (1) MIN Output on-time error (1) On/off latch data = all '1', 20 ns BLANK low level one-shot pulse input (see Figure 4) –8 UNIT Output on-time error (tON_ERR) is calculated by the formula: tON_ERR (ns) = tOUT_ON – BLANK low level one-shot pulse width (TWL2). tOUT_ON indicates the actual on-time of the constant current driver. FUNCTIONAL BLOCK DIAGRAM VCC VCC SIN LSB MSB On/Off Control Shift Register (1 Bit x 16 Channels) SCLK 0 SOUT 15 16 MSB LSB LAT 16 On/Off Control Data Latch (1 Bit x 16 Channels) 0 BLANK 15 16 SID Latch IREF 16-Channel Constant Current Sink Driver 16 Thermal Detection GND 16-Channel LED Open Detection GND ¼ OUT0 OUT1 OUT14 OUT15 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TLC5928 5 TLC5928 SBVS120A – JULY 2008 – REVISED SEPTEMBER 2008 ................................................................................................................................................. www.ti.com DEVICE INFORMATION SO-24 AND TSSOP-24 DBQ AND PW PACKAGES (TOP VIEW) HTSSOP-24 PowerPAD PWP PACKAGE (TOP VIEW) GND 1 24 VCC GND 1 24 VCC SIN 2 23 IREF SIN 2 23 IREF SCLK 3 22 SOUT SCLK 3 22 SOUT LAT 4 21 BLANK LAT 4 21 BLANK OUT0 5 20 OUT15 OUT0 5 20 OUT15 OUT1 6 19 OUT14 OUT1 6 19 OUT14 18 OUT13 Thermal Pad (Bottom Side) TLC5928 TLC5928 OUT2 7 18 OUT13 OUT2 7 OUT3 8 17 OUT12 OUT3 8 17 OUT12 OUT4 9 16 OUT11 OUT4 9 16 OUT11 OUT5 10 15 OUT10 OUT5 10 15 OUT10 OUT6 11 14 OUT9 OUT6 11 14 OUT9 OUT7 12 13 OUT8 OUT7 12 13 OUT8 SCLK SIN GND VCC IREF SOUT 24 23 22 21 20 19 QFN-24(1) RGE PACKAGE (TOP VIEW) LAT 1 18 BLANK OUT0 2 17 OUT15 OUT1 3 16 OUT14 OUT2 4 15 OUT13 OUT3 5 14 OUT12 OUT4 6 13 OUT11 7 8 9 10 11 12 OUT5 OUT6 OUT7 OUT8 OUT9 OUT10 Thermal Pad (Bottom Side) TLC5928 NOTE: Thermal pad is not connected to GND internally. The thermal pad must be connected to GND via the PCB pattern. (1) Product preview device. 6 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TLC5928 TLC5928 www.ti.com ................................................................................................................................................. SBVS120A – JULY 2008 – REVISED SEPTEMBER 2008 TERMINAL FUNCTIONS TERMINAL NAME DBQ/PW/ PWP RGE I/O DESCRIPTION SIN 2 23 I Serial data input for driver on/off control. When SIN = high level, data '1' are written into LSB of the on/off control shift register at the rising edge of SCLK. SCLK 3 24 I Serial data shift clock. Schmitt buffer input. All data in the on/off control shift register are shifted toward the MSB by 1-bit synchronization of SCLK. A rising edge on SCLK is allowed 100 ns after a rising edge of LAT. LAT 4 1 I Edge triggered latch. The data in the on/off control data shift register are transferred to the on/off control data latch at this rising edge. At the same time, the data in the on/off control shift register are replaced with LED open detection (LOD) and pre-thermal warning (PTW) data. LAT must be toggled only once after the shift data are updated to avoid the on/off control latch data being replaced with LOD and PTW data in the shift register. BLANK 21 18 I Blank, all outputs. When BLANK = high level, all constant current outputs (OUT0–OUT15) are forced off. When BLANK = low level, all constant current outputs are controlled by the on/off control data in the data latch. LOD and PTW data are latched into the SID data latch at the rising edge of BLANK and are present at the output of the SID data latch when BLANK is low. IREF 23 20 I/O Constant current value setting, OUT0–OUT15 sink constant current is set to desired value by connection to an external resistor between IREF and GND. SOUT 22 19 O Serial data output. This output is connected to the MSB of the on/off data shift register. SOUT data changes at the rising edge of SCLK. OUT0 5 2 O Constant current output. Each output can be tied together with others to increase the constant current. Different voltages can be applied to each output. OUT1 6 3 O Constant current output OUT2 7 4 O Constant current output OUT3 8 5 O Constant current output OUT4 9 6 O Constant current output OUT5 10 7 O Constant current output OUT6 11 8 O Constant current output OUT7 12 9 O Constant current output OUT8 13 10 O Constant current output OUT9 14 11 O Constant current output OUT10 15 12 O Constant current output OUT11 16 13 O Constant current output OUT12 17 14 O Constant current output OUT13 18 15 O Constant current output OUT14 19 16 O Constant current output OUT15 20 17 O Constant current output VCC 24 21 — Power-supply voltage GND 1 22 — Power ground Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TLC5928 7 TLC5928 SBVS120A – JULY 2008 – REVISED SEPTEMBER 2008 ................................................................................................................................................. www.ti.com PARAMETER MEASUREMENT INFORMATION PIN EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS VCC VCC INPUT SOUT GND GND Figure 1. SIN, SCLK, LAT, BLANK Figure 2. SOUT OUTn GND Figure 3. OUT0 Through OUT15 TEST CIRCUITS RL VCC VCC OUTn IREF RIREF VCC (1) VLED SOUT VCC CL GND GND (1) CL includes measurement probe and jig capacitance. Figure 4. Rise Time and Fall Time Test Circuit for OUTn VCC (1) CL includes measurement probe and jig capacitance. Figure 5. Rise Time and Fall Time Test Circuit for SOUT OUT0 ¼ VCC (1) CL IREF ¼ RIREF OUTn GND OUT15 VOUTn VOUTFIX Figure 6. Constant Current Test Circuit for OUTn 8 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TLC5928 TLC5928 www.ti.com ................................................................................................................................................. SBVS120A – JULY 2008 – REVISED SEPTEMBER 2008 TIMING DIAGRAMS TWH0, TWL0, TWH1, TWH2, TWL2: VCC INPUT (1) 50% GND TWH TWL TSU0, TSU1, TH0, TH1: VCC CLOCK INPUT (1) 50% GND TSU TH VCC DATA/CONTROL INPUT (1) 50% GND (1) Input pulse rise and fall time is 1 ns to 3 ns. Figure 7. Input Timing tR0, tR1, tF0, tF1, tD0, tD1, tD2: VCC (1) INPUT 50% GND tD VOH or VOUTn 90% OUTPUT 50% 10% VOL or VOUTn tR or tF (1) Input pulse rise and fall time is 1 ns to 3 ns. Figure 8. Output Timing Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TLC5928 9 TLC5928 SBVS120A – JULY 2008 – REVISED SEPTEMBER 2008 ................................................................................................................................................. www.ti.com SIN DATA 0A DATA 15B DATA 13B DATA 14B DATA 12B DATA 11B DATA 3B DATA 2B DATA 0B DATA 1B TH0 TSU0 TH1 TWH0 DATA 15C DATA 14C DATA 13C DATA 12C DATA 11C DATA 10C 1 2 3 TWL0 4 5 6 TSU1 SCLK 1 2 3 4 5 13 14 15 16 TWH1 LAT Shift Register LSB Data (Internal) DATA 0A LOD 0 DATA 15B DATA 14B DATA 13B DATA 12B DATA 3B DATA 2B DATA 1B Shift Register LSB+1 Data (Internal) DATA 1A LOD 1 LOD 0 DATA 15B DATA 14B DATA 13B DATA 4B DATA 3B Shift Register MSB-1 Data (Internal) DATA 14A LOD 14 LOD 13 LOD 12 LOD 11 LOD 10 LOD 1 Shift Register MSB Data (Internal) DATA 15A LOD 15 LOD 14 LOD 13 LOD 12 LOD 11 LOD 2 DATA 15C DATA 14C DATA 13C DATA 12C DATA 11C DATA 2B LOD 1A or PTW_A LOD 0A DATA 15C DATA 14C DATA 13C DATA 12C LOD 0 DATA 15B LOD 14A or PTW_A LOD 13A LOD 12A LOD 11A LOD 10A LOD 9A LOD 1 LOD 0 LOD 15A or PTW_A LOD 14A LOD 13A LOD 12A LOD 11A LOD 10A ¼ LOD 0A or PTW_A ¼ ¼ On/Off Control Latch Data (Internal) SOUT DATA 0B DATA 15B Previous Grayscale Latch Data DATA 15A LOD 15 LOD 14 LOD 13 tD0 LOD 12 LOD 11 LOD 2 LOD 1 LOD 0 DATA 15B Latest Grayscale Latch Data LOD 14A LOD 15A or PTW_A tR0/tF0 LOD 13A LOD 12A LOD 11A LOD 10A tWH2 BLANK tWL2 tD2 tD1 OFF OUTn OUTn (1) (2) ON OFF tD2 tF1 tD1 OFF (3) ON ON OFF OFF OUTn (4) tOUTON OFF ON ON OFF OUTn tD1 OFF ON ON tR1 ON (1) On/off latched data are '1'. (2) On/off latched data are changed from '1' to '0' at the second LAT signal. (3) On/off latched data are changed from '0' to '1' at the second LAT signal. (4) On/off latched data are '0'. Figure 9. Timing Diagram 10 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TLC5928 TLC5928 www.ti.com ................................................................................................................................................. SBVS120A – JULY 2008 – REVISED SEPTEMBER 2008 TYPICAL CHARACTERISTICS At VCC = 3.3 V and TA = +25°C, unless otherwise noted. REFERENCE RESISTOR vs OUTPUT CURRENT POWER DISSIPATION RATE vs FREE-AIR TEMPERATURE 4000 100000 Power Dissipation Rate (mW) Reference Resistor (W) TLC5928PWP 25200 10080 10000 5040 3360 2520 2016 1680 3000 TLC5928RGE 2000 TLC5928DBQ 1000 1440 0 1000 0 15 10 5 20 25 TLC5928PW 30 -40 40 Figure 10. Figure 11. OUTPUT CURRENT vs OUTPUT VOLTAGE OUTPUT CURRENT vs OUTPUT VOLTAGE 40 IO = 35 mA TA = +25°C Output Current (mA) Output Current (mA) 25 IO = 20 mA 15 IO = 10 mA 10 IO = 2 mA IO = 5 mA 5 100 38 30 20 80 IO = 30 mA 39 IO = 30 mA 0 37 36 35 34 33 TA = -40°C 32 TA = +25°C 31 TA = +85°C 30 0 1.5 1.0 0.5 2.0 2.5 0 3.0 1.0 0.5 1.5 2.0 Output Voltage (V) Output Voltage (V) Figure 12. Figure 13. ΔIOLC vs AMBIENT TEMPERATURE 2.5 3.0 ΔIOLC vs OUTPUT CURRENT 4 4 IO = 35 mA TA = +25°C 3 3 2 2 1 1 DIOLC (%) DIOLC (%) 60 40 Free-Air Temperature (°C) 35 0 -1 -2 0 -1 -2 VCC = 3.3 V -3 -4 20 0 -20 Output Current (mA) -40 -20 0 20 40 60 80 VCC = 3.3 V -3 VCC = 5 V 100 -4 VCC = 5 V 0 10 20 Ambient Temperature (°C) Output Current (mA) Figure 14. Figure 15. 30 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TLC5928 40 11 TLC5928 SBVS120A – JULY 2008 – REVISED SEPTEMBER 2008 ................................................................................................................................................. www.ti.com TYPICAL CHARACTERISTICS (continued) At VCC = 3.3 V and TA = +25°C, unless otherwise noted. CONSTANT CURRENT OUTPUT VOLTAGE WAVEFORM CH1 (2 V/div) CH1-BLANK (20 ns) CH2 (2 V/div) CH2-OUT0 (BLANK = 20 ns) CH3 (2 V/div) CH3-OUT15 (BLANK = 20 ns) IOLC = 35 mA TA = +25°C RL = 130 W CL = 15 pF VLED = 5.5 V Time (12.5 ns/div) Figure 16. 12 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TLC5928 TLC5928 www.ti.com ................................................................................................................................................. SBVS120A – JULY 2008 – REVISED SEPTEMBER 2008 DETAILED DESCRIPTION SETTING FOR THE CONSTANT SINK CURRENT VALUE The constant current values are determined by an external resistor (RIREF) placed between IREF and GND. The resistor (RIREF) value is calculated by Equation 1. RIREF (kW) = VIREF (V) ´ 42 IOLC (mA) (1) Where: VIREF = the internal reference voltage on the IREF pin (typically 1.20 V) IOLC must be set in the range of 2 mA to 35 mA. The constant sink current characteristic for the external resistor value is shown in Figure 10. Table 1 describes the constant current output versus external resistor value. Table 1. Constant Current Output versus External Resistor Value IOLCMax (mA, Typical) RIREF (kΩ) 35 1.44 30 1.68 25 2.02 20 2.52 15 3.36 10 5.04 5 10.1 2 25.2 CONSTANT CURRENT DRIVER ON/OFF CONTROL When BLANK is low, the corresponding output is turned on if the data in the on/off control data latch are '1' and remains off if the data are '0'. When BLANK is high, all outputs are forced off. This control is shown in Table 2. Table 2. On/Off Control Data Truth Table ON/OFF CONTROL LATCH DATA CONSTANT CURRENT OUTPUT STATUS 0 Off 1 On When the IC is initially powered on, the data in the on/off control shift register and data latch are not set to the respective default value. Therefore, the on/off control data must be written to the data latch before turning the constant current output on. BLANK should be at a high level when powered on because the constant current may be turned on as a result of random data in the on/off control latch. The on/off data corresponding to any unconnected OUTn outputs should be set to ‘0’ before turning on the remaining outputs. Otherwise, the supply current (ICC) increases while the LEDs are on. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TLC5928 13 TLC5928 SBVS120A – JULY 2008 – REVISED SEPTEMBER 2008 ................................................................................................................................................. www.ti.com REGISTER CONFIGURATION The TLC5928 has an on/off control data shift register and data latch. Both the on/off control shift register and latch are 16 bits long and are used to turn on/off the constant current drivers. Figure 17 shows the shift register and latch configuration. The data at the SIN pin are shifted in to the LSB of the shift register at the rising edge of the SCLK pin; SOUT data change at the rising edge of SCLK. The timing diagram for data writing is shown in Figure 18. The driver on/off is controlled by the data in the on/off control data latch. The on/off data are latched into the data latch by a rising edge of LAT after the data are written into the on/off control shift register by SIN and SCLK. At the same time, the data in the on/off control shift register are replaced with LED open detection (LOD) and pre-thermal warning (PTW) data. Therefore, LAT must be input only once after the on/off data update to avoid the on/off control data latch being replaced with LOD and PTW data in the shift register. When the IC is initially powered on, the data in the on/off control shift register and latch are not set to the default values; on/off control data must be written to the on/off control data latch before turning the constant current output on. BLANK should be high when the IC is powered on because the constant current may be turned on at that time as a result of random values in the on/off data latch. All constant current outputs are forced off when BLANK is high. On/Off Control Shift Register (1 Bit ´ 16 Channels) SOUT MSB 15 14 13 12 On/Off Data for OUT15 On/Off Data for OUT14 On/Off Data for OUT13 On/Off Data for OUT12 4 11 ¼ 3 2 1 LSB 0 On/Off Data for OUT3 On/Off Data for OUT2 On/Off Data for OUT1 On/Off Data for OUT0 3 2 1 LSB 0 On/Off Data for OUT3 On/Off Data for OUT2 On/Off Data for OUT1 On/Off Data for OUT0 SIN SCLK ¼ MSB 15 14 13 12 On/Off Data for OUT15 On/Off Data for OUT14 On/Off Data for OUT13 On/Off Data for OUT12 On/Off Control Data Latch (1 Bit ´ 16 Channels) 4 11 ¼ LAT 16 Bits To Constant Current Driver Control Block Figure 17. On/Off Control Shift Register and Latch Configuration 14 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TLC5928 TLC5928 www.ti.com ................................................................................................................................................. SBVS120A – JULY 2008 – REVISED SEPTEMBER 2008 SIN DATA 0A DATA 15B DATA 14B DATA 13B DATA 12B DATA 11B 1 2 3 4 5 DATA 3B DATA 2B DATA 1B DATA 0B DATA 15C DATA 14C DATA 13C DATA 12C DATA 11C DATA 10C 16 1 2 3 4 5 6 SCLK 13 14 15 LAT DATA 0A LOD 0 DATA 15B DATA 14B DATA 13B DATA 12B DATA 3B DATA 2B DATA 1B Shift Register LSB+1 Data (Internal) DATA 1A LOD 1 LOD 0 DATA 15B DATA 14B DATA 13B DATA 4B DATA 3B Shift Register MSB-1 Data(Internal) DATA 14A LOD 14 LOD 13 LOD 12 LOD 11 LOD 10 LOD 1 Shift Register MSB Data(Internal) DATA 1A LOD 15 LOD 14 LOD 13 LOD 12 LOD 11 LOD 2 On/Off Control Latch Data (Internal) SOUT LOD 0A or PTW_A DATA 15C DATA 14C DATA 13C DATA 12C DATA 11C DATA 2B LOD 1A or PTW_A LOD 0A DATA 15C DATA 14C DATA 13C DATA 12C LOD 0 DATA 15B LOD 14A or PTW_A LOD 13A LOD 12A LOD 11A LOD 10A LOD 9A LOD 1 LOD 0 LOD 15A or PTW_A LOD 14A LOD 13A LOD 12A LOD 11A LOD 10A DATA 0B ¼ ¼ ¼ Shift Register LSB Data (Internal) DATA 15B Previous Grayscale Latch Data DATA 1A LOD 15 LOD 14 LOD 13 LOD 12 LOD 11 LOD 2 LOD 1 LOD 0 DATA 15B Latest Grayscale Latch Data LOD 15A or PTW_A LOD 14A LOD 13A LOD 12A LOD 11A LOD 10A BLANK OUTn (1) ON OUTn (2) (3) ON OFF OFF ON OUTn OFF OFF OFF ON OFF OUTn (4) OFF OFF ON ON OFF OFF ON (1) On/off latched data are '1'. (2) On/off latched data are changed from '1' to '0' at the second LAT signal. (3) On/off latched data are changed from '0' to '1' at the second LAT signal. (4) On/off latched data are '0'. Figure 18. On/Off Control Operation Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TLC5928 15 TLC5928 SBVS120A – JULY 2008 – REVISED SEPTEMBER 2008 ................................................................................................................................................. www.ti.com LED OPEN DETECTION (LOD) AND PRE-THERMAL WARNING (PTW) The LED open detection (LOD) circuit checks the voltage of each active (that is, on) constant current sink output (OUT0 through OUT15) to detect open LEDs and LEDs shorted to GND while BLANK is low. The LOD bits in the status information data register (SID) are set to '1' if the voltage of the corresponding OUTn pin is less than the LED open detection threshold (VLOD = 0.3 V, typ). The status information data can be read from the SOUT pin. To avoid false detection of open LEDs, the LED driver design must ensure that the constant-current sink output voltage is greater than 0.3 V when the outputs are on. Also, the output on-time must be 1 µs or greater to correctly read the valid LOD status. The PTW function indicates that the IC junction temperature is too high. The PTW bit in the SID data is set to '1' while the IC junction temperature exceeds the temperature threshold (T(PTW) = +138 °C, typ). If the IC junction temperature decreases below the temperature of T(PTW), the SID data are set depending on the LOD function. The constant current outputs are not forced off during PTW conditions, so the controller should take appropriate action (such as reducing the duty cycle of effected channels). The LOD and PTW data are latched into the SID latch with the rising edge of BLANK and do not change until BLANK goes low. The SID data latched in the latch are transferred into the on/off shift register with a rising edge of LAT. SID can be shifted out from SOUT with rising edges of SCLK. The data in the on/off control shift register are replaced with the LOD and PTW data at the rising edge of LAT. Therefore, LAT should be input only once after the shift data are updated to avoid the on/off control data latch information from being replaced with LOD and PTW data in the shift register. A timing diagram for LOD, PTW, and SID is shown in Figure 19. BLANK OUTn OUTn OFF OUTn ON VOUTn GND LOD circuit needs 1ms to detect LED open correctly as maximum. LOD Circuit Data (Internal) PTW Circuit Data (Internal) No Error Information If the voltage of OUTn (VOUTn) is less than VLOD (0.3 V, typ) when OUTn is on, then the LOD circuit reports error information to the LOD data latch and the error information is set as '1' to the bit that corresponds with the error OUTn in the LOD data latch. Latest Error Information From LOD Circuit LOD and PTW data are always copied into SID data latch while BLANK is low level. TJ < T(PTW): Normal Temperature TJ ³ T(PTW): High Temperature No Error Information TJ < T(PTW): Normal Temperature LOD and PTW data of from before BLANK goes high are held in the SID data latch at the rising edge of BLANK. Previous LOD and PTW Data SID Data Latch (Internal) PTW Error Latest Error Information From LOD and PTW Circuit No Error Information Figure 19. LOD/PTW/SID timing 16 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TLC5928 TLC5928 www.ti.com ................................................................................................................................................. SBVS120A – JULY 2008 – REVISED SEPTEMBER 2008 STATUS INFORMATION DATA (SID) The latched LED open detection (LOD) error and pre-thermal warning (PTW) in the SID data latch are shifted out onto the SOUT pin with each rising edge of SCLK. If a PTW is reported, all LOD error bits are set to '1'. The SID data are written over the data in the on/off control shift register at the rising edge of LAT. Therefore, the previous data in the on/off control shift register are lost when SID information is latched in. Figure 20 shows the SID bit assignments. See Figure 7 for the read timing of SID. When the IC is powered on, the initial LOD data are invalid. Therefore, LOD data must be read after the rising edge of BLANK. Table 3 shows a truth table for LOD and PTW. Table 3. LOD and PTW Truth Table CONDITION LED is connected (VOUTn > VLOD) '0' (low level at SOUT) LED is opened or shorted to GND (VOUTn ≤ VLOD and output on) '1' (high level at SOUT); set to the bit that has an LED error condition IC temperature is low (IC temperature ≤ T(PTW)) Depend LED open error IC temperature is high (IC temperature > T(PTW)) All bits = '1' (high level at SOUT) LED open detection (LODn) Pre-termal warning (PTW) SID DATA SID Data Latch (1 Bit ´ 16 Channels) MSB 15 14 13 12 OUT15 LOD Data (LOD 15) OUT15 LOD Data (LOD 14) OUT15 LOD Data (LOD 13) OUT15 LOD Data (LOD 12) 4 11 ¼ 3 2 1 LSB 0 OUT15 LOD Data (LOD 3) OUT15 LOD Data (LOD 2) OUT15 LOD Data (LOD 1) OUT15 LOD Data (LOD 0) All Bits Become ‘1’ When the IC is in a PTW (Pre-Thermal Warning) Condition ¼ SOUT MSB 15 14 13 12 On/Off Data for OUT15 On/Off Data for OUT14 On/Off Data for OUT13 On/Off Data for OUT12 4 11 ¼ 3 2 1 LSB 0 On/Off Data for OUT3 On/Off Data for OUT2 On/Off Data for OUT1 On/Off Data for OUT0 SIN SCLK The 16 bits in the SID latch are loaded into the on/off shift register at the rising edge of LAT. SID Control Shift Register (1 Bit ´ 16 Channels) Figure 20. Status Information Data Configuration Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TLC5928 17 PACKAGE OPTION ADDENDUM www.ti.com 2-Oct-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TLC5928DBQ ACTIVE SSOP/ QSOP DBQ 24 TLC5928DBQR ACTIVE SSOP/ QSOP DBQ 24 TLC5928PW ACTIVE TSSOP PW 24 60 TLC5928PWP ACTIVE HTSSOP PWP 24 60 TLC5928PWPR ACTIVE HTSSOP PWP TLC5928PWR ACTIVE TSSOP PW 50 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 8-Sep-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLC5928DBQR SSOP/ QSOP DBQ 24 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TLC5928PWPR HTSSOP PWP 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 8-Sep-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLC5928DBQR TLC5928PWPR SSOP/QSOP DBQ 24 2500 346.0 346.0 33.0 HTSSOP PWP 24 2000 346.0 346.0 33.0 Pack Materials-Page 2 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. 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