NEC UPA1560

DATA SHEET
COMPOUND FIELD EFFECT POWER TRANSISTOR
µ PA1560
N-CHANNEL POWER MOS FET ARRAY
SWITCHING
INDUSTRIAL USE
DESCRIPTION
PACKAGE DRAWING (Unit : mm)
The µPA1560 is N-Channel Power MOS FET Array
that built in 4 circuits designed for solenoid, motor and
lamp driver.
4.0
2.5
10 MIN.
10
26.8 MAX.
FEATURES
• Full mold package with 4 circuits
• 4 V driving is possible
• Low on-state resistance
RDS(on)1 = 165 mΩ MAX. (VGS = 10 V, ID = 1.5 A)
RDS(on)2 = 200 mΩ MAX. (VGS = 4 V, ID = 1.5 A)
• Low input capacitance
Ciss = 600 pF TYP.
1.4
0.5±0.1
2.54
1.4
0.6±0.1
1 2 3 4 5 6 7 8 910
EQUIVALENT CIRCUIT
3
5
7
9
ORDERING INFORMATION
PART NUMBER
PACKAGE
µ PA1560H
10-pin SIP
2
4
6
8
1
10
ELECTRODE CONNECTION
2, 4, 6, 8 : Gate
3, 5, 7, 9 : Drain
1, 10
: Source
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
Drain to Source Voltage (VGS = 0 V)
VDSS
120
V
Gate to Source Voltage (VDS = 0 V)
VGSS(AC)
±20
V
Gate to Source Voltage (VDS = 0 V)
VGSS(DC)
+ 20, –10
V
ID(DC)
±3.0
A
ID(pulse)
±12
A
Total Power Dissipation (TC = 25°C)
PT1
28
W
Total Power Dissipation (TA = 25°C)
PT2
3.7
W
Channel Temperature
Tch
150
°C
Drain Current (DC)
Drain Current (pulse)
Note1
Storage Temperature
Tstg
–55 to + 150
°C
Single Avalanche Current
Note2
IAS
3.0
A
Single Avalanche Energy
Note2
EAS
0.9
mJ
Notes 1. PW ≤ 10 µs, Duty Cycle ≤ 1 %
2. Starting Tch = 25 °C, VDD = 60 V, RG = 25 Ω, VGS = 20 V → 0 V
Remark
The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage
exceeding the rated voltage may be applied to this device.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No.
G14283EJ1V0DS00 (1st edition)
Date Published April 1999 NS CP(K)
Printed in Japan
©
1999
µ PA1560
ELECTRICAL CHARACTERISTICS (TA = 25 °C)
CHARACTERISTICS
SYMBOL
Drain to Source On-state Resistance
Gate to Source Cut-off Voltage
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
RDS(on)1
VGS = 10 V, ID = 1.5 A
130
165
mΩ
RDS(on)2
VGS = 4.0 V, ID = 1.5 A
145
200
mΩ
VGS(off)
VDS = 10 V, ID = 1.0 mA
1.0
1.8
2.5
V
2
4.5
Forward Transfer Admittance
| yfs |
VDS = 10 V, ID = 1.5 A
Drain Leakage Current
IDSS
VDS = 120 V, VGS = 0 V
10
µA
Gate to Source Leakage Current
IGSS
VGS = ±20 V, VDS = 0 V
±10
µA
Input Capacitance
Ciss
VDS = 10 V
600
pF
Output Capacitance
Coss
VGS = 0 V
160
pF
Reverse Transfer Capacitance
Crss
f = 1.0 MHz
70
pF
Turn-on Delay Time
t d(on)
ID = 1.5 A
35
ns
VGS(on) = 10 V
80
ns
td(off)
VDD = 60 V
700
ns
tf
RL = 30 Ω
250
ns
Total Gate Charge
QG
ID = 3.0 A
28
nC
Gate to Source Charge
QGS
VDD = 96 V
2.5
nC
Gate to Drain Charge
QGD
VGS = 10 V
9
nC
Rise Time
tr
Turn-off Delay Time
Fall Time
Body Diode Forward Voltage
S
VF(S-D)
IF = 3.0 A, VGS = 0 V
0.9
V
Reverse Recovery Time
trr
IF = 3.0 A, VGS = 0 V
160
ns
Reverse Recovery Charge
Qrr
di/dt = 50 A/ µs
280
nC
TEST CIRCUIT 1 AVALANCHE CAPABILITY
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
D.U.T.
RG = 25 Ω
PG
L
50 Ω
VDD
VGS = 20 → 0 V
RL
RG
RG = 10 Ω
PG.
ID
BVDSS
VDS
0
Starting Tch
τ = 1µ s
Duty Cycle ≤ 1 %
D.U.T.
RL
50 Ω
VDD
90 %
VDD
ID
Wave Form
TEST CIRCUIT 3 GATE CHARGE
IG = 2 mA
VGS(on)
10 %
90 %
90 %
ID
VGS
0
τ
VDD
2
Wave Form
ID
IAS
PG.
VGS
VGS
Data Sheet G14283EJ1V0DS00
10 %
0 10 %
tr
td(on)
ton
td(off)
tf
toff
µ PA1560
[MEMO]
Data Sheet G14283EJ1V0DS00
3
µ PA1560
• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
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rights of third parties by or arising from use of a device described herein or any other liability arising from use
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purposes in semiconductor product operation and application examples. The incorporation of these circuits,
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parties arising from the use of these circuits, software, and information.
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the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
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"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
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The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
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M7 98. 8