NEC UPA1819

DATA SHEET
MOS FIELD EFFECT TRANSISTOR
µ PA1819
P-CHANNEL MOS FIELD EFFECT TRANSISTOR
FOR SWITCHING
PACKAGE DRAWING (Unit: mm)
DESCRIPTION
The µ PA1819 is a switching device that can be driven
directly by a 4.0 V power source.
This device features a low on-state resistance and
excellent switching characteristics, and is suitable for
applications such as power management of notebook
computers and so on.
8
5
11, 2, 3: : Drain1
Source
2, 3
: Source1
Gate
44:
: Gate1
5
: Gate2
5,
6,
7,
8:
Drain
6, 7
: Source2
8
: Drain2
1.2 MAX.
1.0±0.05
0.25
FEATURES
3° +5°
–3°
• 4.0 V drive available
• Low on-state resistance
RDS(on)1 = 12 mΩ MAX. (VGS = −10 V, ID = −6.0 A)
RDS(on)2 = 18.5 mΩ MAX. (VGS = −4.5 V, ID = −6.0 A)
RDS(on)3 = 22 mΩ MAX. (VGS = −4.0 V, ID = −6.0 A)
• Built-in G-S protection diode against ESD
0.1±0.05
1
4
6.4 ±0.2
PACKAGE
µPA1819GR-9JG
Power TSSOP8
0.65
0.27
+0.03
–0.08
4.4 ±0.1
0.145 ±0.055
3.15 ±0.15
3.0 ±0.1
ORDERING INFORMATION
PART NUMBER
0.5
0.6 +0.15
–0.1
1.0 ±0.2
0.1
0.8 MAX.
0.10 M
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
Drain to Source Voltage (VGS = 0 V)
VDSS
−30
V
Gate to Source Voltage (VDS = 0 V)
VGSS
m20
V
Drain Current (DC) (TA = 25°C)
ID(DC)
m12
A
ID(pulse)
m48
A
PT
2.0
W
Channel Temperature
Tch
150
°C
Storage Temperature
Tstg
−55 to +150
°C
Drain Current (pulse)
Note1
Total Power Dissipation
Note2
EQUIVALENT CIRCUIT
Drain
Body
Diode
Gate
Gate
Protection
Diode
Source
Notes 1. PW ≤ 10 µs, Duty Cycle ≤ 1%
2
2. Mounted on ceramic substrate of 5000 mm x 1.1 mm
Remark
The diode connected between the gate and source of the transistor serves as a protector against ESD. When
this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated
voltage may be applied to this device.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. G16267EJ1V0DS00 (1st edition)
Date Published September 2002 NS CP(K)
Printed in Japan
©
2002
µ PA1819
ELECTRICAL CHARACTERISTICS (TA = 25°C)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Zero Gate Voltage Drain Current
IDSS
VDS = −30 V, VGS = 0 V
−1.0
µA
Gate Leakage Current
IGSS
VGS = m20 V, VDS = 0 V
m10
µA
−2.5
V
Gate Cut-off Voltage
VDS = −10 V, ID = −1.0 mA
VGS(off)
−2.0
11
23
| yfs |
VDS = −10 V, ID = −6.0 A
RDS(on)1
VGS = −10 V, ID = −6.0 A
9.8
12
mΩ
RDS(on)2
VGS = −4.5 V, ID = −6.0 A
13.9
18.5
mΩ
RDS(on)3
VGS = −4.0 V, ID = −6.0 A
16.4
22
mΩ
Forward Transfer Admittance
Drain to Source On-state Resistance
−1.0
S
Input Capacitance
Ciss
VDS = −10 V
2430
pF
Output Capacitance
Coss
VGS = 0 V
690
pF
Reverse Transfer Capacitance
Crss
f = 1.0 MHz
420
pF
Turn-on Delay Time
td(on)
VDD = −15 V, ID = −6.0 A
19
ns
VGS = −10 V
17
ns
RG = 10 Ω
160
ns
160
ns
Rise Time
tr
Turn-off Delay Time
td(off)
Fall Time
tf
Total Gate Charge
QG
VDD = −24 V
45
nC
Gate to Source Charge
QGS
VGS = −10 V
5.5
nC
Gate to Drain Charge
QGD
ID = −12 A
15
nC
Body Diode Forward Voltage
VF(S-D)
IF = 12 A, VGS = 0 V
0.83
V
Reverse Recovery Time
trr
IF = 12 A, VGS = 0 V
50
ns
Reverse Recovery Charge
Qrr
di/dt = 100 A/µs
40
nC
TEST CIRCUIT 1 SWITCHING TIME
TEST CIRCUIT 2 GATE CHARGE
D.U.T.
D.U.T.
VGS(−)
RL
VGS
RG
PG.
Wave Form
VDD
0
VGS
10%
PG.
90%
τ
τ = 1 µs
Duty Cycle ≤ 1%
2
90%
VDS
VDS
10%
0
10%
Wave Form
td(on)
tr
ton
RL
50 Ω
VDD
90%
VDS(−)
VGS(−)
0
IG = −2 mA
td(off)
tf
toff
Data Sheet G16267EJ1V0DS
µ PA1819
TYPICAL CHARACTERISTICS (TA = 25°C)
DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
TOTAL POWER DISSIPATION vs.
AMBIENT TEMPERATURE
2.5
PT - Total Power Dissipation - W
dT - Percentage of Rated Power - %
120
100
80
60
40
20
2
Mounted on ceramic
2
Substrate of 5000 mm x 1.1 mm
1.5
1
0.5
Mounted on FR-4 board
2
of 2500 mm x 1.6 mm
0
0
0
0
25
50
75
100
125
150
25
50
75
100
125
150
175
175
TA - Ambient Temperature - °C
TA - Ambient Temperature - °C
FORWARD BIAS SAFE OPERATING AREA
- 100
ID(pulse)
PW = 1 ms
10 ms
-1
R DS(on) Limited
(V GS = −10 V)
100 ms
- 0.1
DC
Single pulse
Mounted on ceramic
Substrate of 5000 mm 2 x 1.1 mm
- 0.01
- 0.1
-1
- 10
- 100
VDS - Drain to Source Voltage - V
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
1000
rth(ch-A) - Transient Thermal Resistance - °C/W
ID - Drain Current - A
ID(DC)
- 10
Single pulse
Mounted on FR-4 board
2
of 2500 mm x 1.6 mm
125°C/W
100
10
Mounted on ceramic
2
Substrate of 5000 mm x 1.1 mm
62.5°C/W
1
0.1
1m
10 m
100 m
1
10
100
1000
PW - Pulse Width - s
Data Sheet G16267EJ1V0DS
3
µ PA1819
DRAIN CURRENT vs.
DRAIN TO SOURCE VOLTAGE
FORWARD TRANSFER CHARACTERISTICS
- 50
- 100
- 10
VGS = −10 V
- 40
−4.0 V
- 30
- 20
- 10
-1
TA = 125°C
75°C
25°C
−25°C
- 0.1
- 0.01
- 0.001
0
- 0.0001
0
- 0.2
- 0.4
- 0.6
- 0.8
-1
-1
VDS - Drain to Source Voltage - V
- 1.5
- 3.5
| yfs | - Forward Transfer Admittance - S
- 2.2
- 2.0
- 1.8
- 1.6
0
50
100
VDS = −10 V
Pulsed
10
TA = −25°C
25°C
75°C
125°C
1
0.1
- 0.01
- 0.1
ID = −6.0 A
Pulsed
VGS = −4.0 V
20
−4.5 V
−10 V
50
100
- 100
DRAIN TO SOURCE ON-STATE RESISTANCE
vs.GATE TO SOURCE VOLTAGE
RDS(on) - Drain to Source On-state Resistance - mΩ
30
0
- 10
ID - Drain Current - A
DRAIN TO SOURCE ON-STATE RESISTANCE
vs. CHANNEL TEMPERATURE
10
-1
150
Tch - Channel Temperature - °C
RDS(on) - Drain to Source On-state Resistance - mΩ
-3
100
VDS = −10 V
ID = −1.0 mA
- 1.4
-50
150
Tch – Channel Temperrature - °C
4
- 2.5
FORWARD TRANSFER ADMITTANCE vs.
DRAIN CURRENT
- 2.4
0
-50
-2
VGS - Gate to Source Voltage - V
GATE CUT-OFF VOLTAGE vs.
CHANNEL TEMPERATURE
VGS(off) - Gate Cut-off Voltage - V
VDS = −10 V
Pulsed
−4.5 V
ID - Drain Current - A
ID - Drain Current - A
Pulsed
30
ID = −6.0 A
Pulsed
20
10
0
0
-5
- 10
- 15
VGS - Gate to Source Voltage - V
Data Sheet G16267EJ1V0DS
- 20
-4
µ PA1819
30
VGS = −10 V
Pulsed
TA = 125°C
75°C
25°C
−25°C
20
10
0
- 0.01
- 0.1
-1
- 10
- 100
DRAIN TO SOURCE ON-STATE RESISTANCE
vs. DRAIN CURRENT
RDS(on) - Drain to Source On-state Resistance - mΩ
RDS(on) - Drain to Source On-state Resistance - mΩ
DRAIN TO SOURCE ON-STATE RESISTANCE
vs. DRAIN CURRENT
30
VGS = −4.5 V
Pulsed
TA = 125°C
75°C
25°C
−25°C
20
10
0
- 0.01
- 0.1
ID - Drain Current - A
VGS = 0 V
f = 1.0 MHz
Ciss, C oss, Crss - Capacitance - pF
RDS(on) - Drain to Source On-state Resistance - mΩ
10000
VGS = −4.0 V
Pulsed
20
TA = 125°C
75°C
25°C
−25°C
- 0.1
-1
- 10
C iss
1000
Coss
Crss
100
- 0.1
- 100
ID - Drain Current - A
- 10
- 100
SOURCE TO DRAIN DIODE FORWARD VOLTAGE
VDD = −15 V
VGS = −10 V
RG = 10 Ω
tf
t d(off)
100
100
VGS = 0 V
Pulsed
IF - Diode Forward Current - A
td(on), tr, td(off), tf - Switching Time - ns
10000
-1
VDS - Drain to Source Voltage - V
SWITCHING CHARACTERISTICS
1000
- 100
CAPACITANCE vs.
DRAIN TO SOURCE VOLTAGE
30
0
- 0.01
- 10
ID - Drain Current - A
DRAIN TO SOURCE ON-STATE RESISTANCE
vs. DRAIN CURRENT
10
-1
10
1
0.1
t d(on)
tr
10
- 0.01
0.01
- 0.1
-1
- 10
- 100
ID - Drain Current - A
0.4
0.6
0.8
1
1.2
VF(S-D) - Source to Drain Voltage - V
Data Sheet G16267EJ1V0DS
5
µ PA1819
DYNAMIC INPUT/OUTPUT CHARACTERISTICS
- 10
VGS - Gate to Source Voltage - V
ID = −12 A
VDD = −6.0 V
−15 V
−24 V
-8
-6
-4
-2
0
0
10
20
30
40
50
QG - Gate Charge - nC
6
Data Sheet G16267EJ1V0DS
µ PA1819
[MEMO]
Data Sheet G16267EJ1V0DS
7
µ PA1819
• The information in this document is current as of September, 2002. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
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M8E 00. 4