DATA SHEET MOS FIELD EFFECT TRANSISTOR µ PA2503 N-CHANNEL MOS FIELD EFFECT TRANSISTOR FOR SWITCHING DESCRIPTION PACKAGE DRAWING (Unit: mm) 0.10 M • Low on-state resistance +0.1 spreader. The land size is same as 8-pin TSSOP. 0.25 −0.05 • µ PA2503 has a thin surface mount package with a heat 8 7 6 5 3 ±0.1 1 2 3 4 FEATURES 3.15 ±0.15 applications of notebook computers. 0.10 S 5.8 ±0.1 6.4 ±0.1 0.17 ±0.05 RDS(on)1 = 9.5 mΩ MAX. (VGS = 10.0 V, ID = 8.0 A) RDS(on)2 = 15.1 mΩ MAX. (VGS = 4.5 V, ID = 8.0 A) 0 −0 +0.05 • Low Ciss: 1200 pF TYP. (VDS = 10.0 V, VGS = 0 V) 0.8 MAX. MOS Field Effect Transistor designed for power management 0.65 TYP. The µ PA2503, which has a heat spreader, is N-channel PART NUMBER PACKAGE µ PA2503TM 8PIN HWSON 1, 2, 3 : Source 4 : Gate 5, 6, 7, 8: Drain 2.2 ±0.2 ORDERING INFORMATION 0.75 ±0.15 4.15 ±0.2 0.85 ±0.15 ABSOLUTE MAXIMUM RATINGS (TA = 25°C) Drain to Source Voltage (VGS = 0 V) VDSS 30.0 V Gate to Source Voltage (VDS = 0 V) VGSS ±20.0 V Drain Current (DC) Note1 Drain Current (pulse) Note2 Total Power Dissipation Note1 Channel Temperature Storage Temperature Single Avalanche Current Note3 Single Avalanche Energy Note3 ID(DC) ±16.0 A ID(pulse) ±64.0 A PT 2.7 W Tch 150 °C Tstg −55 to +150 °C IAS 16.0 A EAS 25.6 mJ 2 Notes 1. Mounted on FR-4 board of 25 cm x 1.6 mm, PW ≤ 10 sec 2. PW ≤ 10 µs, Duty Cycle ≤ 1% EQUIVALENT CIRCUIT Drain Body Diode Gate Gate Protection Diode Source 3. Starting Tch = 25°C, VDD = 30 V, RG = 25 Ω, VGS = 20.0 → 0 V Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage may be applied to this device. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. G16682EJ1V0DS00 (1st edition) Date Published December 2003 NS CP(K) Printed in Japan 2003 µ PA2503 ELECTRICAL CHARACTERISTICS (TA = 25°C) CHARACTERISTICS SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Zero Gate Voltage Drain Current IDSS VDS = 30.0 V, VGS = 0 V 1.0 µA Gate Leakage Current IGSS VGS = ±18.0 V, VDS = 0 V ±10.0 µA VGS(off) VDS = 10.0 V, ID = 1.0 mA 2.5 V Gate Cut-off Voltage Forward Transfer Admittance Note Drain to Source On-state Resistance Note 1.5 | yfs | VDS = 10.0 V, ID = 8.0 A RDS(on)1 VGS = 10.0 V, ID = 8.0 A 7.5 9.5 mΩ RDS(on)2 VGS = 4.5 V, ID = 8.0 A 11.0 15.1 mΩ 5 S Input Capacitance Ciss VDS = 10.0 V 1200 pF Output Capacitance Coss VGS = 0 V 320 pF Reverse Transfer Capacitance Crss f = 1.0 MHz 190 pF Turn-on Delay Time td(on) VDD = 15.0 V, ID = 8.0 A 12 ns VGS = 10.0 V 17 ns RG = 10 Ω 52 ns 15 ns Rise Time tr Turn-off Delay Time td(off) Fall Time tf Total Gate Charge QG VDD = 15.0 V 15 nC Gate to Source Charge QGS VGS = 5.0 V 4 nC QGD ID = 16.0 A 7 nC Gate to Drain Charge Body Diode Forward Voltage Note VF(S-D) IF = 16.0 A, VGS = 0 V 0.84 V Reverse Recovery Time trr IF = 16.0 A, VGS = 0 V 28 ns Reverse Recovery Charge Qrr di/dt = 100 A/µs 18 nC Note Pulsed: PW ≤ 350 µs, Duty Cycle ≤ 2% TEST CIRCUIT 1 AVALANCHE CAPABILITY D.U.T. RG = 25 Ω D.U.T. L 50 Ω PG. VGS = 20 → 0 V TEST CIRCUIT 2 SWITCHING TIME RL RG PG. VDD VGS VGS Wave Form 0 VGS 10% 90% VDD VDS 90% IAS VDS ID VDS τ τ = 1 µs Duty Cycle ≤ 1% TEST CIRCUIT 3 GATE CHARGE D.U.T. IG = 2 mA PG. 2 50 Ω 0 10% 10% tr td(off) Wave Form VDD Starting Tch 90% VDS VGS 0 BVDSS RL VDD Data Sheet G16682EJ1V0DS td(on) ton tf toff µ PA2503 TYPICAL CHARACTERISTICS (TA = 25°C) TOTAL POWER DISSIPATION vs. AMBIENT TEMPERATURE 120 3 PT - Total Power Dissipation - W dT - Percentage of Rated Power - % DERATING FACTOR OF FORWARD BIAS SAFE OPERATING AREA 100 80 60 40 20 Mounted on FR-4 board of 25 cm2 x 1.6 mm, PW ≤ 10 sec 2.5 2 1.5 1 0.5 0 0 0 25 50 75 100 125 150 175 0 TA - Ambient Temperature - °C 25 50 75 100 125 150 175 TA - Ambient Temperature - °C FORWARD BIAS SAFE OPERATING AREA 100 RDS(on) Limited (at VGS = 10 V) ID(pulse) ID(DC) PW = 1 ms 10 1 10 ms 30 ms 0.1 10 s Single pulse 2 Mounted on FR-4 board of 25 cm x 1.6 mm 0.01 0.1 1 10 100 VDS - Drain to Source Voltage - V TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH rth(ch-A) - Transient Thermal Resistance - °C/W ID - Drain Current - A 1000 1000 100 10 1 Single pulse Mounted on FR-4 board of 25 cm2 x 1.6 mm 0.1 1m 10 m 100 m 1 10 PW - Pulse Width - s Data Sheet G16682EJ1V0DS 100 1000 3 µ PA2503 DRAIN CURRENT vs. DRAIN TO SOURCE VOLTAGE FORWARD TRANSFER CHARACTERISTICS 100 80 ID - Drain Current - A ID - Drain Current - A Pulsed VGS = 10.0 V 60 4.5 V 40 20 0.2 0.4 0.6 0.8 0.1 1 1 1.5 2 2.5 3 3.5 4 4.5 VDS - Drain to Source Voltage - V VGS - Gate to Source Voltage - V GATE CUT-OFF VOLTAGE vs. CHANNEL TEMPERATURE FORWARD TRANSFER ADMITTANCE vs. DRAIN CURRENT | yfs | - Forward Transfer Admittance - S 2.4 VDS = 10.0 V ID = 1.0 mA 2 1.6 1.2 0.8 -50 0 50 100 150 100 VDS = 10.0 V Pulsed 10 TA = −25°C 25°C 75°C 125°C 1 0.1 0.01 0.01 0.1 1 10 100 Tch - Channel Temperature - °C ID - Drain Current - A DRAIN TO SOURCE ON-STATE RESISTANCE vs. DRAIN CURRENT DRAIN TO SOURCE ON-STATE RESISTANCE vs. GATE TO SOURCE VOLTAGE 25 Pulsed 20 15 VGS = 4.5 V 10.0 V 10 5 0 0.1 1 10 100 RDS(on) - Drain to Source On-state Resistance - mΩ VGS(off) - Gate Cut-off Voltage - V TA = 125°C 75°C 25°C −25°C 1 0.001 0 RDS(on) - Drain to Source On-state Resistance - mΩ 10 0.01 0 25 ID = 8.0 A Pulsed 20 15 10 ID - Drain Current - A 4 VDS = 10.0 V Pulsed 5 0 0 5 10 15 VGS - Gate to Source Voltage - V Data Sheet G16682EJ1V0DS 20 DRAIN TO SOURCE ON-STATE RESISTANCE vs. CHANNEL TEMPERATURE CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE 10000 25 ID = 8.0 A Pulsed 20 Ciss, Coss, Crss - Capacitance - pF RDS(on) - Drain to Source On-state Resistance - mΩ µ PA2503 VGS = 4.5 V 10.0 V 15 10 5 0 VGS = 0 V f = 1.0 MHz Ciss 1000 Coss Crss 100 -50 0 50 100 150 0.1 Tch - Channel Temperature - °C VGS - Gate to Source Voltage - V td(on), tr, td(off), tf - Switching Time - ns 5 100 td(off) tr 10 td(on) VDD = 15.0 V ID = 16.0 A 4 3 2 1 0 1 0.1 1 10 0 100 4 8 12 16 QG - Gate Charge - nC ID - Drain Current - A SOURCE TO DRAIN DIODE FORWARD VOLTAGE SINGLE AVALANCHE CURRENT vs. INDUCTIVE LOAD 100 100 VGS = 0 V Pulsed IAS - Single Avalanche Current - A IF - Diode Forward Current - A 100 DYNAMIC INPUT CHARACTERISTICS VDD = 15.0 V VGS = 10.0 V RG = 10 Ω tf 10 VDS - Drain to Source Voltage - V SWITCHING CHARACTERISTICS 1000 1 10 1 0.1 0.01 0.4 0.6 0.8 1 1.2 IAS = 16.0 A 10 1 EAS = 25.6 mJ VDD = 15.0 V RG = 25 Ω VGS = 20.0 → 0 V Starting Tch = 25°C 0.1 0.01 VF(S-D) - Source to Drain Voltage - V 0.1 1 10 L - Inductive Load - mH Data Sheet G16682EJ1V0DS 5 µ PA2503 EXAMPLE OF THE LAND PATTERN Please optimize the land pattern in consideration of density, appearance of solder fillets, common difference, etc in an actual design. l3 e1 b3 b2 (Unit: mm) l1 6 e1: 0.65 b2: 0.35 b3: 2.7 l1: 1.3 l2: 3.7 l3: 7.1 l2 Data Sheet G16682EJ1V0DS µ PA2503 • The information in this document is current as of December, 2003. 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