DATA SHEET MOS INTEGRATED CIRCUIT µPD4702 INCREMENTAL ENCODER 8-BIT UP/DOWN COUNTER CMOS INTEGRATED CIRCUITS DESCRIPTION The µPD4702 is 8-bit up/down counters for an incremental encoder. Two-phase (A, B) incremental input signals are phase-differentiated, and on each signal edge, an up-count is executed if the A phase is leading, or a down-count if the B phase is leading. Eight-bit count data is output in real time. A carry output and borrow output are also provided for counter overflow and underflow. The µPD4704 is also available; use of these enables the count width to be extended. PIN CONFIGURATION (Top View) FEATURES • Incremental inputs (A, B) • On-chip phase discrimination circuit (up-count mode Reset 1 20 VDD when the phase order is A → B, down-count mode when B → A) 4-multiplication count method A 2 19 Carry • On-chip edge detection circuit • 8-bit up/down counter latch output o Carry output, B 3 18 Borrow NC 4 17 STB borrow output • Count data output controllable (3-state output) CD0 5 16 OE CD1 6 15 CD7 • CMOS, single +5 V power supply CD2 7 14 CD6 CD3 8 13 CD5 NC 9 12 CD4 VSS 10 11 NC ORDERING INFORMATION Part Number Package µPD4702C 20-pin plastic DIP (300 mil) µPD4702G 20-pin plastic SOP (300 mil) PIN NAMES A B Reset 2-phase incremental signal inputs : Counter reset input STB OE : Latch strobe signal input : Output control signal input CD0-7 Carry : Count data outputs : Carry pulse output Borrow : Borrow pulse output Document No. IC-3304A (2nd edition) (O. D. No. IC-5403A) Date Published April 1997 P Printed in Japan © 1993 1994 µPD4702 BLOCK DIAGRAM Reset Carry A Phase Discrimination Edge Detection 8-Bit Up/Down Counter B Borrow 8-Bit Latch 3-State Output STB OE CD0–7 PIN FUNCTIONS Pin Name 2 Input/Output Function A, B Input (Schmitt) Incremental signal A phase and B phase signal input pins (Schmitt input) D0 to 7 Output (3-state) Count data output pins. Activated when OE is “L”, high impedance outputs when OE is “H”. Carry Output 8-bit counter carry signal output pin (active-low) Borrow Output 8-bit counter borrow signal output pin (active-low) RESET Input (Schmitt) 8-bit counter reset signal output pin Counter is reset when this pin is “H”. OE Input Count data output control signal input pin STB Input Counter data output latch signal. Data is latched on the fall of STB, and is held while STB = “L”. VDD Power supply input pin GND Ground pin µPD4702 1. DESCRIPTION OF OPERATIONS (1) Count operation The µPD4702 incorporates a phase discrimination circuit, and counts by 4-multiplication of the A and B input 2phase pulses. Therefore, a count operation is performed by an A input edge and a B input edge. Fig. 1 Count Operation Timing Chart Forward (Up-Count) Reverse (Down-Count) A Input Count Operation 1 2 3 4 5 4 3 2 1 0 B Input (2) Latch operation An R-S flip-flop is inserted in the strobe input of the latch circuit as shown in Fig. 2, and when STB changes from “H” to “L” during a count operation, the internal latch signal STB remains at “H” until the end of the count operation. Therefore, the count value is latched correctly even if STB input is performed asynchronously from the A and B input (if STB changes from “H” to “L” within tSABSTB (40 ns) after the A input or B input edge, the latch contents will be either the pre-count or post-count value). However, when a µPD4704 is added, the correct value cannot be latched if all digits are latched simultaneously when a carry or borrow is generated (the high-order digit may be latched before carry/borrow transmission). Fig. 2 STB Input Circuit From Phase Discrimination Circuit (Count Pulse) STB STB Latched when L A, B Inputs tSABSTB STB If tSABSTB is 40 ns or longer, the post-count value is input to the latch. 3 µPD4702 (3) Carry & borrow outputs If the counter performs an up-count operation when the count value is 0FFH, an active-low pulse is output to the Carry output (the pulse width is 25 ns MIN. 120 ns MAX. irrespective of the A/B phase input cycle. Similarly, if the counter performs a down-count operation when the count value is 00H, an active-low pulse is output to the Borrow output. A Borrow pulse is also output if a down-count operation is performed while RESET is “H” (during a reset), and therefore, when a µPD4704 is added, a reset must be executed at the same time. 4 µPD4702 2. OPERATING PRECAUTIONS As the µPD4702 incorporates an 8-bit counter, a large transient current flows in the case of a count value which changes all the bits (such as 00H ↔ 0FFH or 7FH ↔ 080H). This will cause misoperation unless the impedance of the power supply line is sufficiently low. It is therefore recommended that a decoupling capacitor (of around 0.1 µF) be connected between VDD and VSS right next to the IC as shown in Fig. 3. Fig. 3 Decoupling Capacitor +5 V C VDD µPD4702 C : 0.1 µF tantalum electrolytic laminated ceramic capacitor, etc. VSS Also, if a pulse shorter than the phase difference time tSAB (70 ns) is input to the A/ B phase inputs, this will result in a miscount. Therefore, if this kind of pulse is to be input because of encoder bounds, etc., a filter should be inserted in the A & B phase inputs. Fig. 4 A & B Phase Input Pulses A Phase (or B Phase) B Phase (or A Phase) PW If a pulse such that PW < 70 ns is input in the A or B phase, there is a danger of a miscount. If PW is at 70 ns or more, the count value remains the same before and after pulse input. (UP count → DOWN count or DOWN count → UP count is implemented, and therefore the the result is no change in the count value.) 5 µPD4702 ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, VSS = 0 V) PARAMETER SYMBOL RATING UNIT VDD –0.5 to +7.0 V Input voltage VI –1.0 to VDD +1.0 V Output voltage VO –0.5 to VDD +0.5 V Operating temperature Topt –40 to +85 °C Storage temperature Tstg –65 to +150 °C Permissible loss PD Supply voltage 500 (DIP) 200 (SOP) mW DC CHARACTERISTICS (TA = –40 to +85 °C, VDD = +5 V ±10 %) RATING PARAMETER SYMBOL TEST CONDITIONS UNIT MIN. Input voltage high VIL MAX. 0.8 V VIH A, B, Reset 2.6 V VIH Other than the above 2.2 V Output voltage low VOL IOL = 12 mA Output voltage high VOH IOH = –4 mA Static consumption current IDD VI = VDD, VSS II VI = VDD, VSS Input voltage low Input current 3-state output leak current Dynamic consumption current Hysteresis voltage IOFF IDD dyn VH 0.45 VDD – 0.8 V 50 µA –1.0 1.0 µA –10 10 µA 12 mA fIN = 3.6 MHz, CL = 50 pF A, B, Reset V 0.2 V AC CHARACTERISTICS (TA = –40 to +85 °C, VDD = +5 V ±10 %) PARAMETER Cycle tCYAB TEST CONDITIONS fin = 3.6 MHz MIN. MAX. UNIT 280 ns High-level width tPWABH 140 ns Low-level width tPWABL 140 ns tSAB 70 ns Setting time tSRSAB 0 ns Reset time tDRSCD 60 ns Output delay tDABCD 100 ns Output delay tDOECD 50 ns Output delay tDSTBCD 60 ns Float time tFOECD 40 ns Carry Output delay tDABCB 120 ns Borrow Output pulse width tPWCB 25 120 ns RESET Reset pulse width tPWRS 40 ns STB Setting time tSABSTB 40 ns A, B Phase difference time CD0 to 7 6 SYMBOL µPD4702 AC Timings Fig. 1 Two-Phase Signal Input Timing tCYAB tPWABH tPWABL A tSAB tSAB tSAB tSAB B tPWABH tPWABL tCYAB Fig. 2 Count Data Output Timing tPWRS Reset tSRSAB tSABSTB A/B tDRSCD tDABCD tDSTBCD CD0–7 tDOECD tFOECD OE STB Fig. 3 Carry/Borrow Signal Output Timing A/B (CD) (0FEH) (0FFH) (00) (01) (00) (0FFH) (0FEH) (0FDH) tDABCB Carry Borrow tPWCB tDABCB tPWCB 7 µPD4702 Consumption Current Measurement Circuit Measurement Conditions A, B inputs fIN = 3.6 MHz A D0 CL B 2.6 V D1 CL 0.8 V STB input connected to VDD or VDD OE input connected to VSS. STB Load on all outputs, CL = 50 pF. OE D7 CL AC Test Input Waveform VIH VIL VIH = 2.6 V (A, B, RESET inputs) VIH = 2.2 V (inputs other than A, B, RESET) VIL = 0.8 V Timing measurement is performed at 1.5 V. 8 µPD4702 Sample Application Circuits 16-bit counter 8 Data Bus Incremental Rotary Encoder 8 A Carry B Borrow 8 UP Down CD0 CD0 STB STB OE OE R CD7 R CD7 RESET µPD4702 µPD4704 CSL CSH The application circuits and their parameters are for references only and are not intended for use in actual design-in's. 9 µPD4702 RECOMMENDED SOLDERING CONDITIONS The following conditions (see table below) must be met when soldering this product. Please consult with our sales offices in case other soldering process is used, or in case soldering is done under different conditions. TYPES OF SURFACE MOUNT DEVICE For more details, refer to our document “Semiconductor Device Mounting Technology Manual” (IEI-1207). µPD4702G Soldering process * Soldering conditions Symbol Infrared ray reflow Peak package’s surface temperature: 235 °C or below, Reflow time: 30 seconds or below (210 °C or higher), Number of reflow process: 2, Exposure limit*: None IR35-00-2 VPS Peak package’s surface temperature: 215 °C or below, Reflow time: 40 seconds or below (200 °C or higher), Number of reflow process: 2, Exposure limit*: None VP15-00-2 Wave soldering Solder temperature: 260 °C or below, Flow time: 10 seconds or below, Number of flow process: 1, Exposure limit*: None WS60-00-1 Partial heating method Terminal temperature: 300 °C or below, Flow time: 10 seconds or below, Exposure limit*: None Exposure limit before soldering after dry-pack package is opened. Storage conditions: 25 °C and relative humidity at 65 % or less. Note Do not apply more than a single process at once, except for “Partial heating method”. TYPES OF THROUGH HOLE MOUNT DEVICE µPD4702C Soldering process Wave soldering Soldering conditions Symbol Solder temperature: 260 °C or below, Flow time: 10 seconds or below REFERENCE Dcodument name 10 Document No. NEC semiconductor device reliability/quality control system IEI-1212 Quality grade on NEC semiconductor devices IEI-1209 Semiconductor device mounting technology manual IEI-1207 Semiconductor device package manual IEI-1213 Guide to quality assurance for semiconductor devices MEI-1202 Semiconductor selection guide MF-1134 µPD4702 20PIN PLASTIC DIP (300 mil) 20 11 1 10 A K L P I J H C F D N R M B G M NOTES 1) Each lead centerline is located within 0.25 mm (0.01 inch) of its true position (T.P.) at maximum material condition. 2) ltem "K" to center of leads when formed parallel. ITEM MILLIMETERS INCHES A B 25.40 MAX. 1.27 MAX. 1.000 MAX. 0.050 MAX. C 2.54 (T.P.) 0.100 (T.P.) D 0.50±0.10 0.020 +0.004 –0.005 F 1.1 MIN. 0.043 MIN. G H 3.5±0.3 0.51 MIN. 0.138±0.012 0.020 MIN. I J 4.31 MAX. 5.08 MAX. 0.170 MAX. 0.200 MAX. K 7.62 (T.P.) 0.300 (T.P.) L 6.4 0.252 M 0.25 +0.10 –0.05 0.010 +0.004 –0.003 N 0.25 P 0.9 MIN. R 0~15 ° 0.01 0.035 MIN. 0~15° P20C-100-300A,C-1 11 µPD4702 20 PIN PLASTIC SOP (300 mil) 20 11 P detail of lead end 1 10 A H J E K F G I C N D M L B M NOTE Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 13.00 MAX. 0.512 MAX. B 0.78 MAX. 0.031 MAX. C 1.27 (T.P.) 0.050 (T.P.) D 0.40 +0.10 –0.05 0.016 +0.004 –0.003 E 0.1±0.1 0.004±0.004 F 1.8 MAX. 0.071 MAX. G 1.55 0.061 H 7.7±0.3 0.303±0.012 I 5.6 0.220 J 1.1 0.043 K 0.20 +0.10 –0.05 0.008 +0.004 –0.002 L 0.6±0.2 M 0.12 0.005 N 0.10 0.004 P 3 ° +7° –3° 3° +7° –3° 0.024 +0.008 –0.009 P20GM-50-300B, C-4 12 µPD4702 [MEMO] 13 µPD4702 [MEMO] 14 µPD4702 [MEMO] 15 µPD4702 [MEMO] No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5