DATA SHEET MOS INTEGRATED CIRCUIT µPD17P218 4-BIT SINGLE-CHIP MICROCONTROLLER FOR INFRARED REMOTE CONTROLLER DESCRIPTION The µPD17P218 is a model of the µPD17218 with a one-time PROM instead of an internal mask ROM. ★ Since the user can write programs to the µPD17P218, it is ideal for experimental production or small-scale production of the µPD17215, 17216, 17217 or 17218 systems. When reading this document, also read the documents related to the µPD17215, 17216, 17217 and 17218. Detailed functions are described in the following user’s manual. Read this manual when designing your system. µPD172×× Series User’s Manual: IEU-1317 FEATURES • Pin compatible with µPD17215, 17216, 17217 and 17218 (except PROM programming function) • Carrier generator circuit for infrared remote controller (REM output) • 17K architecture: General-purpose register method • Program memory (one-time PROM): 16K bytes (8192 × 16) • Data memory (RAM): 223 × 4 bits • Pull-up resistor can be connected to RESET pin Note. • Low-voltage detection circuit (WDOUT output) Note • Operating voltage range: 2.0 to 5.5 V (fx = 4 MHz: normal mode, 8 µs) 2.2 to 5.5 V (fx = 4 MHz: high-speed mode, 4 µs) 3.5 to 5.5 V (fx = 8 MHz: high-speed mode, 2 µs) Note: Can be selected by mask option with the mask model. APPLICATIONS Preset remote controllers, toys, and portable systems ORDERING INFORMATION Part Number Package Quality Grade µPD17P218GT 28-pin plastic SOP (375 mil) Standard µPD17P218CT 28-pin plastic shrink DIP (400 mil) Standard Please refer to “Quality Grade on NEC Semiconductor Devices” (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. The information in this document is subject to change without notice. Document No. IC - 3252 (O. D. No. IC - 8797) Date Published September 1994 P Printed in Japan The mark ★ shows major revised points. © 1994 µPD17P218 PIN CONFIGURATION (TOP VIEW) (1) P0D 2 1 28 P0D 1 P0D 3 2 27 P0D 0 INT 3 26 P0C 3 P0E 0 4 25 P0C 2 P0E 1 5 24 P0C 1 P0E 2 6 23 P0C 0 P0E 3 7 22 P0B 3 REM 8 21 P0B 2 V DD 9 20 P0B 1 X OUT 10 19 P0B 0 X IN 11 18 P0A 3 GND 12 17 P0A 2 RESET 13 16 P0A 1 WDOUT 14 15 P0A 0 µ PD17P218GT µ PD17P218CT 2 Normal operation mode GND : Ground INT : External interrupt request signal input P0A0-P0A3 : Port 0A (CMOS input) P0B0-P0B3 : Port 0B (CMOS input) P0C0-P0C3 : Port 0C (N-ch open-drain output) P0D0-P0D3 : Port 0D (N-ch open-drain output) P0E0-P0E3 : Port 0E (CMOS push-pull output) REM : Remote controller transmission output (CMOS push-pull output) RESET : Reset input VDD : Positive power supply WDOUT : Hang-up detection/low-voltage detection output (N-ch open-drain output) XIN, XOUT : Oscillation connection µPD17P218 (2) PROM programming mode 1 28 D1 D3 2 27 D0 V PP 3 26 D7 4 25 D6 5 24 D5 23 D4 22 MD 3 21 MD 2 20 MD 1 MD 0 (L) 6 7 (Open) 8 V DD 9 µ PD17P218GT µ PD17P218CT D2 (Open) 10 19 CLK 11 18 GND 12 17 (L) 13 16 (Open) 14 15 (L) Note: Those enclosed in parentheses indicate the processing of the pins not used in PROM programming mode. L : Ground these pins through a resistor (470 W). Open : Do not connect anything to these pins. CLK : PROM clock input D0-D7 : PROM data I/O GND : Ground MD0-MD3 : PROM mode selection VDD : Positive power supply VPP : PROM writing power supply 3 µPD17P218 BLOCK DIAGRAM P0A 0 P0A 1 P0A 2 P0A 3 P0A Remote Control Divider RF RAM 223 × 4 bits P0B 0 /MD 0 P0B 1 /MD 1 P0B 2 /MD 2 P0B 3 /MD 3 REM 8-bit Timer/ Counter SYSTEM REG. P0B Interrupt Controller INT/V PP ALU P0C 0 /D 4 P0C 1 /D 5 P0C 2 /D 6 P0C 3 /D 7 P0D 0 /D 0 P0D 1 /D 1 P0D 2 /D 2 P0D 3 /D 3 P0C One Time PROM 8192 × 16 bits Instruction Decoder RESET P0D WDOUT Program Counter P0E 0 P0E 1 P0E 2 P0E 3 Power Supply Circuit P0E Stack 5 × 13 bits Basic Interval/ Watchdog Timer 4 V DD GND CPU Clock XIN /CLK OSC XOUT µPD17P218 CONTENTS 1. DIFFERENCES BETWEEN µPD17P218 AND µPD17215/17216/17217/17218 .................................. 6 2. PIN FUNCTIONS ................................................................................................................................. 7 2.1 IN NORMAL MODE ................................................................................................................................ 7 2.2 IN PROM PROGRAMMING MODE ........................................................................................................ 8 2.3 PIN I/O CIRCUITS ................................................................................................................................... 8 2.4 PROCESSING OF UNUSED PINS .......................................................................................................... 11 ★ 2.5 NOTES ON USING INT AND RESET PINS ........................................................................................... 11 ★ 3. WRITING/VERIFYING ONE-TIME PROM (PROGRAM MEMORY) .................................................. 12 3.1 OPERATION MODE FOR WRITING/VERIFICATION OF PROGRAM MEMORY .................................. 12 3.2 PROGRAM MEMORY WRITE PROCEDURE ......................................................................................... 13 3.3 PROGRAM MEMORY READ PROCEDURE ........................................................................................... 14 4. ELECTRICAL SPECIFICATIONS (PRELIMINARY) ........................................................................... 15 5. PACKAGE DRAWINGS .................................................................................................................... 23 6. RECOMMENDED SOLDERING CONDITIONS ................................................................................ 25 ★ APPENDIX A. FUNCTION OF µPD17215 SUB-SERIES PRODUCTS ................................................. 26 APPENDIX B. DEVELOPMENT TOOLS ............................................................................................... 27 5 µPD17P218 ★ 1. DIFFERENCES BETWEEN µPD17P218 AND µPD17215/17216/17217/17218 The µPD17P218 is a model of the µPD17218 provided with a one-time PROM as the program memory, to which the user can write data, instead of an internal mask ROM. Table 1-1 shows the differences among the µPD17P218, µPD17215, 17216, 17217, and 17218. These five products have different memory capacities and mask options but the same CPU function and internal hardware. Therefore, the µPD17P218 can be used to evaluate the program of a system using the µPD17215, 17216, 17217, or 17218. Note that part of the electrical specifications of the µPD17P218 such as supply current and lowvoltage detection voltage are different from those of the µPD17215, 17216, 17217, and 17218. For the detail of the CPU functions and internal hardware, refer to the Data Sheet of the µPD17215, 17216, 17217, and 17218. Table 1-1 Differences between µPD17P218 and 17215/17216/17217/17218 Product Name Item µPD17P218 µPD17215 µPD17216 One-time PROM Program Memory 223 × 4 bits Pull-Up Resistor of RESET Pin 8 K bytes (4096 × 16) 12 K bytes (6144 × 16) 16 K bytes (8192 × 16) (0000H-0FFFH) (0000H-17FFH) (0000H-1FFFH) 111 x 4 bits 223 x 4 bits Provided Any (mask option) Note Provided Any (mask option) VPP Pin, Operation Mode Select Pin Provided Not provided Low-Voltage Detector Circuit Instruction Execution Time Operation When P0C, P0D Are Standby Operating Voltage Range Package µPD17218 Mask ROM 16 K bytes (8192 × 16) 4 K bytes (2048 × 16) (0000H-1FFFH) (0000H-07FFH) Data Memory µPD17217 2 µs (8 MHz ceramic oscillator: in high-speed mode) 4 µs (4 MHz ceramic oscillator: in high-speed mode) 16 µs (1 MHz ceramic oscillator: in high-speed mode) Retain output level immediately before standby mode 2.2 to 5.5 V (at 4 MHz, in high-speed mode) 28-pin plastic SOP (375 mil) 28-pin plastic shrink DIP (400 mil) Note: Although the circuit configuration of the low-voltage detector circuit is identical, its electrical specifications differ depending on the product. 6 µPD17P218 2. PIN FUNCTIONS 2.1 IN NORMAL MODE Pin No. Symbol Function Output Format On Reset — Input — Input 4-bit N-ch open-drain output port. Can be used for key source output of key matrix. This port retains output level immediately before standby mode is set when standby mode is set, and outputs low level on reset. N-ch open-drain Low-level output 4-bit N-ch open-drain output port. Can be used for key source output of key matrix. This port retains output level immediately before standby mode is set when standby mode is set, and outputs low level on reset. N-ch open-drain Low-level output 4-bit I/O port which can be set in input or output mode in bit units. In output mode, this port serves as high-current CMOS output port. In input mode, it serves as CMOS input port to which pull-up resistor can be connected by program in bit units. On reset, this port is set as input port. CMOS push-pull Input 15 P0A0 16 P0A1 17 P0A2 18 P0A3 19 P0B0 20 P0B1 21 P0B2 22 P0B3 23 P0C0 24 P0C1 25 P0C2 26 P0C3 27 P0D0 28 P0D1 1 P0D2 2 P0D3 4 P0E0 5 P0E1 6 P0E2 7 P0E3 8 REM Infrared remote controller transmission output pin. Outputs low level on reset. CMOS push-pull Low-level output 13 RESET System reset input pin. By inputting low level to this pin, CPU can be reset. While low level is input to this pin, oscillation circuit stops oscillating. RESET pin of µPD17P218 is provided with pull-up resistor. — Input 9 VDD Positive power supply pin — — 12 GND Ground — — 3 INT External interrupt request input — Input N-ch open-drain High-impedance or low-level output — (Oscillation stops) 14 WDOUT 11 XIN 10 XOUT 4-bit CMOS input port with pull-up resistor. Can be used for key return input of key matrix. This port can release standby mode when at least one of pins goes low. 4-bit CMOS input port with pull-up resistor. Can be used for key return input of key matrix. This port can release standby mode when at least one of pins goes low. Output for detection of hang-up or voltage drop. Outputs low level when watchdog timer overflows, when stack overflows/underflows, or when low voltage is detected. Connect this pin to RESET pin. Connect ceramic oscillator for system clock oscillation across these pins. 7 µPD17P218 2.2 IN PROM PROGRAMMING MODE Pin No. Symbol 3 VPP 9 VDD 11 CLK 12 Output Format On Reset — — Positive power supply. Apply 6 V to this pin when writing/ verifying program memory. — — Inputs clock for PROM programming. — — GND Ground — — 19 MD0 | | Input pins used to select operation mode when PROM is programmed. — Input CMOS push-pull Input 22 MD3 23 D4 | | 26 D7 27 D0 28 D1 1 D2 2 D3 Function Power supply for PROM programming. Apply 12.5 V to this pin as the program voltage when writing/verifying program memory. Input/output 8-bit data for PROM programming. Remarks: Pins other than above are not used in the PROM programming mode. For the processing of the unused pins, refer to PIN CONFIGURATION (2) PROM programming mode. 2.3 PIN I/O CIRCUITS This section shows the I/O circuits of the µPD17P218 pins in simplified schematic diagrams. (1) P0A0-P0A3, P0B0/MD0-P0B3/MD3 V DD Input buffer 8 µPD17P218 (2) P0C0/D4-P0C3/D7, P0D0/D0-P0D3/D3 Output latch Data N-ch Input buffer (3) Data P0E0-P0E3 V DD Pull-up resistor P-ch V DD Data Output latch P-ch N-ch Output disable Multiplexer Input buffer 9 µPD17P218 (4) RESET V DD Pull-up resistor Note Input buffer Note: Can be selected with mask option when mask products such as µPD17215, 17216, 17217, and 17218 are used. Remarks: Schmitt trigeer input with hysteresis characteristics (5) INT (Schmitt trigger input) Input buffer Remarks: Schmitt trigeer input with hysteresis characteristics 10 µPD17P218 2.4 ★ PROCESSING OF UNUSED PINS Process the unused pins as follows: Table 2-1 Processing of Unused Pins Pin 2.5 Recommended Connection P0A0-P0A3 Connect to VDD P0B0-P0B3 Connect to VDD P0C0-P0C3 Connect to GND P0D0-P0D3 Connect to GND P0E0-P0E3 Input : Connect to VDD or GND Output : Open REM Open INT Connect to GND WDOUT Connect to GND ★ NOTES ON USING INT AND RESET PINS In addition to the functions shown in 2 PIN FUNCTIONS, the INT and RESET pins also have a function to set a test mode (for IC testing) in which the internal operations of the µPD17P218 are tested. When a voltage higher than VDD is applied to either of these pins, the test mode is set. This means that, even during normal operation, the µPD17P218 may be set in the test mode and malfunction if a noise exceeding VDD is applied. For example, if the wiring length of the INT or RESET pin is too long, noise superimposed on the wiring line of the pin may cause the above problem. Therefore, keep the wiring length of these pins as short as possible to suppress the noise; otherwise, take noise preventive measures as shown below by using external components. • Connect diode with low VF between VDD • Connect capacitor between VDD and INT/RESET pin and INT/RESET pin V DD Diode with low V F V DD V DD INT, RESET V DD INT, RESET Moreover, if the test mode is set by the INT pin, low level is output from the WDOUT pin. In this case, connect the WDOUT pin to the RESET pin. 11 µPD17P218 3. WRITING/VERIFYING ONE-TIME PROM (PROGRAM MEMORY) The program memory of the µPD17P218 is a one-time PROM of 8192 x 16 bits. To write data to or verify this one- time PROM, the pins shown in the following table are used. No address input pin is used, as the address is updated by the clock input from the CLK pin. Table 3-1 Pins Used to Write/Verify Program Memory Function Pin Name 3.1 VPP Applies voltage when program memory is written/verified. Apply +12.5 V to this pin. VDD Positive power supply. Apply +6 V to write/verify program memory. CLK Input clock to update address when program memory is written/verified. Program memory address is updated when four pulses are input to this pin. MD0-MD3 Select operation mode when program memory is written/verified. D0-D7 Input/output 8-bit data when program memory is written/verified. OPERATION MODE FOR WRITING/VERIFICATION OF PROGRAM MEMORY If +6 V is applied to the VDD and +12.5 V to the VPP pin after µPD17P218 has been placed in the reset status for a fixed time (VDD = 5V, RESET = 0V), µPD17P218 enters program memory write/verify mode. The MD0 to MD3 pins are used to set the operating modes listed in the following table. Leave the pins not used for program memory writing/verification open or connect to GND through pull-down resistors (470 Ω) (Refer to PIN CONFIGRATION (2) PROM programming mode). Table 3-2 Operating Mode Specification Operating Mode Specification Operating Mode VPP +12.5 V VDD MD0 MD1 MD2 MD3 H L H L Program memory address 0 clear mode L H H H Write mode L L H H Verify mode H × H H Program inhibit mode +6 V Remarks: ×: don‘t care (L or H) 12 µPD17P218 3.2 PROGRAM MEMORY WRITE PROCEDURE The program memory write procedure is as follows. High-speed program memory write is possible. (1) Ground the unused pins through pull-down resistors. The CLK pin must be low. (2) Supply 5 V to the VDD pin. The VPP pin must be low. (3) After waiting for 10 microseconds, supply 5 V to the VPP pin. (4) Operate the MD0 to MD3 pins to set program memory address 0 clear mode. (5) Supply 6 V to the VDD pin and 12.5 V to the VPP pin. (6) Set program inhibit mode. (7) Write data in 1-millisecond write mode. (8) Set program inhibit mode. (9) Set verify mode. If data has been written connectly, proceed to step (10). If data has not yet been written, repeat steps (7) to (9). (10) Write additional data for (the number of times data was written (×) in steps (7) to (9)) times 1 milliseconds. (11) Set program inhibit mode. (12) Supply a pulse to the CLK pin four times to update the program memory address by 1. (13) Repeat steps (7) to (12) to the last address. (14) Set program memory address 0 clear mode. (15) Change the voltages of VDD and VPP pins to 5 V. (16) Turn off the power supply. Steps (2) to (12) are illustrated below. X-time repetition Reset Write Verify Additional data write Address increment VPP VPP VDD GND VDD+1 VDD VDD GND CLK D 0 -D 7 Data input Data output Data input MD 0 MD 1 MD 2 MD 3 Remarks: Broken line indicates high impedance. 13 µPD17P218 3.3 PROGRAM MEMORY READ PROCEDURE (1) Ground the unused pins through pull-down resistors. The CLK pin must be low. (2) Supply 5 V to the VDD pin. The VPP pin must be low. (3) After waiting for 10 microseconds, supply 5 V to the VPP pin. (4) Operate the MD0 to MD3 pins to set program memory address 0 clear mode. (5) Supply 6 V to the VDD pin and 12.5 V to the VPP pin. (6) Set program inhibit mode. (7) Set verify mode. Data of each address is sequentially output each time a clock pulse is input to the CLK pin four times. (8) Set program inhibit mode. (9) Set program memory address 0 clear mode. (10) Change the voltages of VDD and VPP pins to 5 V. (11) Turn off the power supply. Steps (2) to (9) are illustrated below. VPP VPP VDD GND VDD+1 VDD VDD GND 1 cycle CLK Hi-Z D 0 - D7 MD 0 MD 1 MD 2 MD 3 14 L Data output Data output Hi-Z µPD17P218 4. ELECTRICAL SPECIFICATIONS (PRELIMINARY) ABSOLUTE MAXIMUM RATINGS (Ta = 25 °C) Item Symbol Conditions Ratings Unit –0.3 to +7.0 V Supply Voltage VDD Input Voltage VI –0.3 to VDD +0.3 V Output Voltage VO –0.3 to VDD +0.3 V Peak value –36.0 mA Effective value –24.0 mA Peak value –7.5 mA Effective value –5.0 mA Peak value –22.5 mA Effective value –15.0 mA Peak value 7.5 mA Effective value 5.0 mA Peak value 30.0 mA Effective value 20.0 mA Total of P0C, P0D, Peak value 22.5 mA WDOUT pins Effective value 15.0 mA REM pin High-Level Output Current Note IOH 1 pin (P0E pin) Total of P0E pins 1 pin Low-Level Output Current Note IOL Total of P0E pins Operating Temperature Topt –40 to +85 °C Storage Temperature Tstg –60 to +150 °C Power dissipation Pd 180 mW Ta = 85°C Note: Effective value = Peak value × √Duty. ★ ★ ★ Caution: Even if one of the parameters exceeds its absolute maximum rating even momentarily, the quality ★ of the product may be degraded. The absolute maximum rating therefore specifies the upper or lower limit of the value at which the product can be used without physical damages. Be sure not to exceed or fall below this value when using the product. RECOMMENDED OPERATING RANGE (VDD = 2.0 to 5.5 V, Ta = –40 to +85 °C) Item VDD1 Supply Voltage Conditions Note Symbol fx = 1 MHz VDD2 fx = 4 MHz VDD3 VDD4 Oscillation Frequency fx = 8 MHz ★ MIN. TYP. MAX. 2.0 3.0 5.5 High-speed mode (4 µs) 2.2 3.0 5.5 High-speed mode (2 µs) 3.5 5.0 5.5 1.0 4.0 8.0 High-speed mode (16 µs) Normal mode (8 µs) fX Unit V MHz Note: Figures in parentheses indicate instruction execution time. 15 µPD17P218 SYSTEM CLOCK OSCILLATOR CIRCUIT CHARACTERISTICS (Ta = –40 to +85°C, VDD = 2.0 to 5.5 V) Recommended Constants Oscillator X IN X OUT Ceramic Oscillator Crystal Oscillator X OUT Conditions Oscillation frequency (fx) Note 1 Oscillation stabilization timeNote 2 X IN ★ Item TYP. MAX. Unit 1.0 4.0 8.0 MHz 4 ms 8.0 MHz 10 ms 30 ms After VDD has reached MIN value of oscillation voltage range Oscillation frequency (fx) Note 1 Oscillation stabilization timeNote 2 MIN. 1.0 4.0 VDD = 4.5 to 5.5 V Note 1: The oscillation frequency indicates only the characteristics of the oscillation circuit. 2: The oscillation stabilization time is the time required for oscillation to stabilize after VDD has been applied or the STOP mode has been released. Caution: Wire the shaded portion in the above figures as follows to prevent adverse influence of wiring capacitance when the system clock oscillation circuit is used: • Keep the wiring length as short as possible. • Do not cross the wiring with the other signal lines. Do not place the wiring in the vicinity of lines through which a high alternating current flows. • Always keep the ground of the capacitor of the oscillation circuit at the same potential as GND. Do not ground the capacitor to a ground pattern through which a high current flows. • Do not extract a signal from the oscillation circuit. 16 µPD17P218 DC CHARACTERISTICS (VDD = 2.0 to 5.5 V, Ta = –40 to +85 °C) Item Symbol Conditions MIN. TYP. MAX. Unit VIH1 RESET, INT pin 0.8VDD VDD V VIH2 P0A, P0B 0.7VDD VDD V VIH3 P0E 2.0 V ≤ VDD < 3.0 V VDD–0.3 VDD V VIH4 P0E 3.0 V ≤ VDD ≤ 5.5 V VDD–0.5 VDD V VIH5 XIN 0.8VDD VDD V VIL1 RESET, INT pins 0 0.2VDD V VIL2 P0A, P0B 0 0.3VDD V VIL3 P0E 0 0.35VDD V VIL4 XIN 0 0.2VDD V VOH P0E, REM IOH = –0.5 mA VDD–0.3 VDD V VOL1 P0C, P0D, REM, WDOUT IOL = 0.5 mA 0 0.3 V VOL2 P0E IOL = 1.5 mA 0 0.3 V High-Level Input Current IIH XIN VIH = VDD 20 µA Low-Level Input Current IIL XIN VIL = 0 V –20 µA High-Level Input Leakage Current ILIH INT, RESET, P0A, P0B, P0E VIH = VDD 3.0 µA High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage Low-Level Output Voltage ILIL1 INT VIL = 0 V –3.0 µA Low-Level Input Leakage Current ILIL2 P0E VIL = 0 V w/o pull-up resistor –3.0 µA High-Level Output Current IOH REM VOH = 1.0 V, VDD = 3 V –24.0 mA High-Level Output Leakage Current ILOH P0C, P0D, P0E, WDOUT VOH = VDD 3.0 µA ILOL1 WDOUT VOL = 0 V –3.0 µA ILOL2 P0E VOL = 0 V w/o pull-up resistor –3.0 µA RU1 RESET, P0E Low-Level Output Leakage Current Internal Pull-Up Resistor RU2 Low-Voltage Detector Voltage VDT P0A, P0B –6.0 –13.0 VDD = 3 V ± 10 % 25 50 100 kΩ VDD = 5 V ± 10 % 25 50 100 kΩ VDD = 3 V ± 10 % 100 200 400 kΩ VDD = 5 V ± 10 % 100 200 400 kΩ 0.5 1.4 2.0 V WDOUT = Low level, VDT = VDD ★ 17 µPD17P218 ★ DC CHARACTERISTICS (VDD = 2.0 to 5.5 V, Ta = –40 to +85 °C) Item Symbol Conditions Unit Operating mode (High-speed mode) VDD = 5 V ± 10 % 3.8 7.6 mA IDD2 fX = 8 MHz HALT mode VDD = 5 V ± 10 % 2.6 5.2 mA Operating mode (High-speed mode) VDD = 5 V ± 10 % 2.3 4.6 mA VDD = 3 V ± 10 % 1.2 2.5 mA VDD = 5 V ± 10 % 2.0 4.0 mA VDD = 3 V ± 10 % 1.0 2.0 mA VDD = 2.0 to 2.2 V 0.55 1.1 mA VDD = 5 V ± 10 % 1.8 3.6 mA VDD = 3 V ± 10 % 1.0 2.0 mA VDD = 2.0 to 2.2 V 0.5 1.0 mA VDD = 3 V ± 10 % 0.7 2.1 mA VDD = 2.0 to 2.2 V 0.3 0.9 mA VDD = 3 V ± 10 % 0.6 1.8 mA VDD = 2.0 to 2.2 V 0.2 0.6 mA VDD = 5 V ± 10 % 1 30 µA VDD = 3 V ± 10 % 1 20 µA VDD = 2.0 to 2.2 V 1 16 µA VDD = 5 V ± 10 % 1 20 µA VDD = 3 V ± 10 % 1 10 µA VDD = 2.0 to 2.2 V 1 8 µA VDD = 5 V ± 10 % 1 5 µA VDD = 3 V ± 10 % 1 5 µA VDD = 2.0 to 2.2 V 1 5 µA 5.5 V IDD4 IDD5 IDD6 IDD7 IDD8 IDD9 18 MAX. fX = 8 MHz fX = 4 MHz Operating mode (Normal mode) Data Retention Voltage TYP. IDD1 IDD3 Supply Current MIN. VDDR fX = 4 MHz fX = 1 MHz fX = 1 MHz HALT mode Operating mode (High-speed mode) HALT mode STOP mode (Ta = –40 to +85 ˚C) STOP mode (Ta = –20 to +70 ˚C) STOP mode (Ta = 25 °C) RESET = Low level or in STOP mode 1.3 µPD17P218 AC CHARACTERISTICS (Ta = –40 to +85 °C) Item Symbol CPU Clock Cycle Time Note (Instruction Execution Time) Conditions MIN. TYP. MAX. Unit tCY1 VDD = 3.5 to 5.5 V 1.99 32.2 µs tCY2 VDD = 2.2 to 5.5 V 3.98 32.2 µs tCY3 VDD = 2.0 to 5.5 V 7.96 32.2 µs tIOH1 VDD = 4.5 to 5.5 V 10.0 µs tIOH2 VDD = 2.0 to 5.5 V 50.0 µs tIOL1 VDD = 4.5 to 5.5 V 10.0 µs tIOL2 VDD = 2.0 to 5.5 V 50.0 µs tRSL1 VDD = 4.5 to 5.5 V 10.0 µs tRSL2 VDD = 2.0 to 5.5 V 50.0 µs INT High-Level Width INT Low-Level Width RESET Low-Level Width Note: CPU clock cycle time (instruction execution time) is determined depending on the connected oscillation frequency and SYSCK (RF: address 02H) in the register file. The following figure shows CPU clock cycle time tCY characteristics versus supply voltage VDD. ★ tCY vs VDD 40 CPU clock cycle time tCY [µs] 32 10 9 8 7 6 5 4 3 2 2.2 V 0 1 2 3 4 5 6 Supply voltage VDD [V] 19 µPD17P218 DC PROGRAMMING CHARACTERISTICS (Ta = 25°C, VDD = 6.0 ± 0.25 V, VPP = 12.5 ± 0.3 V) Item High-Level Input Voltage Low-Level Input Voltage Symbol Conditions MAX. Unit VDD V Other than CLK 0.7 VDD VIH2 CLK VDD –0.5 VDD V VIL1 Other than CLK 0 0.3 VDD V 0 0.4 V 10 µA 0.4 V 30 mA 30 mA VIL2 CLK ILI VIN = VIL or VIH High-Level Output Voltage VOH IOH = –1 mA Low-Level Output Voltage VOL IOL = 1.6 mA VDD Supply Current IDD IPP MD0 = VIL, MD1 = VIH Caution 1: VPP must not exceed +13.5 V, including the overshoot. 2: Apply VDD before VPP and disconnect it after VPP. 20 TYP. VIH1 Input Leakage Current VPP Supply Current MIN. VDD –1.0 V µPD17P218 AC PROGRAMMING CHARACTERISTICS (Ta = 25°C, VDD = 6.0 ± 0.25 V, VPP = 12.5 ± 0.3 V) Item Symbol Note 1 Conditions MIN. TYP. MAX. Unit tAS tAS 2 µs MD1 Setup Time (vs. MD0↓) tM1S tOES 2 µs Data Setup Time (vs. MD0↓) tDS tDS 2 µs tAH tAH 2 µs Data Hold Time (vs. MD0↑) tDH tDH 2 MD0 ↑→ Data Output Float Delay Time tDF tDF 0 VPP Setup Time (vs. MD3↑) tVPS tVPS 2 µs VDD Setup Time (vs. MD3↑) tVDS tVCS 2 µs Address Setup Time Address Hold Note 2 Time Note 2 (vs.MD0↓) (vs.MD0↑) Initial Program Pulse Width tPW tPW 0.95 Additional Program Pulse Width tOPW tOPW 0.95 MD0 Setup Time (vs. MD1↑) tMOS tCES 2 MD0 ↓→ Data Output Delay Time tDV tDV MD1 Hold Time (vs. MD0↑) tM1H tOEH MD1 Recovery Time (vs. MD0↓) tM1R tOR Program Counter Reset Time tPCR µs 130 1.0 1.05 ms 21.0 ms µs 1 MD0 = MD1 = VIL ns µs 2 µs 2 µs – 10 µs tXH,tXL – 0.125 µs CLK Input Frequency fX – Initial Mode Set Time tI – 2 µs MD3 Setup Time (vs. MD1↑) tM3S – 2 µs MD3 Hold Time (vs. MD1↓) tM3H – 2 µs MD3 Setup Time (vs. MD0↓) tM3SR – When data is read from program memory 2 µs Address Note 2 → Data Output Delay Time tDAD tACC When data is read from program memory 2 µs Address Note 2 → Data Output Hold Time tHAD tOH When data is read from program memory 0 MD3 Hold Time (vs. MD0↑) tM3HR – When data is read from program memory 2 µs MD3 ↓→ Data Output Float Delay Time tDFR – When data is read from program memory 2 µs Reset Setup Time tRES 10 µs CLK Input High-/Low- Level Width tM1H + tM1R 50 µs 4.19 130 MHz ns Note 1: These symbols are the corresponding µPD27C256A symbols. 2: The internal address is incremented by 1 at the third falling edge of CLK (with four clocks constituting as one cycle). The internal address is not connected to any pin. 21 µPD17P218 PROGRAM MEMORY WRITE TIMING tRES VPP VDD tVPS VPP VDD GND VDD+1 VDD GND tVDS tXH CLK D 0 -D 7 Data output Data input tDS tOH tI tDV tXL Data input tDF tDH tAH tDS Data input tAS MD 0 tPW tM1R tM0S tOPW MD 1 tPCR tM1S tM1H MD 2 tM3H tM3S MD 3 Remarks: Broken line indicates high impedance. PROGRAM MEMORY READ TIMING tRES tVPS VPP VPP VDD GND VDD VDD+1 VDD GND tVDS tXH CLK tXL Hi-Z D 0 -D 7 MD 0 MD 1 L tPCR MD 2 tM3SR MD 3 22 Data output tDV tI tHAD tDAD Hi-Z Data output tM3HR tDFR µPD17P218 PACKAGE DRAWINGS 28 PIN PLASTIC SOP (375 mil) 28 15 1 3° +7° –3° detail of lead end 14 A H J K F G I L E 5. B C D N M M P28GM-50-375B-2 NOTE Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 18.07 MAX. 0.712 MAX. B 0.78 MAX. 0.031 MAX. C 1.27 (T.P.) 0.050 (T.P.) D 0.40 +0.10 –0.05 0.016+0.004 –0.003 E 0.1 ± 0.1 0.004 ± 0.004 F 2.9 MAX. 0.115 MAX. G 2.50 0.098 H 10.3 ± 0.3 0.406+0.012 –0.013 I 7.2 0.283 J 1.6 0.063 K 0.15 +0.10 –0.05 0.006+0.004 –0.002 L 0.8 ± 0.2 0.031 –0.008 M 0.12 0.005 N 0.15 0.006 +0.009 23 µPD17P218 28 PIN PLASTIC SHRINK DIP (400 mil) 28 15 1 14 A I K H G J L F D N M C B M R NOTES 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 2) Item "K" to center of leads when formed parallel. 24 ITEM MILLIMETERS INCHES A 28.46 MAX. 1.121 MAX. B 2.67 MAX. 0.106 MAX. C 1.778 (T.P.) 0.070 (T.P.) D 0.50±0.10 0.020 +0.004 –0.005 F 0.85 MIN. 0.033 MIN. G 3.2±0.3 0.126±0.012 H 0.51 MIN. 0.020 MIN. I 4.31 MAX. 0.170 MAX. J 5.08 MAX. 0.200 MAX. K L 10.16 (T.P.) 8.6 0.400 (T.P.) 0.339 M 0.25 +0.10 –0.05 0.010 +0.004 –0.003 N 0.17 0.007 R 0 ˜15° 0 ˜15° S28C-70-400B-1 µPD17P218 6. ★ RECOMMENDED SOLDERING CONDITIONS For the µPD17P218, soldering must be performed under the following conditions. For details of recommended conditions for surface mounting, refer to information document “Semiconductor device mounting technology manual” (IEI-1207). For other soldering methods, please consult with NEC sales personnel. Table 6-1 Soldering Conditions of Surface-Mount Type µPD17P218GT: 28-pin plastic SOP (375 mil) Soldering Method Soldering Conditions Infrared Reflow Package peak temperature: 230 ˚C, Time: 30 seconds max. (more than 210 ˚C), Number of soldering operations: 1, Maximum number of days: 3 days Note (Afterwards, 20 hours prebaking at 125 ˚C is required) Pin Partial Heating Pin temperature: 300 ˚C max., Time: 3 seconds max. (per side) Recommended Conditions Reference Code IR30-203-1 — Note: This means the number of days after unpacking the dry pack. Storage conditions are 25 ˚C and 65 % RH max. Caution: Do not use one soldering method in combination with another. (However, pin partial heating can be performed with other soldering methods.) Table 6-2 Soldering Conditions of Through-Hole Type µPD17P218CT: 28-pin plastic shrink DIP (400 mil) Soldering Method Soldering Conditions Wave Soldering (Only for lead part) Solder bath temperature: 260 ˚C max., Time: 10 seconds max. Pin Partial Heating Pin temperature: 300 ˚C max., Time: 10 seconds max. Caution: The wave soldering must be performed at the lead part only. Note that the solder must not be directly contacted to the package body. 25 µPD17P218 ★ APPENDIX A. FUNCTION OF µPD17215 SUB-SERIES PRODUCTS Product Item ROM Capacity RAM Capacity µPD17215 µPD17216 µPD17218 111 x 4 bits 223 x 4 bits Provided (without LED output) Number of I/O Ports 20 1 (rising-edge, falling-edge detection) 2 channels 8-bit modulo timer : 1 channel Basic interval timer: 1 channel Timer Watchdog Timer Provided (WDOUT output) Low-Voltage Detector Circuit Note Provided (WDOUT output) Serial Interface Stack None 5 levels (3 levels of multiplexed interrupts) Instruction Execution Time 2 µs (8-MHz ceramic oscillator: high-speed mode) 4 µs (4-MHz ceramic oscillator: high-speed mode) 16 µs (1-MHz ceramic oscillator: high-speed mode) Operation of P0C and P0D in Standby Mode Retain output level immediately before standby mode Operating Voltage Range 2.2 to 5.5 V (4 MHz, high-speed mode) Standby Function Package µPD17P218 4K bytes (2048 x 16) 8K bytes (4096 x 16) 12K bytes (6144 x 16) 16K bytes (8192 x 16) 16K bytes (8192 x 16) (mask ROM) (mask ROM) (mask ROM) (mask ROM) (one-time PROM) Infrared Remote Controller Carrier Generator Circuit (REM) External Interrupt (INT) µPD17217 STOP mode, HALT mode 28-pin plastic SOP (375 mil) 28-pin plastic shrink DIP (400 mil) Note : Although the circuit configuration of the low-voltage detection circuit is identical, its electrical specifications differ depending on the product. 26 µPD17P218 APPENDIX B. ★ DEVELOPMENT TOOLS To develop the programs for the µPD17P218, the following development tools are available: Hardware Name In-Circuit Emulator IE-17K, IE-17K-ET Note 1, EMU-17K Note 2 Remarks IE-17K, IE-17K-ET, and EMU-17K are the in-circuit emulators used in common with the 17K series microcomputer. IE-17K and IE-17K-ET are connected to a PC-9800 series or IBM PC/ATTM as the host machine with RS-232C. EMU-17K is inserted into the expansion slot of a PC-9800 series. By using these in-circuit emulators with a system evaluation board corresponding to the microcomputer, the emulators can emulate the microcomputer. A higher level debugging environment can be provided by using man-machine interface SIMPLEHOSTTM. EMU-17K also has a function by which you can check the contents of data memory realtime. SE Board (SE-17215) This is an SE board for µPD17215 sub-series. It can be used alone to evaluate a system or in combination with an in-circuit emulator for debugging. Emulation Probe (EP-17K28CT) EP-17K28CT is an emulation probe for 17K series 28-pin shrink DIP (400mil). Emulation Probe (EP-17K28GT) EP-17K28GT is an emulation probe for 17K series 28-pin SOP (375 mil). When used with EV-9500GT-28 Note 3, it connects an SE board to the target system. Conversion Adapter (EV-9500GT-28 Note 3) EV-9500GT-28 is a conversion adapter for 28-pin SOP (375 mil) and is used to connect EP-17K28GT to the target system. PROM Programmer (AF-9703 Note 4, AF-9704 Note 4, 5, AF-9706 Note 4) AF-9703, AF-9704, and AF-9706 are PROM programmers corresponding to µPD17P218. By connecting program adapter AF-9808J or AF-9808H to this PROM programmer, µPD17P218 can be programmed. Program Adapter (AF-9808JNote 4, AF-9808H Note 4) AF-9808J and AF-9808H are adapters that is used to program µPD17P218CT and µPD17P218GT respectively, and is used in combination with AF-9703, AF-9704, or AF-9706. Note 1: Low-cost model: External power supply type 2: This is a product from IC Corp. For details, consult IC Corp. 3: Two EV-9500GT-28s are supplied with the EP-17K28GT. Five EV-9500GT-28s are optionally available as a set. 4: These are products from Ando Electric. For details, consult Ando Electric. 5: Maintenance product (This is no longer produced.) 27 µPD17P218 Software Name 17K Series Assembler (AS17K) Device File AS17215 AS17216 AS17217 AS17218 Support Software (SIMPLEHOST) Outline OS Media Host Machine AS17K is an assembler that can be used in common with the 17K series products. When developing the program of the µPD17P218, AS17K is used in combination with a device file (AS17215, AS17216, AS17217, or AS17218). PC-9800 series MS-DOS PC DOS IBM PC/AT PC-9800 series AS17215, AS17216, AS17217, and AS17218 are device files for µPD17215, 17216, 17217, and 17218 respectirely, and are used in combination with an assembler for the 17K series (AS17K). SIMPLEHOST is a software package that enables manmachine interface on the WindowsTM when a program is developed by using an incircuit emulator and a personal computer. µS5A10AS17K 3.5" 2HD µS5A13AS17K 5" 2HC µS7B10AS17K 3.5" 2HC µS7B13AS17K 5" 2HD µS5A10AS17215 Note 3.5" 2HD µS5A13AS17215 Note 5" 2HC µS7B10AS17215 Note 3.5" 2HC µS7B13AS17215 Note 5" 2HD µS5A10IE17K 3.5" 2HD µS5A13IE17K 5" 2HC µS7B10IE17K 3.5" 2HC µS7B13IE17K TM PC DOS MS-DOS Windows IBM PC/AT PC DOS Remarks: The corresponding OS versions are as follows: OS Version Note MS-DOS Ver. 3.30 to Ver. 5.00A PC DOS Ver. 3.1 to Ver. 5.0 Note Windows Ver. 3.0 to Ver. 3.1 Note: Ver. 5.00/5.00A of MS-DOS and Ver. 5.0 of PC DOS have a task swap function, but this function cannot be used with 28 5" 2HD TM Note: µS××××AS17215 includes AS17215, AS17216, AS17217, and AS17218. this software. Order Code MS-DOS IBM PC/AT PC-9800 series Supply µPD17P218 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 29 µPD17P218 [MEMO] No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment, Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. Special: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime systems, etc. M4 92.6 SIMPLEHOST is a trademark of NEC Corporation. MS-DOS and Windows are trademarks of Microsoft Corporation. PC/AT and PC DOS are trademarks of IBM Corporation.