NEC UPD3753CY-A

DATA SHEET
MOS INTEGRATED CIRCUIT
µ PD3753
2088 PIXELS CCD LINEAR IMAGE SENSOR WITH PERIPHERAL CIRCUIT
DESCRIPTION
The µ PD3753 is a 2088-pixel high sensitivity CCD (Charge Coupled Device) linear image sensor which changes
optical images to electrical signal.
The µ PD3753 consists of 2088-pixels photocell array and a line of 2088-pixel CCD charge transferred register. It
contains a reset a feed-through level clamp circuit, a reset pulse generator, a clamp pulse generator, and a voltage
amplifier to provide high sensitivity and low noise. It also supports low power consumption with single 5 V power
supply. The µ PD3753 can be driven by power supply and three input clocks owing to the on-chip reset pulse
generator and a clamp pulse generator.
FEATURES
• Valid photocell
: 2088 pixels
• Photocell pitch
: 14 µ m
• Peak response wavelength : 550 nm (green)
• Resolution
: 8 dot/mm B4 (257 × 364 mm) size (shorter side)
• High response sensitivity
• Low noise
• Drive clock level
: CMOS output under +5 V operation
• Data rate
: 2 MHz Max.
• Power supply
: +5 V
• On-chip circuits
: Reset feed-through level clamp circuit
Reset pulse generator
Clamp pulse generator
Voltage amplifier
ORDERING INFORMATION
<R>
Part Number
Package
µ PD3753CY-A
CCD linear image sensor 22-pin plastic DIP (10.16 mm (400))
Remark
The µ PD3753CY-A is a lead-free product.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. S16546EJ2V0DS00 (2nd edition)
Date Published February 2006 NS CP (N)
Printed in Japan
1994
The mark <R> shows major revised points.
The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field.
µ PD3753
BLOCK DIAGRAM
VOD
3
Reset pulse/
clamp pulse
generator
VOUT 19
Voltage amplifier
Reset feed-through
level clamp circuit
15 φ 2
Optical black 18 pixels, invalid photocell 2 pixels,
valid photocell 2088 pixels, invalid photocell 2 pixels
9
φTG
CCD register
14 φ 1
2
20
13
AGND
DGND
Data Sheet S16546EJ2V0DS
µ PD3753
PIN CONFIGURATION (Top View)
CCD linear image sensor 22-pin plastic DIP (10.16 mm (400))
• µ PD3753CY-A
No connection
1
NC
NC
22
No connection
No connection
2
NC
NC
21
No connection
Output drain voltage
3
VOD
AGND
20
Analog ground
No connection
4
NC
VOUT
19
Output
No connection
5
NC
NC
18
No connection
No connection
6
NC
NC
17
No connection
No connection
7
NC
NC
16
No connection
No connection
8
NC
φ2
15
Shift register clock 2
Transfer gate clock
9
φ TG
φ1
14
Shift register clock 1
No connection
10
NC
DGND
13
Digital ground
No connection
11
NC
NC
12
No connection
Caution Connect the No connection pins (NC) to GND.
PHOTOCELL STRUCTURE DIAGRAM
2 µm
14 µ m
12 µ m
Channel stopper
Aluminum
shield
Data Sheet S16546EJ2V0DS
3
µ PD3753
ABSOLUTE MAXIMUM RATINGS (TA = +25°C)
Parameter
Symbol
Ratings
Unit
Output drain voltage
VOD
−0.3 to +8
V
Shift register clock voltage
Vφ 1, Vφ 2
−0.3 to +8
V
Vφ TG
−0.3 to +8
V
TA
−25 to +60
°C
Tstg
−40 to +70
°C
Transfer gate clock voltage
Operating ambient temperature
Storage temperature
Note
Note Use at the condition without dew condensation.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
RECOMMENDED OPERATING CONDITIONS (TA = +25°C)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Output drain voltage
VOD
4.7
5.0
5.3
V
Shift register clock high level
Vφ 1_H, Vφ 2_H
4.5
5.0
VOD +0.2
V
Shift register clock low level
Vφ 1_L, Vφ 2_L
−0.3
0
+0.5
V
Note
Vφ 1_H
Note
Transfer gate clock high level
Vφ TGH
4.5
Vφ 1_H
V
Transfer gate clock low level
Vφ TGL
−0.3
0
+0.5
V
Data rate
fφ R
0.2
1
2
MHz
Note When Transfer gate clock high level (Vφ TGH) is higher than Shift register clock high level (Vφ 1_H), Image lag
can increase.
4
Data Sheet S16546EJ2V0DS
µ PD3753
ELECTRICAL CHARACTERISTICS
TA = +25°C, VOD = 5 V, fφ 1 = 1 MHz, data rate = 1 MHz, storage time = 10 ms, input signal clock = 5 Vp-p,
light source : 3200 K halogen lamp + C500 (infrared cut filter)
Parameter
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
1.0
1.2
−
V
Saturation voltage
Vsat
Saturation exposure
SE
Daylight color fluorescent lamp
−
0.013
−
lx•s
Photo response non-uniformity
PRNU
VOUT = 500 mV
−
±2
±8
%
Average dark signal
ADS
Light shielding
−
1.0
8.0
mV
Dark signal non-uniformity
DSNU
Light shielding
−8
±4
+8
mV
Power consumption
PW
−
30
50
mW
Output impedance
ZO
−
0.5
1
kΩ
Response
RF
63
90
117
V/lx•s
−
550
−
nm
−
7
14
%
2.5
3.0
3.5
V
Daylight color fluorescent lamp
Response peak
Image lag
Offset level
IL
Note
VOUT = 1.0 V
VOS
Note
td
VOUT = 500 mV, t1, t2 = 50 ns
−
130
−
ns
TTE
VOUT = 1.0 V, data rate = 2 MHz
92
98
−
%
DR
Vsat/DSNU
−
375
−
times
RFTN
Light shielding
0
800
1500
mV
Bit noise
BN
Light shielding
−
10
−
mVp-p
Resolution
MTF
Modulation transfer function at
−
65
−
%
Output fall delay time
Total transfer efficiency
Dynamic range
Reset feed-through noise
Note
nyquist frequency
Note Refer to TIMING CHART 2.
Remark When VOD = 4.7 V, the response typically decreases to 90% of the value under 5 V operation.
INPUT PIN CAPACITANCE (TA = +25°C, VOD = 5 V)
Parameter
Symbol
Pin name
Pin No.
Min.
Typ.
Max.
Unit
Shift register clock pin capacitance 1
Cφ 1
φ1
14
−
300
−
pF
Shift register clock pin capacitance 2
Cφ 2
φ2
15
−
300
−
pF
Transfer gate clock pin capacitance
Cφ TG
φ TG
9
−
100
−
pF
Data Sheet S16546EJ2V0DS
5
µ PD3753
TIMING CHART 1
2124
2123
2122
2121
2120
2119
2118
37
36
35
34
33
32
31
16
15
14
13
12
5
4
3
2
φ1
1
φ TG
φ2
VOUT
VOUT unstable period *
(12 pixels)
Optical black
(18 pixels)
Valid photocell
(2088 pixels)
Invalid photocell
(2 pixels)
Invalid photocell
(2 pixels)
Caution Be sure not to use this period (indicated by *) as the black level, because this part is unstable.
TIMING CHART 2
t1
t2
90%
φ1
φ2
10%
90%
10%
td
VOUT
10%
Remark
: Signal output
Symbol
t1, t2
Min.
Typ.
Max.
Unit
0
50
(100)
ns
Remark The MAX. in the table above shows the operation range in which the output characteristics are kept
almost enough for general purpose, does not show the limit above which the µ PD3753 is destroyed.
6
Data Sheet S16546EJ2V0DS
µ PD3753
φ TG, φ 1, φ 2 TIMING CHART
t3
t5
t4
90%
10%
φTG
t7
t6
90%
φ1
φ2
Symbol
t3, t4
t5
t6, t7
Min.
Typ.
Max.
Unit
0
50
−
ns
650
1000
(2000)
ns
0
100
−
ns
Remark The MAX. in the table above shows the operation range in which the output characteristics are kept
almost enough for general purpose, does not show the limit above which the µ PD3753 is destroyed.
φ 1, φ 2 cross points
φ1
φ2
2.0 V or more
2.0 V or more
Remark Adjust cross points φ 1, φ 2 with input resistance of each pin.
Data Sheet S16546EJ2V0DS
7
µ PD3753
DEFINITIONS OF CHARACTERISTIC ITEMS
1. Saturation voltage : Vsat
Output signal voltage at which the response linearity is lost.
2. Saturation exposure : SE
Product of intensity of illumination (lx) and storage time (s) when saturation of output voltage occurs.
3. Photo response non-uniformity : PRNU
The peak/bottom ratio to the average output voltage of all the valid pixels calculated by the following formula.
VMAX. or VMIN.
PRNU (%) =
n
ΣV
1
n
−1
j
× 100
j=1
n : Number of valid pixcels
Vj : Output voltage of each pixel
VMIN.
Register Dark
DC level
VMAX.
1
n
n
ΣV
j
j=1
4. Average dark signal : ADS
Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following
formula.
2088
Σd
j
ADS (mV) =
j=1
2088
dj : Dark signal of valid pixel number j
5. Dark signal non-uniformity : DSNU
The difference between ADS and voltage of the highest or lowest output pixel of all the valid pixels at light
shielding.
VOUT
ADS
Register Dark
DC level
DSNU MIN.
DSNU MAX.
8
Data Sheet S16546EJ2V0DS
µ PD3753
6. Output impedance : ZO
Impedance of the output pins viewed from outside.
7. Response : R
Output voltage divided by exposure (lx•s).
Note that the response varies with a light source (spectral characteristic).
8. Image lag : IL
The rate between the last output voltage and the next one after read out the data of a line.
φ TG
Light
ON
OFF
VOUT
V1
VOUT
IL (%) =
V1
× 100
VOUT
9. Bit Noise : BN
Output signal distribution of a photocell by scan.
Data Sheet S16546EJ2V0DS
9
µ PD3753
STANDARD CHARACTERISTIC CURVES (Reference Value)
DARK OUTPUT TEMPERATURE
CHARACTERISTIC
STORAGE TIME OUTPUT VOLTAGE
CHARACTERISTIC (TA = +25°C)
8
2
2
1
0.5
0.2
0.25
0.1
0
1
Relative Output Voltage
Relative Output Voltage
4
10
20
30
40
0.1
50
Operating Ambient Temperature TA (°C)
1
5
10
Storage Time (ms)
TOTAL SPECTRAL RESPONSE CHARACTERISTICS (without infrared cut filter) (TA = +25°C)
100
Response Ratio (%)
80
60
40
20
0
400
600
800
Wavelength (nm)
10
Data Sheet S16546EJ2V0DS
1000
1200
µ PD3753
POWER SUPPLY VOLTAGE RESPONSE RATIO CHARACTERISTIC
110
Response Ratio (%)
100
90
0
4.5
4.7
5.0
5.3
5.5
Power Supply Voltage (V)
Data Sheet S16546EJ2V0DS
11
µ PD3753
APPLICATION CIRCUIT EXAMPLE
+5 V
+5 V
10 Ω
10 µF/16 V
10 µF/16 V
+
+
0.1 µ F
0.1 µ F
µ PD3753CY
74HC04
1
NC
NC 22
2
NC
NC 21
3
VOD
AGND 20
2.2 kΩ
VOUT
100 Ω
4
NC
VOUT 19
5
NC
NC 18
6
NC
NC 17
7
NC
NC 16
8
NC
φ 2 15
9
φ TG
φ 1 14
2SA1005
100 Ω
φ1
φ2
φ TG
10 Ω
10 NC
DGND 13
11 NC
NC 12
Caution Connect the No connection pins (NC) to GND.
12
Data Sheet S16546EJ2V0DS
47 Ω
47 Ω
µ PD3753
PACKAGE DRAWING
µ PD3753CY
CCD LINEAR IMAGE SENSOR 22-PIN PLASTIC DIP (10.16 mm (400) )
(Unit : mm)
44.0±0.3
1st valid pixel
1.7±0.3
1
9.25±0.3
22
12
1
11
2.0
37.5
1.02±0.15
0.46±0.1
4.39±0.4
2.54±0.25
(5.42)
(1.99)
2
2.35±0.2
3
10.16±0.2
0.25±0.05
10.16 +0.7
−0.2
4.21±0.5
Name
Dimensions
Refractive index
Plastic cap
42.9×8.35×0.7
1.5
1 1st valid pixel
The center of the pin1
2 The surface of the CCD chip
The top of the cap
3 The bottom of the package
The surface of the CCD chip
22C-1CCD-PKG15-1
Data Sheet S16546EJ2V0DS
13
µ PD3753
RECOMMENDED SOLDERING CONDITIONS
When soldering this product, it is highly recommended to observe the conditions as shown below.
If other soldering processes are used, or if the soldering is performed under different conditions, please make sure
to consult with our sales offices.
Type of Through-hole Device
µ PD3753CY-A : CCD linear image sensor 22-pin plastic DIP (10.16 mm (400))
Process
Partial heating method
Cautions 1.
Conditions
Pin temperature : 300 °C or below, Heat time : 3 seconds or less (per pin)
During assembly care should be taken to prevent solder or flux from contacting the plastic
cap. The optical characteristics could be degraded by such contact.
2.
Soldering by the solder flow method may have deleterious effects on prevention of plastic
cap soiling and heat resistance. So the method cannot be guaranteed.
14
Data Sheet S16546EJ2V0DS
µ PD3753
NOTES ON HANDLING THE PACKAGES
1 DUST AND DIRT PROTECTING
The optical characteristics of the CCD will be degraded if the cap is scratched during cleaning. Don’t either
touch plastic cap surface by hand or have any object come in contact with plastic cap surface. Should dirt
stick to a plastic cap surface, blow it off with an air blower. For dirt stuck through electricity ionized air is
recommended. And if the plastic cap surface is grease stained, clean with our recommended solvents.
CLEANING THE PLASTIC CAP
Care should be taken when cleaning the surface to prevent scratches.
We recommend cleaning the cap with a soft cloth moistened with one of the recommended solvents below.
Excessive pressure should not be applied to the cap during cleaning. If the cap requires multiple cleanings it is
recommended that a clean surface or cloth be used.
RECOMMENDED SOLVENTS
The following are the recommended solvents for cleaning the CCD plastic cap.
Use of solvents other than these could result in optical or physical degradation in the plastic cap.
Please consult your sales office when considering an alternative solvent.
Solvents
Ethyl Alcohol
Methyl Alcohol
Isopropyl Alcohol
N-methyl Pyrrolidone
Symbol
EtOH
MeOH
IPA
NMP
2 MOUNTING OF THE PACKAGE
The application of an excessive load to the package may cause the package to warp or break, or cause chips
to come off internally. Particular care should be taken when mounting the package on the circuit board. Don't
have any object come in contact with plastic cap. You should not reform the lead frame. We recommended to
use a IC-inserter when you assemble to PCB.
Also, be care that the any of the following can cause the package to crack or dust to be generated.
1. Applying heat to the external leads for an extended period of time with soldering iron.
2. Applying repetitive bending stress to the external leads.
3. Rapid cooling or heating
3 OPERATE AND STORAGE ENVIRONMENTS
Operate in clean environments. CCD image sensors are precise optical equipment that should not be subject
to mechanical shocks. Exposure to high temperatures or humidity will affect the characteristics. So avoid
storage or usage in such conditions.
Keep in a case to protect from dust and dirt. Dew condensation may occur on CCD image sensors when the
devices are transported from a low-temperature environment to a high-temperature environment. Avoid such
rapid temperature changes.
For more details, refer to our document "Review of Quality and Reliability Handbook" (C12769E)
4 ELECTROSTATIC BREAKDOWN
CCD image sensor is protected against static electricity, but destruction due to static electricity is sometimes
detected. Before handling be sure to take the following protective measures.
1.
2.
3.
4.
5.
6.
Ground the tools such as soldering iron, radio cutting pliers of or pincer.
Install a conductive mat or on the floor or working table to prevent the generation of static electricity.
Either handle bare handed or use non-chargeable gloves, clothes or material.
Ionized air is recommended for discharge when handling CCD image sensor.
For the shipment of mounted substrates, use box treated for prevention of static charges.
Anyone who is handling CCD image sensors, mounting them on PCBs or testing or inspecting PCBs on
which CCD image sensors have been mounted must wear anti-static bands such as wrist straps and ankle
straps which are grounded via a series resistance connection of about 1 MΩ.
Data Sheet S16546EJ2V0DS
15
µ PD3753
[MEMO]
16
Data Sheet S16546EJ2V0DS
µ PD3753
[MEMO]
Data Sheet S16546EJ2V0DS
17
µ PD3753
[MEMO]
18
Data Sheet S16546EJ2V0DS
µ PD3753
NOTES FOR CMOS DEVICES
1
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between VIL (MAX) and
VIH (MIN).
2
HANDLING OF UNUSED INPUT PINS
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred.
Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded.
The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
Data Sheet S16546EJ2V0DS
19
µ PD3753
• The information in this document is current as of February, 2006. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
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written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
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M8E 02. 11-1