DATA SHEET MOS INTEGRATED CIRCUIT µ PD3728DZ 7300 PIXELS × 3 COLOR CCD LINEAR IMAGE SENSOR DESCRIPTION The µ PD3728DZ is a high-speed and high sensitive color CCD (Charge Coupled Device) linear image sensor which changes optical images to electrical signal and has the function of color separation. The µ PD3728DZ has 3 rows of 7300 pixels, and it is a 2-output/color type CCD sensor with 2 rows/color of charge transfer register, which transfers the photo signal electrons of 7300 pixels separately in odd and even pixels. Therefore, it is suitable for 600 dpi/A3 high-speed color digital copiers and so on. FEATURES • Valid photocell : 7300 pixels × 3 • Photocell pitch : 10 µ m • Line spacing : 40 µ m (4 lines) Red line - Green line, Green line - Blue line • Color filter : Primary colors (red, green and blue), pigment filter (with light resistance 10 lx•hour) • Resolution : 24 dot/mm A3 (297 × 420 mm) size (shorter side) 7 • Drive clock level : CMOS output under 5 V operation • Data rate : 40 MHz MAX. (20 MHz/1 output) • Output type : 2 outputs in phase/color • Power supply : +12 V • On-chip circuits : Reset feed-through level clamp circuits Voltage amplifiers ORDERING INFORMATION Part Number Package µ PD3728DZ CCD linear image sensor 36-pin ceramic DIP (CERDIP) (15.24 mm (600)) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S15417EJ2V0DS00 (2nd edition) Date Published October 2002 NS CP (K) Printed in Japan The mark shows major revised points. 2001 µ PD3728DZ BLOCK DIAGRAM 23 24 VOUT5 (Red, odd) 5 GND 6 2 ..... D134 4 Photocell (Green) 21 φ TG2 (Green) 15 φ TG3 (Red) CCD analog shift register Transfer gate ..... D128 GND φ TG1 (Blue) D134 ..... D128 D27 3 ..... 22 Transfer gate CCD analog shift register D27 VOUT6 (Red, even) ..... CCD analog shift register Transfer gate VOUT4 1 (Green, even) 2 (Blue) Transfer gate CCD analog shift register VOUT3 36 (Green, odd) GND Photocell D134 ..... D129 CCD analog shift register Transfer gate D129 35 16 D129 GND 28 S7299 S7300 34 29 S7299 S7300 VOUT1 (Blue, odd) 30 Photocell (Red) S7299 S7300 33 φ2 S1 S2 GND φ1 D128 32 GND S1 S2 VOUT2 (Blue, even) φ 20 S1 S2 31 φ 1L D27 GND φ CLB Transfer gate CCD analog shift register 7 8 9 13 14 VOD φ RB φ10 φ1 φ2 Data Sheet S15417EJ2V0DS µ PD3728DZ PIN CONFIGURATION (Top View) CCD linear image sensor 36-pin ceramic DIP (CERDIP) (15.24 mm (600)) • µ PD3728DZ Output signal 3 (Green, odd) GND 2 35 GND Ground Output signal 6 (Red, even) VOUT6 3 34 VOUT1 Output signal 1 (Blue, odd) Ground GND 4 33 GND Ground Output signal 5 (Red, odd) VOUT5 5 32 VOUT2 Output signal 2 (Blue, even) Ground 6 31 GND Ground Output drain voltage VOD 7 30 φ CLB Reset feed-through level clamp clock Reset gate clock φ RB 8 29 φ 1L Last stage shift register clock 1 Shift register clock 10 φ 10 9 28 φ 20 Shift register clock 20 No connection NC 10 27 NC No connection No connection NC 11 26 NC No connection No connection NC 12 25 NC No connection Shift register clock 1 φ1 13 24 φ2 Shift register clock 2 Shift register clock 2 φ2 14 23 φ1 Shift register clock 1 Transfer gate clock 3 (for Red) φ TG3 15 22 φ TG1 Transfer gate clock 1 (for Blue) 21 φ TG2 Transfer gate clock 2 (for Green) 7300 7300 7300 Blue GND Green Ground Red Caution 1 VOUT3 1 36 1 1 Output signal 4 (Green, even) VOUT4 Ground GND 16 No connection NC 17 20 NC No connection No connection NC 18 19 NC No connection Connect the No connection pins (NC) to GND. PHOTOCELL STRUCTURE DIAGRAM PHOTOCELL ARRAY STRUCTURE DIAGRAM (Line spacing) 10 µm 10 µ m 7 µm Blue photocell array 3 µm 4 lines (40 µm) Channel stopper 10 µm Green photocell array 4 lines (40 µm) Aluminum shield 10 µm Data Sheet S15417EJ2V0DS Red photocell array 3 µ PD3728DZ ABSOLUTE MAXIMUM RATINGS (TA = +25°°C) Parameter Symbol Ratings Unit Output drain voltage VOD −0.3 to +15 V Shift register clock voltage Vφ 1, Vφ 1L, Vφ 10, Vφ 2, Vφ 20 −0.3 to +8 V Reset gate clock voltage Vφ RB −0.3 to +8 V Reset feed-through level clamp clock voltage Vφ CLB −0.3 to +8 V Transfer gate clock voltage Vφ TG1 to Vφ TG3 −0.3 to +8 V Note Operating ambient temperature TA −25 to +60 °C Storage temperature Tstg −40 to +100 °C Note Use at the condition without dew condensation. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. RECOMMENDED OPERATING CONDITIONS (TA = +25°°C) Min. Typ. Max. Unit Output drain voltage Parameter VOD Symbol 11.4 12.0 12.6 V Shift register clock high level Vφ 1H, Vφ 1LH, Vφ 10H, Vφ 2H, Vφ 20H 4.5 5.0 5.5 V Shift register clock low level Vφ 1L, Vφ 1LL, Vφ 10L, Vφ 2L, Vφ 20L −0.3 0 +0.5 V Reset gate clock high level Vφ RBH 4.5 5.0 5.5 V Reset gate clock low level Vφ RBL −0.3 0 +0.5 V Reset feed-through level clamp clock high level Vφ CLBH 4.5 5.0 5.5 V Reset feed-through level clamp clock low level Vφ CLBL −0.3 0 +0.5 V Transfer gate clock high level Vφ TG1H to Vφ TG3H 4.5 Vφ 1H Vφ 1H (Vφ 10H) (Vφ 10H) −0.3 0 +0.5 V − 2 40 MHz Transfer gate clock low level Vφ TG1L to Vφ TG3L Data rate 2fφ RB Note Note V Note When Transfer gate clock high level (Vφ TG1H to Vφ TG3H) is higher than Shift register clock high level (Vφ 1H (Vφ 10H)), Image lag can increase. Remark Pin 9 ( φ 10) and pin 28 ( φ 20) should be open to decrease the influence of input clock noise to output signal waveform, in case of operating at low or middle speed range; data rate under 24 MHz or so. 4 Data Sheet S15417EJ2V0DS µ PD3728DZ ELECTRICAL CHARACTERISTICS TA = +25°C, VOD = 12 V, fφ RB = 1 MHz, data rate = 2 MHz, storage time = 10 ms, input signal clock = 5 Vp-p, light source: 3200 K halogen lamp +C-500S (infrared cut filter, t = 1 mm)+HA-50 (heat absorbing filter, t = 3 mm) Parameter Symbol Min. Typ. Max. Unit Vsat 1.5 2.0 − V Red SER − 0.35 − lx•s Green SEG − 0.39 − lx•s Blue SEB − 0.31 − lx•s Saturation voltage Saturation exposure Test Conditions PRNU VOUT = 1.0 V − 6.0 18.0 % ADS1 Light shielding − 1.0 5.0 mV − 0.5 5.0 mV − 2.0 5.0 mV DSNU2 − 1.0 5.0 mV Power consumption PW − 600 800 mW Output impedance ZO − 0.3 0.5 kΩ Red RR 3.9 5.6 7.3 V/lx•s Green RG 3.6 5.1 6.6 V/lx•s 4.5 6.4 8.3 V/lx•s − 2.0 5.0 % IL2 − 1.0 5.0 % VOS 4.0 5.0 6.0 V Photo response non-uniformity Average dark signal Note1 ADS2 Dark signal non-uniformity Response Note1 Blue Image lag Note1 Offset level DSNU1 RB IL1 Note2 Note3 Light shielding VOUT = 1.0 V td VOUT = 1.0 V − 20 − ns Register imbalance RI VOUT = 1.0 V 0 − 4.0 % Total transfer efficiency TTE VOUT = 1.0 V, data rate = 40 MHz 95 98 − % Red − 630 − nm Green − 540 − nm Blue − 460 − nm Output fall delay time Response peak Dynamic range Note1 Reset feed-through noise Random noise Note1 Note2 DR11 Vsat/DSNU1 − 1000 − times DR12 Vsat/DSNU2 − 2000 − times DR21 Vsat/σ bit1 − 2000 − times DR22 Vsat/σ bit2 − 4000 − times RFTN Light shielding −500 +200 +500 mV σ bit1 Light shielding, − 1.0 − mV σ bit2 bit clamp mode (tcp = 150 ns) − 0.5 − mV σ line1 Light shielding, − 4.0 − mV σ line2 line clamp mode (t19 = 3 µ s) − 2.0 − mV Notes 1. ADS1, DSNU1, IL1, DR11, DR21, σ bit1 and σ line1 show the specification of VOUT1 and VOUT2. ADS2, DSNU2, IL2, DR12, DR22, σ bit2 and σ line2 show the specification of VOUT3 to VOUT6. 2. Refer to TIMING CHART 2, 5. 3. When the fall time of φ 1L (t2’) is the TYP. value (refer to TIMING CHART 2, 5). Data Sheet S15417EJ2V0DS 5 µ PD3728DZ INPUT PIN CAPACITANCE (TA = +25°°C, VOD = 12 V) Parameter Symbol Shift register clock pin capacitance 1 Cφ 1 Shift register clock pin capacitance 2 Cφ 2 Pin name φ1 Pin No. Min. Typ. Max. Unit 13 − 350 500 pF 23 − 350 500 pF φ 10 9 − 350 500 pF φ2 14 − 350 500 pF 24 − 350 500 pF φ 20 28 − 350 500 pF Last stage shift register clock pin capacitance Cφ L φ 1L 29 − 10 − pF Reset gate clock pin capacitance Cφ RB φ RB 8 − 10 − pF Reset feed-through level clamp clock pin capacitance Cφ CLB φ CLB 30 − 10 − pF Transfer gate clock pin capacitance Cφ TG φ TG1 22 − 100 − pF φ TG2 21 − 100 − pF φ TG3 15 − 100 − pF Remark Pins 13, 23 (φ 1) and pin 9 (φ 10) are connected each other inside of the device. Pins 14, 24 (φ 2) and pin 28 (φ 20) are connected each other inside of the device. 6 Data Sheet S15417EJ2V0DS TIMING CHART 1 (Bit clamp mode, for each color) φ TG1 to φ TG3 φ 1 ( φ 10) φ 2 ( φ 20) φ 1L φ RB 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 119 121 123 125 127 129 131 7425 7427 7429 7431 7433 7435 7437 120 122 124 126 128 130 132 7426 7428 7430 7432 7434 7436 7438 Note 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 Data Sheet S15417EJ2V0DS φ CLB Note VOUT1, 3, 5 VOUT2, 4, 6 Optical black (96 pixels) Note Input the φ RB and φ CLB pulses continuously during this period, too. Invalid photocell (6 pixels) 7 µ PD3728DZ Invaid photocell (6 pixels) Valid photocell (7300 pixels) µ PD3728DZ TIMING CHART 2 (Bit clamp mode, for each color) t1 φ 1 ( φ 10) φ 2 ( φ 20) φ 1L t2 90% 10% 90% 10% 90% 10% t5 φ RB t4 t6 t1' 90% t2' t3 tcp t10 t8 10% t11 t7 90% φ CLB t9 10% td VOUT1 to VOUT6 RFTN VOS 10% Symbol Min. Typ. Max. Unit t1, t2 0 50 − ns t1’, t2’ 0 5 − ns t3 17 50 − ns t4 5 200 − ns t5, t6 0 20 − ns t7 17 150 − ns t8, t9 0 20 − ns t10 t11 −10 −5 tcp Note 1 +50 − ns Note 2 +50 − ns 5 150 − ns Notes 1. Min. of t10 shows that the φ RB and φ CLB overlap each other. 90% φ RB φ CLB 90% t10 2. Min. of t11 shows that the φ 1L and φ CLB overlap each other. φ 1L φ CLB 8 90% t11 Data Sheet S15417EJ2V0DS 90% µ PD3728DZ TIMING CHART 3 (Bit clamp, for each color) t13 t12 t14 90% 10% φ TG1 to φ TG3 t15 t16 90% φ 1 ( φ 10) φ 2 ( φ 20) φ 1L 90% φ RB t11 90% φ CLB Note1 Symbol t11 t12 Min. −5 Note 2 3000 Typ. Max. Unit +50 − ns 10000 − ns t13, t14 0 50 − ns t15, t16 900 1000 − ns Notes 1. Input the φ RB and φ CLB pulses continuously during this period, too. 2. Min. of t11 shows that the φ 1L and φ CLB overlap each other. φ 1L φ CLB 90% t11 Data Sheet S15417EJ2V0DS 90% 9 µ PD3728DZ φ 1, φ 2 and φ 10, φ 20 cross points φ1 φ2 2 V or more 2 V or more 2 V or more 2 V or more φ 10 φ 20 φ 1L, φ 20 cross points φ 20 φ 1L 2 V or more 0.5 V or more Remark Adjust cross points (φ 1, φ 2), (φ 10, φ 20) and (φ 1L, φ 20) with input resistance of each pin. 10 Data Sheet S15417EJ2V0DS TIMING CHART 4 (Line clamp mode, for each color) φ TG1- φ TG3 φ 1 ( φ 10) φ 2 ( φ 20) φ 1L φ RB 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 119 121 123 125 127 129 131 7425 7427 7429 7431 7433 7435 7437 120 122 124 126 128 130 132 7426 7428 7430 7432 7434 7436 7438 Note 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 Data Sheet S15417EJ2V0DS φ CLB Note VOUT1, 3, 5 VOUT2, 4, 6 Optical black (96 pixels) Note Set the φ RB pulse to high level during this period. 11 Remark Inverse pulse of φ TG1 to φ TG3 can be used as φ CLB. Invalid photocell (6 pixels) µ PD3728DZ Invalid photocell (6 pixels) Valid photocell (7300 pixels) µ PD3728DZ TIMING CHART 5 (Line clamp mode, for each color) t1 t2 90% φ 1 ( φ 10) 10% 90% φ 2 ( φ 20) 10% 90% φ 1L 10% t5 t1' 90% φ RB t4 t6 t2' t3 10% φ CLB "H" td VOUT1 to VOUT6 RFTN VOS 10% Symbol 12 Min. Typ. Max. Unit t1, t2 0 50 − ns t1’, t2’ 0 5 − ns t3 17 50 − ns t4 5 200 − ns t5, t6 5 20 − ns Data Sheet S15417EJ2V0DS µ PD3728DZ TIMING CHART 6 (Line clamp mode, for each color) t13 t12 t14 90% 10% φ TG1 to φ TG3 t15 t16 90% φ 1 ( φ 10) φ 2 ( φ 20) 90% φ 1L Note φ RB t17 t18 90% 10% t20 φ CLB Symbol t21 t19 Min. Typ. Max. Unit 3000 10000 − ns t13, t14 0 50 − ns t15, t16 900 1000 − ns t17, t18 100 1000 − ns t19 200 t12 − ns 0 20 − ns t12 t20, t21 Note Set the φ RB pulse to high level during this period. Remark Inverse pulse of the φ TG1 and φ TG3 can be used as φ CLB. φ 1, φ 2, and φ 10,φ 20 cross points φ1 φ2 2 V or more 2 V or more 2 V or more 2 V or more φ 10 φ 20 φ 1L, φ 20 cross points φ 20 φ 1L 2 V or more 0.5 V or more Remark Adjust cross points (φ 1, φ 2), (φ 10, φ 20) and (φ 1L, φ 20) with input resistance of each pin. Data Sheet S15417EJ2V0DS 13 µ PD3728DZ DEFINITIONS OF CHARACTERISTIC ITEMS 1. Saturation voltage : Vsat Output signal voltage at which the response linearity is lost. 2. Saturation exposure : SE Product of intensity of illumination (lx) and storage time (s) when saturation of output voltage occurs. 3. Photo response non-uniformity : PRNU The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of uniform illumination. This is calculated by the following formula. PRNU (%) = ∆x × 100 x ∆ x : maximum of xj − x 7300 Σx x= j j=1 7300 xj : Output voltage of valid pixel number j VOUT Register Dark DC level x ∆x 4. Average dark signal : ADS Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula. 7300 Σd ADS (mV) = j j=1 7300 dj : Dark signal of valid pixel number j 14 Data Sheet S15417EJ2V0DS µ PD3728DZ 5. Dark signal non-uniformity : DSNU Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. This is calculated by the following formula. DSNU (mV) : maximum of dj − ADS j = 1 to 7300 dj : Dark signal of valid pixel number j VOUT ADS Register Dark DC level DSNU 6. Output impedance : ZO Impedance of the output pins viewed from outside. 7. Response : R Output voltage divided by exposure (lx•s). Note that the response varies with a light source (spectral characteristic). 8. Image lag : IL The rate between the last output voltage and the next one after read out the data of a line. φ TG Light ON OFF VOUT V1 VOUT IL (%) = V1 × 100 VOUT Data Sheet S15417EJ2V0DS 15 µ PD3728DZ 9. Register imbalance : RI The rate of the difference between the averages of the output voltage of Odd and Even pixels, against the average output voltage of all the valid pixels. This is calculated by the following formula. n 2 2 n ∑ (V2j –1 – V2j) j=1 RI (%) = × 100 n 1 n ∑ Vj j=1 n : Number of valid pixels Vj : Output voltage of each pixel 10. Total transfer efficiency : TTE The total transfer rate of CCD analog shift register. This is calculated by the following formula, it is defined by each output. TTE (%) = (1 − Vb / average output of all the valid pixels) × 100 Va−1 : The last pixel output − 1 (Odd pixel: 7431st pixel) Vb Va : The last pixel output (Odd pixel: 7433rd pixel) Vb : The spilt pixel output (Odd pixel: 7435th pixel) Va Va−1 11. Random noise : σ Random noise is defined as the standard deviation of a valid pixel output signal with 100 times (=100 lines) data sampling at dark (light shielding). This is calculated by the following formula. 100 σ (mV) = Σ (V – V) i 2 , V= i=1 100 1 100 ΣV i 100 i = 1 Vi : A valid pixel output signal among all of the valid pixels for each color VOUT V1 line 1 V2 line 2 … … V100 line 100 This is measured by the DC level sampling of only the signal level, not by CDS (Correlated Double Sampling). 16 Data Sheet S15417EJ2V0DS µ PD3728DZ STANDARD CHARACTERISTIC CURVES (Reference Value) DARK OUTPUT TEMPERATURE CHARACTERISTIC STORAGE TIME OUTPUT VOLTAGE CHARACTERISTIC (TA = +25°C) 8 2 1 Relative Output Voltage 2 1 0.5 0.2 0.25 0.1 0 10 20 30 40 0.1 50 Operating Ambient Temperature TA (°C) 1 5 10 Storage Time (ms) TOTAL SPECTRAL RESPONSE CHARACTERISTICS (without infrared cut filter and heat absorbing filter) (TA = +25°C) 100 B 80 R Response Ratio (%) Relative Output Voltage 4 60 G 40 20 G B 0 400 500 600 700 800 Wavelength (nm) Data Sheet S15417EJ2V0DS 17 µ PD3728DZ APPLICATION CIRCUIT EXAMPLE +5 V +12 V 10 Ω µ PD3728DZ + B4 10 µ F/16 V 0.1 µ F 1 2 B6 3 4 B5 5 6 7 φ RB 47 Ω 8 2Ω 9 10 11 12 φ2 GND GND VOUT6 VOUT1 GND GND VOUT5 VOUT2 GND GND 36 B3 0.1 µ F 47 µ F/25 V 35 34 32 + B2 0.1 µ F 10 µ F/16 V 31 φ CLB 30 47 Ω φ RB φ 1L 29 47 Ω φ 10 φ 20 28 2Ω VOD NC NC NC NC NC NC 26 25 24 2Ω 2Ω φ2 14 φ1 23 2Ω 2Ω φ2 15 φ TG1 22 2Ω φ TG2 21 2Ω 18 GND NC NC NC NC φ CLB 27 φ1 φ TG3 +5 V B1 33 13 17 18 VOUT3 2Ω 16 Caution VOUT4 + 20 19 Connect the No connection pins (NC) to GND. Data Sheet S15417EJ2V0DS φ1 φ TG µ PD3728DZ Remarks 1. Pin 9 (φ 10) and pin 28 (φ 20) should be open to decrease the influence of input clock noise to output signal waveform, in case of operating at low or middle speed range; data rate under 24 MHz or so. 2. Inverters shown in the above application circuit example are the 74AC04. 3. B1 to B6 in the application circuit example are shown in the figure below. B1-B6 EQUIVALENT CIRCUIT +12 V + 47 µ F/25 V 0.1 µ F 4.7 kΩ CCD VOUT 47 Ω 110 Ω 2SC945 2SA1005 1 kΩ Data Sheet S15417EJ2V0DS 19 µ PD3728DZ PACKAGE DRAWING CCD LINEAR IMAGE SENSOR 36-PIN CERAMIC DIP (15.24 mm (600)) 94.00±0.7 46.00±0.5 3.00±0.08 13.00±0.5 35.00±0.6 1 14.66 4 11.00±0.15 1.00±0.08 1.00 The 1st valid pixel index mark (6.00) 2.8±0.08 1.27 48.26±0.4 (17.09 MAX.) (15.24 MIN.) 20.32±0.13 1.00±0.2 4.00±0.2 1 2 3 4 (2.8) 2.54 0.46±0.05 24.13±0.2 20.32±0.13 4.85±0.38 (2.6) 3 2 3.4±0.3 0.25±0.05 Name Dimensions Refractive index Glass cap 93.0 × 9.0 × 1.1 1.5 1st valid pixel Center of package The bottom of package The surface of the chip The surface of the chip The surface of the glass cap The tolerance of package dimension ±0.25 : less than 10mm from W/F edge ±0.50 : equal or more than 10mm from W/F edge 36D-1CCD-PKG2-4 20 Data Sheet S15417EJ2V0DS µ PD3728DZ RECOMMENDED SOLDERING CONDITIONS When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. Type of Through-hole Device µ PD3728DZ : CCD linear image sensor 36-pin ceramic DIP (CERDIP) (15.24 mm (600)) Process Partial heating method Conditions Pin temperature : 300 °C or below, Heat time : 3 seconds or less (per pin) Cautions 1. During assembly care should be taken to prevent solder or flux from contacting the glass cap. The optical characteristics could be degraded by such contact. 2. Soldering by the solder flow method may have deleterious effects on prevention of glass cap soiling and heat resistance. So the method cannot be guaranteed. Data Sheet S15417EJ2V0DS 21 µ PD3728DZ NOTES ON HANDLING THE PACKAGES 1 MOUNTING OF THE PACKAGE The application of an excessive load to the package may cause the package to warp or break, or cause chips to come off internally. Particular care should be taken when mounting the package on the circuit board. Don't have any object come in contact with glass cap. You should not reform the lead frame. We recommended to use a IC-inserter when you assemble to PCB. Also, be care that the any of the following can cause the package to crack or dust to be generated. 1. Applying heat to the external leads for an extended period of time with soldering iron. 2. Applying repetitive bending stress to the external leads. 3. Rapid cooling or heating For this product, the reference value for the three-point bending strength Note is 180 [N] (at distance between supports: 70 mm). Avoid imposing a load, however, on the inside portion as viewed from the face on which the window (glass) is bonded to the package body (ceramic). Note Three-point bending strength test Distance between supports: 70 mm, Support R: R 2 mm, Loading rate: 0.5 mm/min. Load Load 70 mm 70 mm 2 GLASS CAP Don’t either touch glass cap surface by hand or have any object come in contact with glass cap surface. Care should be taken to avoid mechanical or thermal shock because the glass cap is easily to damage. For dirt stuck through electricity ionized air is recommended. 22 Data Sheet S15417EJ2V0DS µ PD3728DZ NOTES ON HANDLING THE PACKAGES 3 OPERATE AND STORAGE ENVIRONMENTS Operate in clean environments. CCD image sensors are precise optical equipment that should not be subject to mechanical shocks. Exposure to high temperatures or humidity will affect the characteristics. So avoid storage or usage in such conditions. Keep in a case to protect from dust and dirt. Dew condensation may occur on CCD image sensors when the devices are transported from a low-temperature environment to a high-temperature environment. Avoid such rapid temperature changes. For more details, refer to our document "Review of Quality and Reliability Handbook" (C12769E) 4 ELECTROSTATIC BREAKDOWN CCD image sensor is protected against static electricity, but destruction due to static electricity is sometimes detected. Before handling be sure to take the following protective measures. 1. 2. 3. 4. 5. Ground the tools such as soldering iron, radio cutting pliers of or pincer. Install a conductive mat or on the floor or working table to prevent the generation of static electricity. Either handle bare handed or use non-chargeable gloves, clothes or material. Ionized air is recommended for discharge when handling CCD image sensor. For the shipment of mounted substrates, use box treated for prevention of static charges. 6. Anyone who is handling CCD image sensors, mounting them on PCBs or testing or inspecting PCBs on which CCD image sensors have been mounted must wear anti-static bands such as wrist straps and ankle straps which are grounded via a series resistance connection of about 1 MΩ. Data Sheet S15417EJ2V0DS 23 µ PD3728DZ [MEMO] 24 Data Sheet S15417EJ2V0DS µ PD3728DZ [MEMO] Data Sheet S15417EJ2V0DS 25 µ PD3728DZ [MEMO] 26 Data Sheet S15417EJ2V0DS µ PD3728DZ NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet S15417EJ2V0DS 27 µ PD3728DZ • The information in this document is current as of October, 2002. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. 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(Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4