DATA SHEET MOS INTEGRATED CIRCUIT µPD4481162, 4481182, 4481322, 4481362 8M-BIT ZEROSBTM SRAM PIPELINED OPERATION Description The µPD4481162 is a 524,288-word by 16-bit, the µPD4481182 is a 524,288-word by 18-bit, the µPD4481322 is a 262,144-word by 32-bit and the µPD4481362 is a 262,144-word by 36-bit ZEROSB static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. The µPD4481162, µPD4481182, µPD4481322 and µPD4481362 are optimized to eliminate dead cycles for read to write, or write to read transitions. These ZEROSB static RAMs integrate unique synchronous peripheral circuitry, 2-bit burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the single clock input (CLK). The µPD4481162, µPD4481182, µPD4481322 and µPD4481362 are suitable for applications which require synchronous operation, high speed, low voltage, high density and wide bit configuration, such as buffer memory. ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State (“Sleep”). In the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal operation. The µPD4481162, µPD4481182, µPD4481322 and µPD4481362 are packaged in 100-pin PLASTIC LQFP with a 1.4 mm package thickness for high density and low capacitive loading. Features • Low voltage core supply : VDD = 3.3 ± 0.165 V (-A44, -A50, -A60, -A75, -A44Y, -A50Y, -A60Y, -A75Y) VDD = 2.5 ± 0.125 V (-C60, -C75, -C60Y, -C75Y) • Synchronous operation • Operating temperature : TA = 0 to 70 °C (-A44, -A50, -A60, -A75, -C60, -C75) TA = −40 to +85 °C (-A44Y, -A50Y, -A60Y, -A75Y, -C60Y, -C75Y) • 100 percent bus utilization • Internally self-timed write control • Burst read / write : Interleaved burst and linear burst sequence • Fully registered inputs and outputs for pipelined operation • All registers triggered off positive clock edge • 3.3V or 2.5V LVTTL Compatible : All inputs and outputs • Fast clock access time : 2.8 ns (225 MHz), 3.2 ns (200 MHz), 3.5 ns (167 MHz) , 4.2 ns (133 MHz) • Asynchronous output enable : /G • Burst sequence selectable : MODE • Sleep mode : ZZ (ZZ = Open or Low : Normal operation) • Separate byte write enable : /BW1 to /BW4 (µPD4481322 and µPD4481362) /BW1 and /BW2 (µPD4481162 and µPD4481182) • Three chip enables for easy depth expansion • Common I/O using three state outputs The information in this document is subject to change without notice. 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Document No. M15562EJ3V0DS00 (3rd edition) Date Published December 2002 NS CP(K) Printed in Japan The mark shows major revised points. 2001 µPD4481162, 4481182, 4481322, 4481362 Ordering Information Part number (1/2) Access Clock Core Supply I/O Interface Time Frequency Voltage Temperature ns MHz V °C µPD4481162GF-A44 2.8 225 3.3 ± 0.165 µPD4481162GF-A50 3.2 200 µPD4481162GF-A60 3.5 167 µPD4481162GF-A75 4.2 133 µPD4481182GF-A44 2.8 225 µPD4481182GF-A50 3.2 200 µPD4481182GF-A60 3.5 167 µPD4481182GF-A75 4.2 133 µPD4481322GF-A44 2.8 225 µPD4481322GF-A50 3.2 200 µPD4481322GF-A60 3.5 167 µPD4481322GF-A75 4.2 133 µPD4481362GF-A44 2.8 225 µPD4481362GF-A50 3.2 200 µPD4481362GF-A60 3.5 167 µPD4481362GF-A75 4.2 133 µPD4481162GF-C60 3.5 167 µPD4481162GF-C75 4.2 133 µPD4481182GF-C60 3.5 167 µPD4481182GF-C75 4.2 133 µPD4481322GF-C60 3.5 167 µPD4481322GF-C75 4.2 133 µPD4481362GF-C60 3.5 167 µPD4481362GF-C75 4.2 133 3.3 V LVTTL Note Operating 0 to 70 Package 100-pin PLASTIC LQFP (14 x 20) 3.3 V or 2.5 V LVTTL 3.3 V LVTTL Note 3.3 V or 2.5 V LVTTL 3.3 V LVTTL Note 3.3 V or 2.5 V LVTTL 3.3 V LVTTL Note 3.3 V or 2.5 V LVTTL 2.5 ± 0.125 2.5 V LVTTL Note Although 2.5V LVTTL interface can also be used, a performance becomes equivalent to -A60 (167 MHz). 2 Data Sheet M15562EJ3V0DS µPD4481162, 4481182, 4481322, 4481362 (2/2) Part number Access Clock Core Supply I/O Interface Time Frequency Voltage Temperature ns MHz V °C µPD4481162GF-A44Y 2.8 225 3.3 ± 0.165 µPD4481162GF-A50Y 3.2 200 µPD4481162GF-A60Y 3.5 167 µPD4481162GF-A75Y 4.2 133 µPD4481182GF-A44Y 2.8 225 µPD4481182GF-A50Y 3.2 200 µPD4481182GF-A60Y 3.5 167 µPD4481182GF-A75Y 4.2 133 µPD4481322GF-A44Y 2.8 225 µPD4481322GF-A50Y 3.2 200 µPD4481322GF-A60Y 3.5 167 µPD4481322GF-A75Y 4.2 133 µPD4481362GF-A44Y 2.8 225 µPD4481362GF-A50Y 3.2 200 µPD4481362GF-A60Y 3.5 167 µPD4481362GF-A75Y 4.2 133 µPD4481162GF-C60Y 3.5 167 µPD4481162GF-C75Y 4.2 133 µPD4481182GF-C60Y 3.5 167 µPD4481182GF-C75Y 4.2 133 µPD4481322GF-C60Y 3.5 167 µPD4481322GF-C75Y 4.2 133 µPD4481362GF-C60Y 3.5 167 µPD4481362GF-C75Y 4.2 133 3.3 V LVTTL Note Operating −40 to +85 Package 100-pin PLASTIC LQFP (14 x 20) 3.3 V or 2.5 V LVTTL 3.3 V LVTTL Note 3.3 V or 2.5 V LVTTL 3.3 V LVTTL Note 3.3 V or 2.5 V LVTTL 3.3 V LVTTL Note 3.3 V or 2.5 V LVTTL 2.5 ± 0.125 2.5 V LVTTL Note Although 2.5V LVTTL interface can also be used, a performance becomes equivalent to -A60Y (167 MHz). Data Sheet M15562EJ3V0DS 3 µPD4481162, 4481182, 4481322, 4481362 Pin Configurations /××× indicates active low signal. 100-pin PLASTIC LQFP (14 × 20) [µPD4481162GF, µPD4481182GF] A9 A8 A17 NC ADV /G /CKE /WE CLK VSS VDD /CE2 /BW1 /BW2 NC NC CE2 /CE A7 A6 Marking Side 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 NC 1 80 A18 NC 2 79 NC NC 3 78 NC VDDQ 4 77 VDDQ VSSQ 5 76 VSSQ NC 6 75 NC NC 7 74 I/OP1, NC I/O9 8 73 I/O8 I/O10 9 72 I/O7 VSSQ 10 71 VSSQ VDDQ 11 70 VDDQ I/O11 12 69 I/O6 I/O12 13 68 I/O5 VDD 14 67 VSS VDD 15 66 VDD VDD 16 65 VDD VSS 17 64 ZZ I/O13 18 63 I/O4 I/O14 19 62 I/O3 VDDQ 20 61 VDDQ VSSQ 21 60 VSSQ I/O15 22 59 I/O2 I/O16 23 58 I/O1 I/OP2, NC 24 57 NC NC 25 56 NC VSSQ 26 55 VSSQ VDDQ 27 54 VDDQ NC 28 53 NC NC 29 52 NC NC 30 51 NC 4 Data Sheet M15562EJ3V0DS A16 A15 A14 A13 A12 A11 NC Remark Refer to Package Drawing for the 1-pin index mark. A10 NC VDD VSS NC NC A0 A1 A2 A3 A4 A5 MODE 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 µPD4481162, 4481182, 4481322, 4481362 Pin Identifications [µPD4481162GF, µPD4481182GF] Symbol A0 to A18 Pin No. 37, 36, 35, 34, 33, 32, 100, 99, 82, 81, Description Synchronous Address Input 44, 45, 46, 47, 48, 49, 50, 83, 80 I/O1 to I/O16 58, 59, 62, 63, 68, 69, 72, 73, 8, 9, 12, 13, Synchronous Data In, 18, 19, 22, 23 Synchronous / Asynchronous Data Out I/OP1, NC Note 74 Synchronous Data In (Parity), I/OP2, NC Note 24 Synchronous / Asynchronous Data Out (Parity) ADV 85 Synchronous Address Load / Advance Input /CE, CE2, /CE2 98, 97, 92 Synchronous Chip Enable Input /WE 88 Synchronous Write Enable Input /BW1, /BW2 93, 94 Synchronous Byte Write Enable Input /G 86 Asynchronous Output Enable Input CLK 89 Clock Input /CKE 87 Synchronous Clock Enable Input MODE 31 Asynchronous Burst Sequence Select Input Have to tied to VDD or VSS during normal operation ZZ 64 Asynchronous Power Down State Input VDD 14, 15, 16, 41, 65, 66, 91 Power Supply VSS 17, 40, 67, 90 Ground VDDQ 4, 11, 20, 27, 54, 61, 70, 77 Output Buffer Power Supply VSSQ 5, 10, 21, 26, 55, 60, 71, 76 Output Buffer Ground NC 1, 2, 3, 6, 7, 25, 28, 29, 30, 38, 39, 42, 43, No Connection 51, 52, 53, 56, 57, 75, 78, 79, 84, 95, 96 Note NC (No Connection) is used in the µPD4481162GF. I/OP1 and I/OP2 are used in the µPD4481182GF. Data Sheet M15562EJ3V0DS 5 µPD4481162, 4481182, 4481322, 4481362 100-pin PLASTIC LQFP (14 × 20) [µPD4481322GF, µPD4481362GF] A9 A8 A17 NC ADV /G /CKE /WE CLK VSS VDD /CE2 /BW1 /BW2 /BW3 /BW4 CE2 /CE A7 A6 Marking Side 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 I/OP3, NC 1 80 I/OP2, NC I/O17 2 79 I/O16 I/O18 3 78 I/O15 VDDQ 4 77 VDDQ VSSQ 5 76 VSSQ I/O19 6 75 I/O14 I/O20 7 74 I/O13 I/O21 8 73 I/O12 I/O22 9 72 I/O11 VSSQ 10 71 VSSQ VDDQ 11 70 VDDQ I/O23 12 69 I/O10 I/O24 13 68 I/O9 VDD 14 67 VSS VDD 15 66 VDD VDD 16 65 VDD VSS 17 64 ZZ I/O25 18 63 I/O8 I/O26 19 62 I/O7 VDDQ 20 61 VDDQ VSSQ 21 60 VSSQ I/O27 22 59 I/O6 I/O28 23 58 I/O5 I/O29 24 57 I/O4 I/O30 25 56 I/O3 VSSQ 26 55 VSSQ VDDQ 27 54 VDDQ I/O31 28 53 I/O2 I/O32 29 52 I/O1 I/OP4, NC 30 51 I/OP1, NC 6 Data Sheet M15562EJ3V0DS A16 A15 A14 A13 A12 A11 NC Remark Refer to Package Drawing for the 1-pin index mark. A10 NC VDD VSS NC NC A0 A1 A2 A3 A4 A5 MODE 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 µPD4481162, 4481182, 4481322, 4481362 [µPD4481322GF, µPD4481362GF] Symbol A0 to A17 Pin No. Description 37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, Synchronous Address Input 45, 46, 47, 48, 49, 50, 83 I/O1 to I/O32 52, 53, 56, 57, 58, 59, 62, 63, 68, 69, 72, Synchronous Data In, 73, 74, 75, 78, 79, 2, 3, 6, 7, 8, 9, 12, 13, Synchronous / Asynchronous Data Out 18, 19, 22, 23, 24, 25, 28, 29 I/OP1, NC Note 51 Synchronous Data In (Parity), I/OP2, NC Note 80 Synchronous / Asynchronous Data Out (Parity) I/OP3, NC Note 1 I/OP4, NC Note 30 ADV 85 Synchronous Address Load / Advance Input /CE, CE2, /CE2 98, 97, 92 Synchronous Chip Enable Input /WE 88 Synchronous Write Enable Input /BW1 to /BW4 93, 94, 95, 96 Synchronous Byte Write Enable Input /G 86 Asynchronous Output Enable Input CLK 89 Clock Input /CKE 87 Synchronous Clock Enable Input MODE 31 Asynchronous Burst Sequence Select Input Have to tied to VDD or VSS during normal operation ZZ 64 Asynchronous Power Down State Input VDD 14, 15, 16, 41, 65, 66, 91 Power Supply VSS 17, 40, 67, 90 Ground VDDQ 4, 11, 20, 27, 54, 61, 70, 77 Output Buffer Power Supply VSSQ 5, 10, 21, 26, 55, 60, 71, 76 Output Buffer Ground NC 38, 39, 42, 43, 84 No Connection Note NC (No Connection) is used in the µPD4481322GF. I/OP1 to I/OP4 are used in the µPD4481362GF. Data Sheet M15562EJ3V0DS 7 µPD4481162, 4481182, 4481322, 4481362 Block Diagrams [µPD4481162, µPD4481182] A0 to A18 19 Address register 0 MODE CLK 17 A1 A0 Burst logic ADV K K 19 A1’ A0’ /CKE 19 Write address register 1 Write address register 0 19 16/18 16/18 Output buffers /WE 1,024 rows 512 x 16 columns (8,388,608 bits) 512 x 18 columns (9,437,184 bits) Data steering Write drivers Output registers Write registry and data coherency control logic Sense amplifiers Memory Cell Array ADV /BW1 /BW2 I/O1 to I/O16 I/OP1, I/OP2 E E 16/18 16/18 16/18 Input register 1E Input register 0E Read logic /G /CE CE2 /CE2 ZZ Power down control Burst Sequence [µPD4481162, µPD4481182] Interleaved Burst Sequence Table (MODE = VDD) External Address A18 to A2, A1, A0 1st Burst Address A18 to A2, A1, /A0 2nd Burst Address A18 to A2, /A1, A0 3rd Burst Address A18 to A2, /A1, /A0 Linear Burst Sequence Table (MODE = VSS) External Address A18 to A2, 0, 0 A18 to A2, 0, 1 A18 to A2, 1, 0 A18 to A2, 1, 1 1st Burst Address A18 to A2, 0, 1 A18 to A2, 1, 0 A18 to A2, 1, 1 A18 to A2, 0, 0 2nd Burst Address A18 to A2, 1, 0 A18 to A2, 1, 1 A18 to A2, 0, 0 A18 to A2, 0, 1 3rd Burst Address A18 to A2, 1, 1 A18 to A2, 0, 0 A18 to A2, 0, 1 A18 to A2, 1, 0 8 Data Sheet M15562EJ3V0DS µPD4481162, 4481182, 4481322, 4481362 [µPD4481322, µPD4481362] A0 to A17 18 Address register 0 MODE CLK 16 A1 A0 Burst logic ADV K K 18 A1’ A0’ /CKE 18 Write address register 1 Write address register 0 18 32/36 32/36 Output buffers 1,024 rows 256 x 32 columns (8,388,608 bits) 256 x 36 columns (9,437,184 bits) Data steering Write drivers Output registers Write registry and data coherency control logic Sense amplifiers Memory Cell Array ADV /BW1 /BW2 /BW3 /BW4 /WE I/O1 to I/O32 I/OP1 to I/OP4 E E 32/36 32/36 32/36 Input register 1E Input register 0E Read logic /G /CE CE2 /CE2 ZZ Power down control [µPD4481322, µPD4481362] Interleaved Burst Sequence Table (MODE = VDD) External Address A17 to A2, A1, A0 1st Burst Address A17 to A2, A1, /A0 2nd Burst Address A17 to A2, /A1, A0 3rd Burst Address A17 to A2, /A1, /A0 Linear Burst Sequence Table (MODE = VSS) External Address A17 to A2, 0, 0 A17 to A2, 0, 1 A17 to A2, 1, 0 A17 to A2, 1, 1 1st Burst Address A17 to A2, 0, 1 A17 to A2, 1, 0 A17 to A2, 1, 1 A17 to A2, 0, 0 2nd Burst Address A17 to A2, 1, 0 A17 to A2, 1, 1 A17 to A2, 0, 0 A17 to A2, 0, 1 3rd Burst Address A17 to A2, 1, 1 A17 to A2, 0, 0 A17 to A2, 0, 1 A17 to A2, 1, 0 Data Sheet M15562EJ3V0DS 9 µPD4481162, 4481182, 4481322, 4481362 State Diagram DS BURST DS DS DESELECT WRITE READ DS DS WRITE BEGIN READ READ READ READ BURST BURST WRITE BURST BEGIN WRITE WRITE READ BURST READ BURST WRITE Command Operation DS Deselect Read New Read Write New Write Burst Burst Read, Burst Write or Continue Deselect WRITE BURST Remarks 1. States change on the rising edge of the clock. 2. A Stall or Ignore Clock Edge cycle is not shown in the above diagram. This is because /CKE HIGH only blocks the clock (CLK) input and does not change the state of the device. 10 Data Sheet M15562EJ3V0DS µPD4481162, 4481182, 4481322, 4481362 Asynchronous Truth Table Operation /G I/O Read Cycle L Dout Read Cycle H High-Z Write Cycle × High-Z, Din Deselected × High-Z Remark × : don’t care Synchronous Truth Table Operation /CE CE2 /CE2 ADV /WE /BWs /CKE CLK I/O Address Note Deselected H × × L × × L L→H High-Z None 1 Deselected × L × L × × L L→H High-Z None 1 Deselected × × H L × × L L→H High-Z None 1 Continue Deselected × × × H × × L L→H High-Z None 1 Read Cycle / Begin Burst L H L L H × L L→H Dout External Read Cycle / Continue Burst × × × H × × L L→H Dout Next Write Cycle / Begin Burst L H L L L L L L→H Din External Write Cycle / Continue Burst × × × H × L L L→H Din Next Write Cycle / Write Abort L H L L L H L L→H High-Z External Write Cycle / Write Abort × × × H × H L L→H High-Z Next Stall / Ignore Clock Edge × × × × × × H L→H − Current Notes 2 1. Deselect status is held until new “Begin Burst” entry. 2. If an Ignore Clock Edge command occurs during a read operation, the I/O bus will remain active (low impedance). If it occurs during a write cycle, the bus will remain high impedance. No write operation will be performed during the Ignore Clock Edge cycle. Remarks 1. × : don’t care 2. /BWs = L means any one or more byte write enables (/BW1, /BW2, /BW3 or /BW4) are LOW. /BWs = H means all byte write enables (/BW1, /BW2, /BW3 or /BW4) are HIGH. Data Sheet M15562EJ3V0DS 11 µPD4481162, 4481182, 4481322, 4481362 Partial Truth Table for Write Enables [µPD4481162, µPD4481182] Operation /WE /BW1 /BW2 Read Cycle H × × Write Cycle / Byte 1 (I/O [1:8], I/OP1) L L H Write Cycle / Byte 2 (I/O [9:16], I/OP2) L H L Write Cycle / All Bytes L L L Write Abort / NOP L H H /WE /BW1 /BW2 /BW3 /BW4 Read Cycle H × × × × Write Cycle / Byte 1 (I/O [1:8], I/OP1) L L H H H Write Cycle / Byte 2 (I/O [9:16], I/OP2) L H L H H Write Cycle / Byte 3 (I/O [17:24], I/OP3) L H H L H Write Cycle / Byte 4 (I/O [25:32], I/OP4) L H H H L Write Cycle / All Bytes L L L L L Write Abort / NOP L H H H H Remark × : don’t care [µPD4481322, µPD4481362] Operation Remark × : don’t care ZZ (Sleep) Truth Table 12 ZZ Chip Status ≤ 0.2 V Active Open Active ≥ VDD − 0.2 V Sleep Data Sheet M15562EJ3V0DS µPD4481162, 4481182, 4481322, 4481362 Electrical Specifications Absolute Maximum Ratings Parameter Supply voltage Symbol Conditions VDD -A44, -A50, -A60, -A75 MIN. TYP. MAX. Unit –0.5 +4.0 V –0.5 +3.0 -A44Y, -A50Y, -A60Y, -A75Y -C60, -C75 -C60Y, -C75Y Output supply voltage VDDQ –0.5 VDD V VIN –0.5 Note VDD + 0.5 V Input / Output voltage VI/O Note VDDQ + 0.5 V Operating ambient TA 70 °C Input voltage temperature –0.5 -A44, -A50, -A60, -A75, -C60, -C75 -A44Y, -A50Y, -A60Y, -A75Y, -C60Y, -C75Y Storage temperature Tstg 0 –40 +85 –55 +125 °C Note –2.0 V (MIN.) (Pulse width : 2 ns) Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended DC Operating Conditions Parameter Symbol (1/2) Conditions -A44, -A50, -A60, -A75 Unit -A44Y, -A50Y, -A60Y, -A75Y Supply voltage MIN. TYP. MAX. VDD 3.135 3.3 3.465 V VDDQ 2.375 2.5 2.9 V VIH 1.7 VDDQ + 0.3 V +0.7 V 3.465 V VDDQ + 0.3 V +0.8 V 2.5 V LVTTL Interface Output supply voltage High level input voltage Low level input voltage VIL –0.3 Note 3.3 V LVTTL Interface Output supply voltage High level input voltage Low level input voltage VDDQ 3.135 VIH 2.0 VIL –0.3 3.3 Note Note –0.8 V (MIN.) (Pulse width : 2 ns) Recommended DC Operating Conditions Parameter Symbol (2/2) Conditions -C60, -C75 Unit -C60Y, -C75Y Supply voltage Output supply voltage MIN. TYP. MAX. VDD 2.375 2.5 2.625 V VDDQ 2.375 2.5 2.625 V High level input voltage VIH 1.7 VDDQ + 0.3 V Low level input voltage VIL –0.3 Note +0.7 V Note –0.8 V (MIN.) (Pulse width : 2 ns) Data Sheet M15562EJ3V0DS 13 µPD4481162, 4481182, 4481322, 4481362 DC Characteristics (VDD = 3.3 ± 0.165 V or 2.5 ± 0.125 V) Parameter Symbol Test condition MIN. TYP. MAX. Unit Input leakage current ILI VIN (except ZZ, MODE) = 0 V to VDD –2 +2 µA I/O leakage current ILO VI/O = 0 V to VDDQ, Outputs are disabled. –2 +2 µA Operating supply current IDD Device selected, -A44 440 mA Cycle = MAX. -A44Y VIN ≤ VIL or VIN ≥ VIH, -A50 II/O = 0 mA -A50Y 400 -A60, -C60 320 -A60Y, -C60Y -A75, -C75 300 -A75Y, -C75Y Standby supply current ISB Device deselected, Cycle = 0 MHz, 30 mA VIN ≤ VIL or VIN ≥ VIH, All inputs are static. ISB1 Device deselected, Cycle = 0 MHz, 15 VIN ≤ 0.2 V or VIN ≥ VDD – 0.2 V, VI/O ≤ 0.2 V, All inputs are static. ISB2 Device deselected, Cycle = MAX. 130 VIN ≤ VIL or VIN ≥ VIH Power down supply current ISBZZ ZZ ≥ VDD – 0.2 V, VI/O ≤ VDDQ + 0.2 V VOH IOH = –2.0 mA 1.7 IOH = –1.0 mA 2.1 15 mA 2.5 V LVTTL Interface High level output voltage Low level output voltage VOL V IOL = +2.0 mA 0.7 IOL = +1.0 mA 0.4 V 3.3 V LVTTL Interface High level output voltage VOH IOH = –4.0 mA Low level output voltage VOL IOL = +8.0 mA 2.4 V 0.4 V MAX. Unit Capacitance (TA = 25 °C, f = 1MHz) Parameter Symbol Test condition MIN. TYP. Input capacitance CIN VIN = 0 V 6.0 pF Input / Output capacitance CI/O VI/O = 0 V 8.0 pF Clock input capacitance Cclk Vclk = 0 V 6.0 pF Remark These parameters are periodically sampled and not 100% tested. 14 Data Sheet M15562EJ3V0DS µPD4481162, 4481182, 4481322, 4481362 AC Characteristics (VDD = 3.3 ± 0.165 V or 2.5 ± 0.125 V) AC Test Conditions 2.5 V LVTTL Interface Input waveform (Rise / Fall time ≤ 2.4 ns) 2.4 V 1.2 V Test points 1.2 V 1.2 V Test points 1.2 V VSS Output waveform 3.3 V LVTTL Interface Input waveform (Rise / Fall time ≤ 3.0 ns) 3.0 V 1.5 V Test points 1.5 V 1.5 V Test points 1.5 V VSS Output waveform Output load condition CL : 30 pF 5 pF (TKHQX1, TKHQX2, TGLQX, TGHQZ, TKHQZ) Figure External load at test ZO = 50 Ω I/O (Output) 50 Ω CL VT = +1.2 V / +1.5 V Remark CL includes capacitances of the probe and jig, and stray capacitances. Data Sheet M15562EJ3V0DS 15 µPD4481162, 4481182, 4481322, 4481362 Read and Write Cycle (2.5 V LVTTL Interface) Parameter Symbol -A44, -A50, -A60, -C60 -A75, -C75 Unit -A44Y, -A50Y, -A60Y, -C60Y -A75Y, -C75Y (167 MHz) (133 MHz) Notes Standard Alias MIN. MAX. MIN. MAX. Cycle time TKHKH TCYC 6 – 7.5 – ns Clock access time TKHQV TCD – 3.5 – 4.2 ns Output enable access time TGLQV TOE – 3.5 – 4.2 ns Clock high to output active TKHQX1 TDC1 1.5 – 1.5 – ns Clock high to output change TKHQX2 TDC2 1.5 – 1.5 – ns Output enable to output active TGLQX TOLZ 0 – 0 – ns 1 Output disable to output High-Z TGHQZ TOHZ 0 3.5 0 4.2 ns 1 Clock high to output High-Z TKHQZ TCZ 1.5 3.5 1.5 3.5 ns 1, 2 Clock high pulse width TKHKL TCH 1.8 – 2.2 – ns Clock low pulse width TKLKH TCL 1.8 – 2.2 – ns Setup times TAVKH TAS 1.5 – 1.5 – ns 0.5 – 0.5 – ns Address Address advance TADVVKH Hold times TADVS Clock enable TEVKH TCES Chip enable TCVKH TCSS Data in TDVKH TDS Write enable TWVKH TWS Address TKHAX TAH Address advance TKHADVX 1, 2 TADVH Clock enable TKHEX TCEH Chip enable TKHCX TCSH Data in TKHDX TDH Write enable TKHWX TWH Power down entry time TZZE TZZE – 12 – 15 ns Power down recovery time TZZR TZZR – 12 – 15 ns Notes 1. Transition is measured ±200 mV from steady state. 2. To avoid bus contention, the output buffers are designed such that TKHQZ (device turn-off) is faster than TKHQX1 (device turn-on) at a given temperature and voltage. The specs as shown do not imply bus contention because TKHQX1 is a min. parameter that is worse case at totally different conditions (TA min., VDD max.) than TKHQZ, which is a max. parameter (worse case at TA max., VDD min.). 16 Data Sheet M15562EJ3V0DS µPD4481162, 4481182, 4481322, 4481362 Read and Write Cycle (3.3 V LVTTL Interface) Parameter Symbol -A44 -A50 -A60 -A75 Unit -A44Y -A50Y -A60Y -A75Y (225 MHz) (200 MHz) (167 MHz) (133 MHz) Notes Standard Alias MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. Cycle time TKHKH TCYC 4.4 – 5 – 6 – 7.5 – ns Clock access time TKHQV TCD – 2.8 – 3.2 – 3.5 – 4.2 ns Output enable access time TGLQV TOE – 2.8 – 3.2 – 3.5 – 4.2 ns Clock high to output active TKHQX1 TDC1 1.5 – 1.5 – 1.5 – 1.5 – ns Clock high to output change TKHQX2 TDC2 1.5 – 1.5 – 1.5 – 1.5 – ns Output enable to output active TGLQX TOLZ 0 – 0 – 0 – 0 – ns 1 Output disable to output High-Z TGHQZ TOHZ 0 2.8 0 3.2 0 3.5 0 4.2 ns 1 Clock high to output High-Z TKHQZ TCZ 1.5 2.8 1.5 3.2 1.5 3.5 1.5 3.5 ns 1, 2 Clock high pulse width TKHKL TCH 1.8 – 1.8 – 1.8 – 2.2 – ns Clock low pulse width TKLKH TCL 1.8 – 1.8 – 1.8 – 2.2 – ns Setup times TAVKH TAS 1.4 – 1.5 – 1.5 – 1.5 – ns 0.4 – 0.5 – 0.5 – 0.5 – ns Address Address advance TADVVKH Hold times TADVS Clock enable TEVKH TCES Chip enable TCVKH TCSS Data in TDVKH TDS Write enable TWVKH TWS Address TKHAX TAH Address advance TKHADVX 1, 2 TADVH Clock enable TKHEX TCEH Chip enable TKHCX TCSH Data in TKHDX TDH Write enable TKHWX TWH Power down entry time TZZE TZZE – 8.8 – 10 – 12 – 15 ns Power down recovery time TZZR TZZR – 8.8 – 10 – 12 – 15 ns Notes 1. Transition is measured ±200 mV from steady state. 2. To avoid bus contention, the output buffers are designed such that TKHQZ (device turn-off) is faster than TKHQX1 (device turn-on) at a given temperature and voltage. The specs as shown do not imply bus contention because TKHQX1 is a min. parameter that is worse case at totally different conditions (TA min., VDD max.) than TKHQZ, which is a max. parameter (worse case at TA max., VDD min.). Data Sheet M15562EJ3V0DS 17 µPD4481162, 4481182, 4481322, 4481362 READ / WRITE CYCLE 2 TKHKH 3 1 4 5 6 A3 A4 D (A2) D (A2+1) 7 8 A5 A6 9 10 CLK TEVKH TKHEX TCVKH TKHCX TKHKL TKLKH /CKE /CEs Note 1 TADVVKH TKHADVX ADV TWVKH TKHWX /WE TWVKH TKHWX /BWs Note 2 Address A1 TAVKH Data In A2 TKHAX High-Z D (A1) TDVKH TKHDX High-Z TKHQX1 TKHQX2 High-Z Data Out A7 Q (A3) TKHQV D (A5) High-Z TGLQV TKHQZ Q (A4) Q (A4+1) High-Z Q (A6) TKHQX2 TGHQZ TGLQX /G Command WRITE D (A1) WRITE D (A2) BURST WRITE D (A2+1) READ Q (A3) READ Q (A4) BURST READ Q (A4+1) WRITE D (A5) READ Q (A6) WRITE Q (A7) DESELECT Notes 1. /CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH. When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW. 2. /BWs refers to /BW1, /BW2, /BW3 and /BW4. When /BWs is LOW, any one or more byte write enables (/BW1, /BW2, /BW3 or /BW4) are LOW. 18 Data Sheet M15562EJ3V0DS µPD4481162, 4481182, 4481322, 4481362 NOP, STALL AND DESELECT CYCLE 1 2 A1 A2 3 4 5 A3 A4 6 7 8 9 10 CLK /CKE /CEs ADV /WE /BWs Address High-Z High-Z D (A1) Data In A5 High-Z D (A4) TKHQZ High-Z Data Out Q (A2) High-Z Q (A3) Q (A5) TKHQX2 Command WRITE D (A1) READ Q (A2) STALL READ Q (A3) WRITE D (A4) STALL Data Sheet M15562EJ3V0DS NOP READ Q (A5) DESELECT CONTINUE DESELECT 19 µPD4481162, 4481182, 4481322, 4481362 POWER DOWN (ZZ) CYCLE 1 2 TKHKH 3 4 5 6 7 8 9 10 11 12 CLK TKHKL TKLKH /CKE /CEs Note ADV /WE Note /BWs Address A1 A2 /G Data Out High-Z High-Z Q (A1) Q1 (A2) ZZ TZZE TZZR Power Down (ISBZZ) State Note /WE or /CEs must be held HIGH at CLK rising edge (clock edge No.2 and No.3 in this figure) prior to power down state entry. 20 Data Sheet M15562EJ3V0DS µPD4481162, 4481182, 4481322, 4481362 Package Drawing 100-PIN PLASTIC LQFP (14x20) A B 80 81 51 50 detail of lead end S C D R Q 31 30 100 1 F G H I J M K P S N S L M NOTE ITEM Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. MILLIMETERS A 22.0±0.2 B 20.0±0.2 C 14.0±0.2 D 16.0±0.2 F 0.825 G 0.575 H 0.32 +0.08 −0.07 I J 0.13 0.65 (T.P.) K 1.0±0.2 L 0.5±0.2 M 0.17 +0.06 −0.05 N 0.10 P 1.4 Q 0.125±0.075 R 3° +7° −3° S 1.7 MAX. S100GF-65-8ET-1 Data Sheet M15562EJ3V0DS 21 µPD4481162, 4481182, 4481322, 4481362 Recommended Soldering Condition Please consult with our sales offices for soldering conditions of the µPD4481162, 4481182, 4481322 and 4481362. Types of Surface Mount Devices µPD4481162GF : 100-pin PLASTIC LQFP (14 x 20) µPD4481182GF : 100-pin PLASTIC LQFP (14 x 20) µPD4481322GF : 100-pin PLASTIC LQFP (14 x 20) µPD4481362GF : 100-pin PLASTIC LQFP (14 x 20) 22 Data Sheet M15562EJ3V0DS µPD4481162, 4481182, 4481322, 4481362 Revision History Edition/ Date 3rd edition/ Dec. 2002 Page Type of This Previous edition edition Throughout Throughout Location Description (Previous edition → This edition) revision Modification − Preliminary Data Sheet → Data Sheet Addition − Extended operating temperature products (TA = −40 to +85 °C) Data Sheet M15562EJ3V0DS 23 µPD4481162, 4481182, 4481322, 4481362 [MEMO] 24 Data Sheet M15562EJ3V0DS µPD4481162, 4481182, 4481322, 4481362 [MEMO] Data Sheet M15562EJ3V0DS 25 µPD4481162, 4481182, 4481322, 4481362 [MEMO] 26 Data Sheet M15562EJ3V0DS µPD4481162, 4481182, 4481322, 4481362 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet M15562EJ3V0DS 27 µPD4481162, 4481182, 4481322, 4481362 ZEROSB is a trademark of NEC Electronics Corporation. • The information in this document is current as of December, 2002. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. 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