DATA SHEET MOS Integrated Circuit µPD720122 USB2.0 Generic Device Controller The µPD720122 is USB2.0 Generic Device Controller, which combines the NEC Electronics USB2.0 PHY and Endpoint Controller. The Controller has certified by USB Implementers Forum. End-point Controller has banked two Bulk Endpoint and one Interrupt End-point, and selectable three general CPU bus-types, suitable for designing various USB device. The controller has the external local bus, that enables to perform high speed data transferring when CPU is accessing to the controller. These IP Blocks in the controller are based completely on an NEC Electronics ASIC core, so µPD720122 is suitable to design for the prototype system that are intended to design ASIC in the future. Detailed function descriptions are provided in the following user’s manual. Be sure to read the manual before designing. µPD720122 User’s Manual: S15829E FEATURES • Complaint with USB2.0 specification (Maximum data transferring rate: 480 Mbps) • USB2.0 certified (TestID=40000822) • High(480Mbps) / Full(12Mbps)- Speed support and switch automatically • Easy to design NEC Electronics ASIC • Generic USB2.0 Device Controller • Two Bulk End-points and One Interrupt End-point • Performed Data Local Bus independent from CPU bus. (Maximum Data Transferring rate: 21 MBps with DMA mode ) • Selectable three CPU Bus Interface ORDERING INFORMATION Part Number Package µPD720122GC-9EU 100-pin plastic TQFP (Fine pitch) (14 × 14) µPD720122F1-DN2 109-pin plastic FBGA (11 × 11) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. S16685EJ2V0DS00 (2nd edition) Date Published June 2003 NS CP (K) Printed in Japan The mark shows major revised points. 2003 µPD720122 BLOCK DIAGRAM EPC2 Core BIU Core CPU BUS Protocol Controller EP0 Control IN 64 Byte EP0 Control OUT 64 Byte Local BUS EP1 BulkOUT 512 Byte x2 EP2 BulkIN 512 Byte x2 EP3 Interrupt IN 8 Byte PHY Core : USB2.0 transceiver with serial interface engine EPC2 Core : Endpoint controller BIU Core : Bus Interface Unit 2 PHY Core Data Sheet S16685EJ2V0DS USB BUS µPD720122 PIN CONFIGURATION • 100-pin plastic TQFP (Fine pitch) (14 × 14) µ PD720122GC-9EU Top View Remark The function of the pin is shown with Function 1/Function 2/Function 3 from the left. Data Sheet S16685EJ2V0DS 3 µPD720122 µ PD720122GC-9EU 4 (1/2) Pin Pin Name Pin Name Pin Name Pin Pin Name Pin Name Pin Name No. Function1 Function2 Function3 No. Function1 Function2 Function3 1 VDD VDD VDD 26 GND GND GND 2 RESETB RESETB RESETB 27 D8 Reserved D8 3 GND GND GND 28 D9 Reserved D9 4 XIN_CLK XIN_CLK XIN_CLK 29 D10 Reserved D10 5 XOUT XOUT XOUT 30 D11 Reserved D11 6 GND GND GND 31 D12 Reserved D12 7 CSB CSB CSB 32 D13 Reserved D13 8 INTB_ALL ALE ALE 33 D14 Reserved D14 9 A1 INTB_ALL INTB_ALL 34 D15 Reserved D15 10 A2 Reserved Reserved 35 VDD VDD VDD 11 A3 Reserved Reserved 36 GND GND GND 12 A4 Reserved Reserved 37 WRB WRB WRB 13 A5 Reserved Reserved 38 RDB RDB RDB 14 A6 Reserved Reserved 39 INT0B INT0B INT0B 15 A7 Reserved Reserved 40 INT1B INT1B INT1B 16 GND GND GND 41 INT2B INT2B INT2B 17 D0 AD0 D0 42 ACTIVE ACTIVE ACTIVE 18 D1 AD1 AD1 43 SCAN1 SCAN1 SCAN1 19 D2 AD2 AD2 44 SCAN0 SCAN0 SCAN0 20 D3 AD3 AD3 45 M2 M2 M2 21 D4 AD4 AD4 46 EP1_DRQB EP1_DRQB EP1_DRQB 22 D5 AD5 AD5 47 EP1_DACKB EP1_DACKB EP1_DACKB 23 D6 AD6 AD6 48 EP1_RDB EP1_RDB Reserved 24 D7 AD7 AD7 49 EP1_TCB EP1_TCB EP1_TCB 25 VDD VDD VDD 50 GND GND GND Data Sheet S16685EJ2V0DS µPD720122 µ PD720122GC-9EU (2/2) Pin Pin Name Pin Name Pin Name Pin Pin Name Pin Name Pin Name No. Fucntion1 Function2 Function3 No. Fucntion1 Function2 Function3 51 VDD VDD VDD 76 GND GND GND 52 FM21 FM21 FM21 77 BUNRI BUNRI BUNRI 53 EP2_DRQB EP2_DRQB EP2_DRQB 78 RREF RREF RREF 54 EP2_DACKB EP2_DACKB EP2_DACKB 79 AVSS(R) AVSS(R) AVSS(R) 55 EP2_WRB EP2_WRB Reserved 80 AVDD AVDD AVDD 56 EP2_TCB EP2_TCB EP2_TCB 81 AVSS AVSS AVSS 57 LD0 LD0 Reserved 82 RPU RPU RPU 58 LD1 LD1 Reserved 83 VSS VSS VSS 59 LD2 LD2 Reserved 84 RSDP RSDP RSDP 60 LD3 LD3 Reserved 85 DP DP DP 61 GND GND GND 86 VDD VDD VDD 62 LD4 LD4 Reserved 87 DM DM DM 63 LD5 LD5 Reserved 88 RSDM RSDM RSDM 64 LD6 LD6 Reserved 89 VSS VSS VSS 65 LD7 LD7 Reserved 90 NC NC NC 66 LD8 LD8 Reserved 91 PVSS PVSS PVSS 67 LD9 LD9 Reserved 92 NC NC NC 68 GND GND GND 93 PVDD PVDD PVDD 69 LD10 LD10 Reserved 94 VSS VSS VSS 70 LD11 LD11 Reserved 95 VDD VDD VDD 71 LD12 LD12 Reserved 96 VSS VSS VSS 72 LD13 LD13 Reserved 97 M1 M1 M1 73 LD14 LD14 Reserved 98 M0 M0 M0 74 LD15 LD15 Reserved 99 VBUS VBUS VBUS 75 VDD VDD VDD 100 GND GND GND Remark AVSS (R) should be used to connect RREF through 1 % precision reference resistor of 9.1 kΩ. Data Sheet S16685EJ2V0DS 5 µPD720122 • 109-pin plastic FBGA (11 × 11) µ PD720122F1-DN2 Bottom View Remarks The pin name is showing it with Function1. As for the pin name of Function2 and Function3, please refer to the table of the next page. 6 Data Sheet S16685EJ2V0DS µPD720122 µ PD720122F1-DN2 (1/2) Pin Pin Name Pin Name Pin Name Pin Pin Name Pin Name Pin Name No. Function1 Function2 Function3 No. Function1 Function2 Function3 1 NC NC NC 26 AVSS AVSS AVSS 2 D8 Reserved D8 27 RSDP RSDP RSDP 3 D10 Reserved D10 28 VDD VDD VDD 4 D12 Reserved D12 29 NC NC NC 5 D15 Reserved D15 30 NC NC NC 6 GND GND GND 31 VDD VDD VDD 7 INT1B INT1B INT1B 32 M1 M1 M1 8 ACTIVE ACTIVE ACTIVE 33 VBUS VBUS VBUS 9 M2 M2 M2 34 NC NC NC 10 EP1_DACKB EP1_DACKB EP1_DACKB 35 RESETB RESETB RESETB 11 EP1_TCB EP1_TCB EP1_TCB 36 XIN_CLK XIN_CLK XIN_CLK 12 NC NC NC 37 GND GND GND 13 FM21 FM21 FM21 38 A1 INTB_ALL INTB_ALL 14 EP2_DACKB EP2_DACKB EP2_DACKB 39 A3 Reserved Reserved 15 EP2_TCB EP2_TCB EP2_TCB 40 A7 Reserved Reserved 16 LD2 LD2 Reserved 41 D0 AD0 D0 17 GND GND GND 42 D3 AD3 AD3 18 LD7 LD7 Reserved 43 D5 AD5 AD5 19 LD9 LD9 Reserved 44 D7 AD7 AD7 20 LD11 LD11 Reserved 45 NC NC NC 21 LD13 LD13 Reserved 46 D9 Reserved D9 22 LD15 LD15 Reserved 47 D11 Reserved D11 23 NC NC NC 48 D14 Reserved D14 24 BUNRI BUNRI BUNRI 49 RDB RDB RDB 25 AVSS(R) AVSS(R) AVSS(R) 50 INT2B INT2B INT2B Remark AVSS (R) should be used to connect RREF through 1 % precision reference resistor of 9.1 kΩ. Data Sheet S16685EJ2V0DS 7 µPD720122 µ PD720122F1-DN2 8 (2/2) Pin Pin Name Pin Name Pin Name Pin Pin Name Pin Name Pin Name No. Function1 Function2 Function3 No. Function1 Function2 Function3 51 SCAN0 SCAN0 SCAN0 81 GND GND GND 52 EP1_DRQB EP1_DRQB EP1_DRQB 82 D13 Reserved D13 53 EP1_RDB EP1_RDB Reserved 83 VDD VDD VDD 54 NC NC NC 84 INT0B INT0B INT0B 55 EP2_DRQB EP2_DRQB EP2_DRQB 85 WRB WRB WRB 56 EP2_WRB EP2_WRB Reserved 86 SCAN1 SCAN1 SCAN1 57 LD1 LD1 Reserved 87 VDD VDD VDD 58 LD5 LD5 Reserved 88 GND GND GND 59 LD8 LD8 Reserved 89 LD0 LD0 Reserved 60 LD10 LD10 Reserved 90 LD3 LD3 Reserved 61 LD12 LD12 Reserved 91 LD6 LD6 Reserved 62 LD14 LD14 Reserved 92 LD4 LD4 Reserved 63 NC NC NC 93 GND GND GND 64 RREF RREF RREF 94 VDD VDD VDD 65 AVDD AVDD AVDD 95 GND GND GND 66 GND GND GND 96 RPU RPU RPU 67 RSDM RSDM RSDM 97 DP DP DP 68 PVSS PVSS PVSS 98 GND GND GND 69 GND GND GND 99 DM DM DM 70 GND GND GND 100 PVDD PVDD PVDD 71 M0 M0 M0 101 VDD VDD VDD 72 NC NC NC 102 GND GND GND 73 GND GND GND 103 CSB CSB CSB 74 XOUT XOUT XOUT 104 A2 Reserved Reserved 75 INTB_ALL ALE ALE 105 A6 Reserved Reserved 76 A5 Reserved Reserved 106 A4 Reserved Reserved 77 GND GND GND 107 D1 AD1 AD1 78 D2 AD2 AD2 108 VDD VDD VDD 79 D4 AD4 AD4 109 GND GND GND 80 D6 AD6 AD6 - - - - Data Sheet S16685EJ2V0DS µPD720122 1. PIN INFORMATION (1/2) Pin Name I/O Buffer Type Active Function Level RESETB I 5 V tolerant Input Schmitt Low Asynchronous reset signaling XIN_CLK I 3.3 V Input System clock input or oscillator In XOUT O 3.3 V Output Oscillator out CSB I 5 V tolerant Input Low Chip select signal INTB_ALL O 5 V tolerant Output Low Interrupt request signal ALE I 5 V tolerant Input High Address strobe signal (Function2/3) A(7:1) I 5 V tolerant Input Address input (Function1) D(15:0) I/O 5 V tolerant I/O Data bus (I/O) (Function1) AD(7:0) I/O 5 V tolerant I/O Address/data multiplexed bus (I/O) (Function2) D0 I/O 5 V tolerant I/O Data bus (I/O) (Function3) AD(7:1) I/O 5 V tolerant I/O Address/data multiplexed bus (I/O) (Function3) D(15:8) I/O 5 V tolerant I/O Data bus (I/O) (Function3) WRB I 5 V tolerant Input Low Write command input RDB I 5 V tolerant Input Low Read command input INT0B O 5 V tolerant Output Low Interrupt request (INT Status 0) INT1B O 5 V tolerant Output Low Interrupt request (INT Status 1) INT2B O 5 V tolerant Output Low Interrupt request (INT Status 2) ACTIVE I 5 V tolerant Input DMA-related pins active level select(Function2/3) SCAN(1:0) I 3.3 V Input 50 kΩ Pull Down Chip test pin. M2 O 5 V tolerant Output Status output pin EP1_DRQB O 5 V tolerant Output Low DMA transfer request output pin of EP1 EP1_DACKB I 5 V tolerant Input Low DMA transfer enable input pin of EP1 EP1_RDB I 5 V tolerant Input Low DMA Read command input pin of EP1 EP1_TCB I 5 V tolerant Input Low DMA terminal count input pin of EP1 FM21 I 3.3 V Input EP2_DRQB O 5 V tolerant Output Low DMA transfer request output pin of EP2 EP2_DACKB I 5 V tolerant Input Low DMA transfer enable input pin of EP2 EP2_WRB I 5 V tolerant Input Low DMA Write command input pin of EP2 EP2_TCB I 5 V tolerant Input Low DMA terminal count input pin of EP2 LD(15:0) I/O 5 V tolerant I/O Data bus (I/O) pin for external local bus BUNRI I 5V torelant Input NEC Electronics test pin RREF A Analog Reference resistor RPU A USB pull-up control USB’s 1.5 kΩ pull-up resistor control RSDP O USB full speed D+ O USB’s full speed D+ signal DP I/O USB high speed D+ I/O USB’s high speed D+ signal DM I/O USB high speed D- I/O USB’s high speed D− signal NEC Electronics test pin Data Sheet S16685EJ2V0DS 9 µPD720122 (2/2) Pin Name RSDM I/O O Buffer Type Active Level USB full speed D- O M(1:0) I 5 V tolerant Input VBUS I 5 V tolerant Input Function USB’s full speed D− signal Function mode setting Note VBUS monitoring AVDD, PVDD 3.3 VDD for Analog circuit VDD 3.3 VDD AVSS, PVSS VSS for Analog circuit VSS, GND VSS NC Not connect Reserved Not used VBUS pin may be used to monitor for VBUS line even if VDD, AVDD, and PVDD are shut off. System must Note ensure that the input voltage level for VBUS pin is less than 3.0 V due to the absolute maximum rating is not exceeded. Remark “5 V tolerant“ means that the buffer is 3.3 V buffer with 5 V tolerant circuit. The operation mode of the BIU can be set by external pins, as shown below. Fix external pins (M1 and M0) when using them. BIU Operation Mode Pin Outline M1 M0 0 0 16-bit mode (Function 1) A 16-bit CPU bus and an external local bus dedicated to data transfer for bulk IN/OUT can be used in this mode. The internal register length is 16 bits. 0 1 8-bit mode (Function 2) Multiplexed bus mode of 8-bit address bus and 8-bit data bus. The register length is 8 bits only in this mode (registers can only be accessed in byte units). Therefore, the address space in this mode differs from that in the other modes. The active levels of some external local bus control pins can be changed by the Active pin. 1 0 16-bit mix mode (Function 3) Multiplexed bus mode of 8-bit address bus and 16-bit data bus. The internal register length is 16 bits. The active levels of some external local bus control pins can be changed by the Active pin. 1 1 Setting prohibited (Function 4) 10 Setting prohibited Data Sheet S16685EJ2V0DS µPD720122 2. 2.1 ELECTRICAL SPECIFICATIONS Buffer List • 3.3 V oscillator interface XIN,XOUT • 3.3 V input buffer FM21,SCAN(1:0) • 5V torelant input buffer RESETB,CSB,A(7:0),WRB,RDB,ACTIVE,EP1_DACKB,EP1_RDB,EP1_TCB,EP2_DACKB,EP2_WRB, EP2_TCB,BUNRI,M0,M1,VBUS,ALE • 5V torelant output buffer INTB_ALL,INT0B,INT1B,INT2B,M2,EP1_DRQB,EP2_DRQB • 5V torelant I/O buffer D(15:0),LD(15:0),AD(7:0),D0,AD(7:1),D(15:8) • USB interface DP,DM,RSDP,RSDM,RREF,RPU 2.2 Terminology Terms Used in Absolute Maximum Ratings Parameter Symbol Meaning Power supply voltage VDD Indicates voltage range within which damage or reduced reliability will not result when power is applied to a VDD pin. Input voltage VI Indicates voltage range within which damage or reduced reliability will not result when power is applied to an input pin. Output voltage VO Indicates voltage range within which damage or reduced reliability will not result when power is applied to an output pin. Output current IO Indicates absolute tolerance value for DC current to prevent damage or reduced reliability when a current flows out of or into an output pin. Operating temperature TA Indicates the ambient temperature range for normal logic operations. Storage temperature Tstg Indicates the element temperature range within which damage or reduced reliability will not result while no voltage or current are applied to the device. Data Sheet S16685EJ2V0DS 11 µPD720122 Terms Used in Recommended Operating Range Parameter Symbol Meaning Power supply voltage VDD Indicates the voltage range for normal logic operations occur when VSS = 0 V. High-level input voltage VIH Indicates the voltage, which is applied to the input pins of the device, is the voltage indicates that the high level states for normal operation of the input buffer. * If a voltage that is equal to or greater than the “Min.” value is applied, the input voltage is guaranteed as high level voltage. Low-level input voltage VIL Indicates the voltage, which is applied to the input pins of the device, is the voltage indicates that the low level states for normal operation of the input buffer. * If a voltage that is equal to or lesser than the “Max.” value is applied, the input voltage is guaranteed as low level voltage. Hysteresys voltage VH Indicates the differential between the positive trigger voltage and the negative trigger voltage. Input rise time tri Indicates allowable input rise time to input pins. Input rise time is transition time from 0.1 × VDD to 0.9 × VDD. Input fall time tfi Indicates allowable input fall time to input pins. Input fall time is transition time from 0.9 × VDD to 0.1 × VDD. Terms Used in DC Characteristics Parameter Symbol Meaning Off-state output leakage current IOZ Indicates the current that flows from the power supply pins when the rated power supply voltage is applied when a 3-state output has high impedance. Output short circuit current IOS Indicates the current that flows when the output pin is shorted (to GND pins) when output is at high-level. Input leakage current II Indicates the current that flows when the input voltage is supplied to the input pin. Low-level output current IOL Indicates the current that flows to the output pins when the rated low-level output voltage is being applied. High-level output current IOH Indicates the current that flows from the output pins when the rated high-level output voltage is being applied. 12 Data Sheet S16685EJ2V0DS µPD720122 2.3 Absolute Maximum Ratings Parameter Symbol Voltage Conditions Ratings Unit −0.5 to +4.6 V VI/VO < VDD+3.0 V −0.5 to +6.6 V VI/VO < VDD+0.3 V −0.5 to +4.6 V 6 mA VDD I/O voltage VI/VO Note 1 Note 2 Output current IO IOL = 6 mA Note 3 Operating ambient temperature TA 0 to +70 °C Storage temperature Tstg −65 to +150 °C Notes 1. 5 V torelant input buffer, output buffer, I/O buffer 2. 3.3 V input buffer,3.3 V oscillator interface 3. 5 V torelant output buffer, I/O buffer(OUT) Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. 2.4 Recommended Operating Range Parameter Symbol Conditions Typ. 3.0 3.3 Max. Unit Power supply voltage VDD 3.6 V Negative trigger voltage VN 0.6 1.8 V Positive trigger voltage VP 1.2 2.4 V Hysteresis voltage VH 0.3 1.5 V Input voltage, low VIL 0 0.8 V Input voltage, high VIH 3.3 V input buffer 2.0 VDD V 5V torelant input buffer, I/O buffer 2.0 5.5 V 0 200 ns Rise/fall time 3.3 V Power Min. tr/tf Data Sheet S16685EJ2V0DS 13 µPD720122 2.5 DC Characteristics The DC characteristics are classified into those of the USB interface and those of the BIU block. 2.5.1 DC characteristics of USB interface Parameter Symbol Serial resistor between DP (DM) and RSDP (RSDM) RS Min. Max. Unit 35.64 36.36 Ω 40.5 49.5 Ω RPU 1.425 1.575 Ω VTERM 3.0 3.6 V High-level input voltage (driven) VIH 2.0 High-level input voltage (floating) VIHZ 2.7 Low-level input voltage VIL Differential input sensitivity VDI (D+) − (D−) 0.2 Differential common mode range VCM Includes VDI range 0.8 2.5 V High-level output voltage VOH RL of 14.25 kΩ to VSS 2.8 3.6 V Low-level output voltage VOL RL of 1.425 kΩ to 3.6 V 0.0 0.3 V Driver output resistance (also serves as high-speed termination) Bus pull-up resistor on upstream facing port Termination voltage for upstream facing port pull-up (full-speed) ZHSDRV Conditions Includes RS resistor Input levels for full-speed: V 3.6 0.8 V V Output levels for full-speed: SE1 VOSE1 0.8 V Output signal crossover voltage VCRS 1.3 2.0 V High-speed squelch detection threshold (differential signal amplitude) VHSSQ 100 150 mV High-speed disconnect detection threshold (differential signal amplitude) VHSDSC 525 625 mV High-speed data signaling common mode voltage range (guideline for receiver) VHSCM −50 500 mV Input levels for high-speed: High-speed differential input signaling level See Figure 2-4 Output levels for high-speed: High-speed idle level VHSOI −10.0 10 mV High-speed data signaling high VHSOH 360 440 mV High-speed data signaling low VHSOL −10.0 10 mV Chirp J level (different voltage) VCHIRPJ 700 1100 mV Chirp K level (different voltage) VCHIRPK −900 −500 mV 14 Data Sheet S16685EJ2V0DS µPD720122 Figure 2-1. Differential Input Sensitivity Range for Low-/Full-Speed Differential input voltage range Differential output crossover voltage range −1.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 4.6 Input voltage range (volts) Figure 2-2. Full-Speed Buffer Voh/Ioh Characteristics for High-Speed Capable Transceiver VDD–3.3 VDD–2.8 VDD–2.3 VDD–1.8 VDD–1.3 VDD–0.8 VDD–0.3 VDD 0 Iout (mA) –20 –40 Min –60 Max –80 Vout (V) Data Sheet S16685EJ2V0DS 15 µPD720122 Figure 2-3. Full-Speed Buffer Vol/Iol Characteristics for High-Speed Capable Transceiver 80 Max Iout (mA) 60 Min 40 20 0 0 0.5 1 1.5 2 2.5 Vout (V) Figure 2-4. Receiver Sensitivity for Transceiver at D+/D− − Level 1 +400 mV differential Point 3 Point 1 Point 4 0V differential Point 2 Point 5 Point 6 –400 mV differential Level 2 0% 16 Unit interval Data Sheet S16685EJ2V0DS 100% 3 µPD720122 Figure 2-5. Receiver Measurement Fixtures Test supply voltage 15.8 Ω USB connector nearest device Vbus D+ DGnd 15.8 Ω 143 Ω 50-Ω Coax 50-Ω Coax + To 50-Ω input of a high-speed differential oscilloscope, or 50-Ω outputs of a high-speed differential data generator – 143 Ω Data Sheet S16685EJ2V0DS 17 µPD720122 2.5.2 DC characteristics of BIU Parameter Off-state output current Symbol IOZ Output short current IOS Input leakage current II Conditions Note VOL = 0.4 V Output current, high IOH VOH = 2.4 V Output voltage, low VOL IOL = 0 mA Output voltage, high VOH IOH = 0 mA 5V-Tolerant Output Data Sheet S16685EJ2V0DS Max. Unit ±10 µA −250 mA µA ±10−5 VI = VDD or GND IOL 18 Typ. VO = VDD or GND Output current, low Note Min. 6 mA −2 mA 0.1 VDD−0.2 V V µPD720122 2.5.3 Pin capacitance Parameter Input capacitance Output/bidirectional capacitance Symbol Conditions Min. Typ. Max. Unit CIN 4.5 6.5 pF COUT 8.5 11 pF Typ. Max. Unit VDD 195 273 mA AVDD 12 17 mA VDD 120 168 mA AVDD 12 17 mA VDD 1.5 2.2 mA AVDD 0.1 0.2 µA VDD 370 520 µA AVDD 0.1 0.2 µA Remark These are just estimated values. 2.5.4 Power consumption Parameter Power consumption Symbol PH PF PS1 PS2 Notes 1. SND PHY Reg. SPND bit = 1 2. SND PHY Reg. SPND bit = 1 Conditions HS mode FS mode Note 1 Suspend mode 1 Note 2 Suspend mode 2 Min. GPR Reg. CONNECTB bit = 0 GPR Reg. PUE bit = 0 BIU Control 0 Reg. OSC_DISCONB bit = 1 Data Sheet S16685EJ2V0DS 19 µPD720122 2.6 AC Characteristics (TA = 0 to +70°°C, VDD = 3.3 V ±10%) The AC characteristics are classified into those of the USB interface block and those of the BIU. 2.6.1 Overall AC characteristics and those of BIU (1) Clock Parameter Symbol Clock frequency fCLK Clock Duty cycle Remarks 1. 2. Condition Min. Typ. Max. Unit X’tal -500ppm 30 +500ppm MHz Oscillator block -500ppm 30 +500ppm MHz 40 50 60 % TDUTY Reccomended accurarcy of clock frequency is ±100ppm. Required accurarcy of X’tal or Oscillator block is includeing initial frequency accuracy, the spread of X’tal capacityor loading, supply voltage, temperature, and aging etc. (2) Reset Symbol TR Specification Reset width Min. 2 HW reset timing RESETB TR 20 Data Sheet S16685EJ2V0DS Typ. Max. Unit µs µPD720122 2.6.2 AC characteristics of BIU block with Function 1 selected (1) CPU BUS read operation Symbol Parameter Min. Typ. Max. Unit T1 Read cycle time 91 ∞ ns T2 Address setup time (RDB↓) 5 ∞ ns T3 Chip select setup time (RDB↓) 5 ∞ ns T4 Buffer direction change time (RDB↓) − 14 ns T5 Output data delay time (RDB↓) − 57 ns ns T6 Read command width 57 ∞ T7 Chip select hold time (RDB↑) 5 ∞ ns T8 Address hold time (RDB↑) 5 ∞ ns T9 RDB inactive time 34 ∞ ns T10 Output data hold time (RDB↑) 4 − ns Remark It is assumed that the external pin capacitance is 15 pF (data bus = 50 pF). CPU bus read timing t1 A7 to A1 VALID t2 t8 CSB t3 t6 t7 RDB WRB t9 t5 High level t10 High level t4 D15 to D0 INVALID VALID Data Sheet S16685EJ2V0DS 21 µPD720122 (2) CPU bus write operation Symbol Parameter Min. Typ. Max. Unit T11 Write cycle time 68 ∞ ns T12 Address setup time (WRB↓) 5 ∞ ns T13 Chip select setup time (WRB↓) 5 ∞ ns T14 Write command width 34 ∞ ns T15 Address hold time (WRB↑) 5 ∞ ns T16 Chip select hold time (WRB↑) 5 ∞ ns T17 WRB inactive time 34 ∞ ns T18 Input data setup time 10 ∞ ns T19 Input data hold time 0 ∞ ns Remark It is assumed that the external pin capacitance is 15 pF (data bus = 50 pF). CPU bus write timing t11 A7 to A1 VALID t12 t15 CSB t13 t16 t14 WRB t17 RDB D15 to D0 22 High level t18 VALID Data Sheet S16685EJ2V0DS t19 µPD720122 (3) CPU BUS RDB vs. WRB timing Symbol T20 Parameter Min. WRB vs. RDB inactive time 34 Typ. Max. Unit ∞ ns Remark It is assumed that the external pin capacitance is 15 pF (data bus = 50 pF). CPU bus read vs. write change timing CSB Low level WRB t20 RDB Data Sheet S16685EJ2V0DS 23 µPD720122 (4) CPU bus DMA transfer (a) CPU bus DMA single mode read transfer timing Symbol Parameter Min. Typ. Max. Unit T21 DMA request acknowledge setup time (RDB↓) 0 ∞ ns T22 DMA request off time (EP1_DACKB↓) − 54 ns T23 DMA single mode read transfer cycle time 91 ∞ ns T24 Read command width 57 ∞ ns T25 Read command inactive time 34 ∞ ns T26 Read data delay time (RDB↓) − 57 ns T27 Buffer direction change time (RDB↓) − 14 ns T28 Read data hold time (RDB↑) 4 − ns T29 EP1_TCB setup time (RDB↓) 0 Note ns T30 EP1_TCB hold time (RDB↓) 17 ∞ ns T31 EP1_STOPB delay time (RDB↓) − 15 ns T32 EP1_STOPB OFF delay time (RDB↑) 3 − ns T33 DMA request acknowledge hold time (RDB↑) 0 ∞ ns Undefined − − ns T34 Note Can be input after previous RDB↑. Remark It is assumed that the external pin capacitance is 15 pF (data bus = 50 pF). (Overall) EP1_DRQB t22 EP1_DACKB t33 t21 t24 RDB t26 D15 to D0 t23 t25 t28 N − 1 cycle 1 cycle N cycle t27 EP1_TCB High level EP1_STOPB High level t31 t32 EP1_STOPB is not asserted in the case of a full packet. 24 Data Sheet S16685EJ2V0DS µPD720122 (Start timing) EP1_DRQB t22 EP1_DACKB t21 t33 t24 t25 RDB t23 t26 D15 to D0 t28 VALID VALID t27 EP1_TCB High level EP1_STOPB High level (End timing) EP1_DRQB t22 EP1_DACKB t33 Last − 1 RDB D15 to D0 Last VALID EP1_TCB High level EP1_STOPB High level VALID t31 t32 EP1_STOPB is not asserted in the case of a full packet. Data Sheet S16685EJ2V0DS 25 µPD720122 (TCB timing) t22 EP1_DRQB EP1_DACKB t21 RDB t29 t30 EP1_TCB 26 Data Sheet S16685EJ2V0DS µPD720122 (b) CPU bus DMA single mode write transfer Symbol Parameter Min. Typ. Max. Unit T35 DMA request acknowledge setup time (WRB↓) 0 ∞ ns T36 DMA request off time (EP2_DACKB↓) − 54 ns T37 DMA single mode write transfer cycle time 88 ∞ ns T38 Write command width 54 ∞ ns T39 Write command inactive time 34 ∞ ns T40 Write data setup time (WRB↑) 10 ∞ ns T41 Write data hold time (WRB↑) 0 ∞ ns T42 EP2_TCB setup time (WRB↓) 0 Note ns T43 EP2_TCB hold time (WRB↓) 17 ∞ ns T44 DMA request acknowledge hold time (WRB↑) 0 ∞ ns Note Can be input after immediately previous WRB↑. Remark It is assumed that the external pin capacitance is 15 pF (data bus = 50 pF). (Overall) EP2_DRQB t36 EP2_DACKB t35 t38 WRB t40 t44 t39 t41 t40 t41 N − 1 cycle 1 cycle D15 to D0 EP2_TCB t44 t37 N cycle High level Data Sheet S16685EJ2V0DS 27 µPD720122 (Start timing) EP2_DRQB t36 EP2_DACKB t35 t44 t38 t39 WRB t37 t40 D15 to D0 EP2_TCB t41 VALID VALID High level (End timing) EP2_DRQB t36 EP2_DACKB t44 Last − 1 WRB Last t41 t40 D15 to D0 EP2_TCB 28 VALID High level Data Sheet S16685EJ2V0DS VALID µPD720122 (TCB timing) t36 EP2_DRQB EP2_DACKB t35 WRB t42 t43 EP2_TCB Data Sheet S16685EJ2V0DS 29 µPD720122 (c) CPU bus DMA demand read transfer timing Symbol Parameter Min. Typ. Max. Unit T45 DMA request acknowledge setup time (RDB↓) 0 ∞ ns T46 DMA demand mode read transfer cycle time 91 ∞ ns T47 Read command width 57 ∞ ns ns T48 Read command inactive time 34 ∞ T49 Read data delay time (RDB↓) − 57 ns T50 Buffer direction change time (RDB↓) − 14 ns T51 Read data hold time (RDB↑) 4 − ns T52 EP1_TCB setup time (RDB↓) 0 Note ns T53 EP1_TCB hold time (RDB↓) 17 ∞ ns T54 EP1_STOPB delay time (RDB↓) − 15 ns T55 EP1_STOPB delay time (RDB↑) 3 − ns T56 DMA request off time (RDB↑) − 59 ns T57 DMA request acknowledge hold time (RDB↑) 0 ∞ ns T69 DMA request off time (EP1_DACKB↓) − 38 ns T71 DMA request off time (EP1_DACKB↓) 1 cycle transfer − 38 ns T72 DMA request on time (EP1_DACKB↑) − 88 ns T74 DMA request off time (RDB↓) − 60 ns Note Can be input after immediately previous RDB↑. Remark It is assumed that the external pin capacitance is 15 pF (data bus = 50 pF). (Overall) EP1_DRQB t56 EP1_DACKB t46 t45 t47 t57 t48 RDB t49 t51 t50 D15 to D0 N − 1 cycle 1 cycle EP1_TCB High level EP1_STOPB High level N cycle t54 t55 EP1_STOPB is not asserted in the case of a full packet. 30 Data Sheet S16685EJ2V0DS µPD720122 (Start timing) EP1_DRQB EP1_DACKB t47 t45 t48 RDB t49 t51 t50 VALID VALID D15 to D0 EP1_TCB High level (End timing) EP1_DRQB t56 EP1_DACKB t57 Last − 1 RDB D15 to D0 Last VALID EP1_TCB High level EP1_STOPB High level VALID t54 t55 EP1_STOPB is not asserted in the case of a full packet. Data Sheet S16685EJ2V0DS 31 µPD720122 (TCB timing) t74 EP1_DRQB EP1_DACKB RDB t53 t52 EP1_TCB (Retransmission timing) DMA transfer retry timing If EP1_DACKB is deasserted without RDB access after EP1_DRQB has been deasserted, EP1_DRQB is asserted again. t72 EP1_DRQB t56 t69 EP1_DACKB Last − 1 RDB D15 to D0 Last VALID EP1_TCB High level EP1_STOPB High level VALID t54 t55 EP1_STOPB is not asserted in the case of a full packet. 32 Data Sheet S16685EJ2V0DS µPD720122 (If EP1_TCB is input when retransmission is executed) t69 EP1_DRQB EP1_DACKB t45 RDB t52 t53 EP1_TCB (One-cycle transfer) EP1_DRQB t71 EP1_DACKB t45 t47 RDB t49 t51 t50 VALID D15 to D0 EP1_TCB High level t54 t55 EP1_STOPB Data Sheet S16685EJ2V0DS 33 µPD720122 (d) CPU bus DMA demand write transfer timing Symbol Parameter Min. DMA request acknowledge setup time (WRB↓) T58 Typ. Max. Unit 0 ∞ ns ns T59 DMA demand mode write transfer cycle time 72 ∞ T60 Write command width 38 ∞ ns T61 Write command inactive time 34 ∞ ns T62 Write data setup time (WRB↑) 10 ∞ ns T63 Write data hold time (WRB↑) 0 ∞ ns T64 EP2_TCB setup time (WRB↓) 0 Note ns T65 EP2_TCB hold time (WRB↓) 17 ∞ ns T66 DMA request off time (WRB↑) − 60 ns T67 DMA request acknowledge hold time (WRB↑) 0 ∞ ns T70 DMA request off time (EP2_DACKB↓) − 38 ns T73 DMA request on time (EP2_DACKB↑) − 88 ns T75 DMA request off time (WRB↓) − 60 ns Note Can be input after immediately previous WRB↑. Remark It is assumed that the external pin capacitance is 15 pF (data bus = 50 pF). (Overall) EP2_DRQB t66 EP2_DACKB t59 t58 t67 t61 t60 WRB t62 D15 to D0 EP2_TCB 34 t63 N − 1 cycle 1 cycle High level Data Sheet S16685EJ2V0DS N cycle µPD720122 (Start timing) EP2_DRQB EP2_DACKB t60 t58 t61 WRB t62 D15 to D0 EP2_TCB t63 VALID VALID High level (End timing) t66 EP2_DRQB t67 EP2_DACKB WRB Last − 1 Last t62 D15 to D0 t63 VALID VALID EP2_TCB Data Sheet S16685EJ2V0DS 35 µPD720122 (TCB timing) t75 EP2_DRQB EP2_DACKB WRB t64 t65 EP2_TCB (Retransmission timing) DMA transfer retry timing If EP2_DACKB is deasserted without WRB access after EP2_DRQB has been deasserted, EP2_DRQB is asserted again. t73 EP2_DRQB Last − 1 WRB t62 D15 to D0 EP2_TCB 36 t70 t66 EP2_DACKB Last t63 VALID VALID High level Data Sheet S16685EJ2V0DS µPD720122 (If EP1_TCB is input when retransmission is executed) t70 EP2_DRQB EP2_DACKB t58 WRB t64 EP2_TCB t65 Data Sheet S16685EJ2V0DS 37 µPD720122 (a) CPU bus DMA read transfer vs. write transfer timing Symbol T68 Parameter Min. RDB vs. WRB command inactive time 34 Remark It is assumed that the external pin capacitance is 15 pF (data bus = 50 pF). EP1_DRQB Low level EP1_DACKB t45 t57 RDB Low level EP2_DRQB EP2_DACKB t68 WRB t58 38 Data Sheet S16685EJ2V0DS Typ. Max. Unit ∞ ns µPD720122 2.6.3 AC characteristics of BIU block with function 2 or 3 selected (1) CPU bus read operation Symbol Parameter Min. Typ. Max. Unit TB1 Read cycle time 86 ∞ ns TB2 Address setup time (ALE↓) 10 ∞ ns TB3 Chip select setup time (ALE↓) 17 ∞ ns TB4 Read command delay time (ALE↓) 7 ∞ ns TB5 Output data delay time (RDB↓) − 57 ns ns TB6 Read command width 57 ∞ TB7 Output data hold time (RDB↑) 4 − ns TB8 Chip select hold time (RDB↑) 5 ∞ ns TB9 ALE width 10 ∞ ns TB10 Address hold time (ALE↓) 0 ∞ ns TB11 Chip select setup time (RDB↓) 5 ∞ ns TB12 Buffer direction change time (RDB↓) − 14 ns Remark It is assumed that the external pin capacitance is 15 pF (data bus = 50 pF). CPU bus read timing DATA invalid tb1 AD7 to AD0Note D15 to D8 ADDRES VALID tb2 ALE tb10 tb9 ADDRES VALID DATA VALID tb12 tb7 tb5 tb3 tb8 tb11 CSB tb4 tb6 RDB Note D7 to D0 for Function 2 Data Sheet S16685EJ2V0DS 39 µPD720122 (2) CPU bus write operation Symbol Parameter Min. Typ. Max. Unit ns TB13 Write cycle time 58 ∞ TB14 Address setup time (ALE↓) 17 ∞ ns TB15 Chip select setup time (ALE↓) 17 ∞ ns TB16 Write command delay time (ALE↓) 7 ∞ ns TB17 Input data setup time (WRB↑) 10 ∞ ns TB18 Input data hold time (WRB↑) 0 ∞ ns TB19 Write command width 34 ∞ ns TB20 Chip select hold time (WRB↑) 0 ∞ ns TB21 Chip select setup time (WRB↓) 5 ∞ ns Remark It is assumed that the external pin capacitance is 15 pF (data bus = 50 pF). CPU bus write timing tb13 AD7 to AD0Note D15 to D8 ADDRESS VALID ADDRESS VALID DATA VALID tb2 tb10 tb17 tb18 ALE tb9 tb15 CSB tb20 tb21 tb16 tb19 WRB Note 40 D7 to D0 for Function 2 Data Sheet S16685EJ2V0DS µPD720122 2.6.4 External local bus (1) External local bus 16-bit mode (a) External local bus 16-bit mode DMA single mode read transfer timing Symbol Parameter Min. Typ. Max. Unit L16T21 DMA request acknowledge setup time (EP1_RDB↓) 0 ∞ ns L16T22 DMA request off time 1 (EP1_DACKB↓) − 54 ns L16T23 DMA single mode read transfer cycle time 91 ∞ ns ns L16T24 Read command width 57 ∞ L16T25 Read command inactive time 34 ∞ ns L16T26 Read data delay time (EP1_RDB↓) − 57 ns L16T27 Buffer direction change time (EP1_RDB↓) − 14 ns L16T28 Read data hold time (EP1_RDB↑) 4 − ns L16T29 EP1_TCB setup time (EP1_RDB↓) 0 Note ns L16T30 EP1_TCB hold time (EP1_RDB↓) 17 ∞ ns L16T31 EP1_STOPB delay time (EP1_RDB↓) − 15 ns L16T32 EP1_STOPB delay time (EP1_RDB↑) 3 − ns L16T33 DMA request acknowledge hold time (EP1_RDB↑) 0 ∞ ns L16T34 Undefined − − ns Note Can be input after previous EP1_RDB↑. Remark It is assumed that the external pin capacitance is 15 pF (data bus = 50 pF). Data Sheet S16685EJ2V0DS 41 µPD720122 (Overall) L16t22 EP1_DRQB L16t21 L16t33 EP1_DACKB L16t24 L16t25 EP1_RDB L16t23 L16t28 L16t26 LD15 to LD0 N − 1 cycle 1 cycle N cycle L16t27 EP1_TCB High level L16t31 EP1_STOPB L16t32 High level EP1_STOPB is not asserted in the case of a full packet. (Start timing) L16t22 EP1_DRQB L16t33 L16t21 EP1_DACKB L16t24 L16t25 EP1_RDB L16t23 L16t26 L16t28 VALID LD15 to LD0 L16t27 EP1_TCB 42 High level Data Sheet S16685EJ2V0DS VALID µPD720122 (End timing) L16t22 EP1_DRQB L16t33 EP1_DACKB Last − 1 EP1_RDB LD15 to LD0 EP1_TCB EP1_STOPB Last VALID VALID High level L16t31 L16t32 High level EP1_STOPB is not asserted in the case of a full packet. (TCB timing) L16T22 EP1_DRQB EP1_DACKB L16T21 EP1_RDB L16T29 EP1_TCB L16T30 Data Sheet S16685EJ2V0DS 43 µPD720122 (a) External local bus 16-bit mode DMA single mode write transfer Symbol Parameter Min. Typ. Max. Unit L16T35 DMA request acknowledge setup time (EP2_WRB↓) 0 ∞ ns L16T36 DMA request off time 1 (EP2_DACKB↓) − 54 ns L16T37 DMA single mode write transfer cycle time 88 ∞ ns L16T38 Write command width 54 ∞ ns L16T39 Write command inactive time 34 ∞ ns L16T40 Write data setup time (EP2_WRB↑) 10 ∞ ns L16T41 Write data hold time (EP2_WRB↑) 0 ∞ ns L16T42 EP2_TCB setup time (EP2_WRB↓) 0 Note ns L16T43 EP2_TCB hold time (EP2_WRB↓) 17 ∞ ns L16T44 DMA request acknowledge hold time (EP2_WRB↑) 0 ∞ ns Note Can be input after previous EP2_WRB↑. Remark It is assumed that the external pin capacitance is 15 pF (data bus = 50 pF). (Overall) L16t36 EP2_DRQB L16t44 L16t35 EP2_DACKB L16t37 L16t38 L16t39 EP2_WRB L16t40 L16t40 EP2_TCB 44 N − 1 cycle 1 cycle LD15 to LD0 L16t41 L16t41 High level Data Sheet S16685EJ2V0DS N cycle µPD720122 (Start timing) L16t36 EP2_DRQB EP2_DACKB L16t44 L16t35 L16t38 L16t39 EP2_WRB L16t37 L16t40 VALID LD15 to LD0 EP2_TCB L16t41 VALID High level (End timing) L16t36 EP2_DRQB EP2_DACKB L16t44 Last − 1 EP2_WRB L16t40 LD15 to LD0 EP2_TCB Last L16t41 VALID VALID High level Data Sheet S16685EJ2V0DS 45 µPD720122 (TCB timing) L16t36 EP2_DRQB EP2_DACKB L16t35 EP2_WRB EP2_TCB 46 L16t42 L16t43 Data Sheet S16685EJ2V0DS µPD720122 (c) External local bus 16-bit mode DMA demand read transfer timing Symbol L16T45 Parameter Min. DMA request acknowledge setup time (EP1_RDB↓) Typ. Max. Unit 0 ∞ ns ns L16T46 DMA demand mode read transfer cycle time 91 ∞ L16T47 Read command width 57 ∞ ns L16T48 Read command inactive time 34 ∞ ns L16T49 Read data delay time (EP1_RDB↓) − 57 ns L16T50 Buffer direction change time (EP1_RDB↓) − 14 ns L16T51 Read data hold time (EP1_RDB↑) 4 − ns L16T52 EP1_TCB setup time (EP1_RDB↓) 0 Note ns L16T53 EP1_TCB hold time (EP1_RDB↓) 17 ∞ ns L16T54 EP1_STOPB delay time (EP1_RDB↓) − 15 ns L16T55 EP1_STOPB delay time (EP1_RDB↑) 3 − ns L16T56 DMA request off time (EP1_RDB↑) − 59 ns L16T57 DMA request acknowledge hold time (EP1_RDB↑) 0 ∞ ns L16T69 DMA request off time (EP1_DACKB↓) − 38 ns L16T71 DMA request off time (EP1_DACKB↓) 1 cycle transfer − 38 ns L16T72 DMA request on time (EP1_DACKB↑) − 88 ns L16T74 DMA request off time (EP1_RDB↓) − 60 ns Note Can be input after immediately previous EP1_RDB↑. Remark It is assumed that the external pin capacitance is 15 pF (data bus = 50 pF). Data Sheet S16685EJ2V0DS 47 µPD720122 (Overall) EP1_DRQB L16t56 EP1_DACKB L16t46 L16t45 L16t47 L16t48 L16t49 L16t51 L16t57 EP1_RDB N − 1 cycle 1 cycle LD15 to LD0 N cycle L16t50 EP1_TCB High Level EP1_STOPB High Level L16t54 L16t55 EP1_STOPB is not asserted in the case of a full packet. (Start timing) EP1_DRQB EP1_DACKB L16t45 L16t47 L16t48 EP1_RDB L16t46 L16t49 L16t51 L16t50 LD15 to LD0 EP1_TCB 48 VALID High level Data Sheet S16685EJ2V0DS VALID µPD720122 (End timing) EP1_DRQB L16t56 EP1_DACKB L16t57 Last − 1 EP1_RDB VALID LD15 to LD0 EP1_TCB Last VALID High level L16t54 EP1_STOPB High level L16t55 EP1_STOPB is not asserted in the case of a full packet. (TCB timing) L16t74 EP1_DRQB EP1_DACKB EP1_RDB L16t52 L16t53 EP1_TCB Data Sheet S16685EJ2V0DS 49 µPD720122 (Retransmission timing) DMA transfer retry timing If EP1_DACKB is deasserted without RDB access after EP1_DRQB has been deasserted, EP1_DRQB is asserted again. However, note that the retry operation cannot be performed in the 8-bit mode. L16t72 EP1_DRQB L16t56 L16t69 EP1_DACKB EP1_RDB Last − 1 LD15 to LD0 Last VALID EP1_TCB High level EP1_STOPB High level VALID L16t54 L16t55 EP1_STOPB is not asserted in the case of a full packet. (If EP1_TCB is input when retransmission is executed) L16t69 EP1_DRQB L16t45 EP1_DACKB EP1_RDB L16t52 L16t53 EP1_TCB 50 Data Sheet S16685EJ2V0DS µPD720122 (One-cycle transfer) EP1_DRQB L16t71 EP1_DACKB L16t45 L16t47 EP1_RDB L16t50 L16t49 L16t51 VALID LD15 to LD0 EP1_TCB High level L16t54 L16t55 EP1_STOPB Data Sheet S16685EJ2V0DS 51 µPD720122 (d) External local bus 16-bit mode DMA demand write transfer timing Symbol Parameter Min. DMA request acknowledge setup time (EP2_WRB↓) L16T58 Typ. Max. Unit 0 ∞ ns ns L16T59 DMA demand mode write transfer cycle time 72 ∞ L16T60 Write command width 38 ∞ ns L16T61 Write command inactive time 34 ∞ ns L16T62 Write data setup time (EP2_WRB↑) 10 ∞ ns L16T63 Write data hold time (EP2_WRB↑) 0 ∞ ns L16T64 EP2_TCB setup time (EP2_WRB↓) 0 Note ns L16T65 EP2_TCB hold time (EP2_WRB↓) 17 ∞ ns L16T66 DMA request off time (EP2_WRB↑) − 60 ns L16T67 DMA request acknowledge hold time (EP2_WRB↑) 0 ∞ ns L16T70 DMA request off time (EP2_DACKB↓) − 38 ns L16T73 DMA request on time (EP2_DACKB↑) − 88 ns L16T75 DMA request off time (EP2_WRB↓) − 60 ns Note Can be input after previous EP2_WRB↑. Remark It is assumed that the external pin capacitance is 15 pF (data bus = 50 pF). (Overall) EP2_DRQB L16t66 EP2_DACKB L16t59 L16t58 L16t60 L16t61 L16t67 EP2_WRB L16t62 LD15 to LD0 L16t63 N − 1 cycle 1 cycle EP2_TCB High level 52 Data Sheet S16685EJ2V0DS N cycle µPD720122 (Start timing) EP2_DRQB EP2_DACKB L16t58 L16t59 L16t60 EP2_WRB L16t61 L16t63 L16t62 VALID LD15 to LD0 EP2_TCB VALID High level (End timing) L16t66 EP2_DRQB L16t67 EP2_DACKB Last − 1 EP2_WRB Last L16t62 VALID LD15 to LD0 EP2_TCB L16t63 VALID High level Data Sheet S16685EJ2V0DS 53 µPD720122 (TCB timing) L16t75 EP2_DRQB EP2_DACKB EP2_WRB L16t64 L16t65 EP2_TCB (Retransmission timing) DMA transfer retry timing If EP2_DACKB is deasserted without RDB access after EP2_DRQB has been deasserted, EP2_DRQB is asserted again. However, note that the retry operation cannot be performed in the 8-bit mode. L16t73 EP2_DRQB L16t70 L16t66 EP2_DACKB EP2_WRB Last − 1 Last L16t62 LD15 to LD0 EP2_TCB 54 L16t63 VALID VALID High level Data Sheet S16685EJ2V0DS µPD720122 (If EP1_TCB is input when retransmission is executed) L16t70 EP2_DRQB EP2_DACKB L16t58 EP2_WRB L16t64 L16t65 EP2_TCB (e) External local bus 16-bit mode DMA EP1_Read transfer vs. EP2_Write transfer timing Symbol L16T68 Parameter Min. EP1_RDB vs. EP2_WRB command inactive time 34 Typ. Max. Unit ∞ ns Remark It is assumed that the external pin capacitance is 15 pF (data bus = 50 pF). EP1_DRQB Low level EP1_DACKB L16t45 L16t57 EP1_RDB EP2_DRQB Low level EP2_DACKB L16t68 EP2_WRB L16t58 Data Sheet S16685EJ2V0DS 55 µPD720122 (2) External local bus 8-bit mode (a) External local bus 8-bit mode DMA single mode read transfer timing Symbol Parameter Min. Typ. Max. Unit L8T21 DMA request acknowledge setup time (EP1_RDB↓) 0 ∞ ns L8T22 DMA request off time 1 (EP1_DACKB↓) − 10 ns L8T23 DMA single mode read transfer cycle time 91 ∞ ns L8T24 Read command width 57 ∞ ns L8T25 Read command inactive time 34 ∞ ns L8T26 Read data delay time (EP1_RDB↓) − 57 ns L8T27 Buffer direction change time (EP1_RDB↓) − 14 ns L8T28 Read data hold time (EP1_RDB↑) 4 − ns L8T31 EP1_STOPB delay time (EP1_RDB↓) − 15 ns L8T32 EP1_STOPB delay time (EP1_RDB↑) 3 − ns L8T33 DMA request acknowledge hold time (EP1_RDB↑) 0 ∞ ns L8T34 Undefined − − ns Remarks 1. Use of EP1_TCB is prohibited in the 8-bit external local bus mode. Clamp this signal to the inactive status. 2. LD15 to 8 are undefined in the 8-bit external local bus mode (these signals are invalid when input and undefined when output). 3. It is assumed that the external pin capacitance is 15 pF (data bus = 50 pF). (Overall) EP1_DRQB L8t22 EP1_DACKB L8t23 L8t21 L8t24 EP1_RDB L8t25 L8t26 LD7 to LD0 L8t33 L8t28 N − 1 cycle 1 cycle N cycle L8t27 EP1_TCB High level EP1_STOPB High level L8t31 L8t32 EP1_STOPB is not asserted in the case of a full packet. 56 Data Sheet S16685EJ2V0DS µPD720122 (Start timing) EP1_DRQB L8t22 L8t33 L8t21 EP1_DACKB L8t23 L8t24 L8t25 EP1_RDB L8t28 L8t26 VALID LD7 to LD0 VALID L8t27 EP1_TCB High level (End timing) EP1_DRQB L8t22 EP1_DACKB L8t33 Last − 1 EP1_RDB Last VALID LD7 to LD0 EP1_TCB High level EP1_STOPB High level VALID L8t31 L8t32 EP1_STOPB is not asserted in the case of a full packet. Data Sheet S16685EJ2V0DS 57 µPD720122 (b) External local bus 8-bit mode DMA single mode write transfer Symbol Parameter Min. Typ. Max. Unit ∞ ns L8T35 DMA request acknowledge setup time (EP2_WRB↓) 0 L8T36 DMA request off time 1 (EP2_DACKB↓) − L8T37 DMA single mode write transfer cycle time 88 ∞ ns L8T38 Write command width 54 ∞ ns L8T39 Write command inactive time 34 ∞ ns L8T40 Write data setup time (EP2_WRB↑) 10 ∞ ns L8T41 Write data hold time (EP2_WRB↑) 0 ∞ ns L8T44 DMA request acknowledge hold time (EP2_WRB↑) 0 ∞ ns Remarks 1. Note 54 ns Use of EP1_TCB is prohibited in the 8-bit external local bus mode. Clamp this signal to the inactive status. 2. LD15 to 8 are undefined in the 8-bit external local bus mode (these signals are invalid when input and undefined when output). 3. Note It is assumed that the external pin capacitance is 15 pF (data bus = 50 pF). The difference in specifications when compared with L8T22 is that BIU processing is performed for EP1 and that EPC2 processing is performed for EP2. (Overall) EP2_DRQB L8t36 L8t44 L8t35 EP2_DACKB L8t37 L8t44 L8t39 L8t38 EP2_WRB L8t40 58 L8t41 N − 1 cycle 1 cycle LD7 to LD0 EP2_TCB L8t40 L8t41 High Level Data Sheet S16685EJ2V0DS N cycle µPD720122 (Start timing) EP2_DRQB L8t36 L8t44 L8t35 EP2_DACKB L8t37 L8t38 L8t39 EP2_WRB L8t40 L8t41 LD7 to LD0 EP2_TCB VALID VALID High level (End timing) EP2_DRQB L8t36 EP2_DACKB L8t44 Last − 1 EP2_WRB Last L8t40 LD7 to LD0 EP2_TCB L8t41 VALID VALID High level Data Sheet S16685EJ2V0DS 59 µPD720122 (c) External local bus 8-bit mode DMA demand read transfer timing Symbol L8T45 Parameter Min. DMA request acknowledge setup time (EP1_RDB↓) Typ. Max. Unit 0 ∞ ns ns L8T46 DMA demand mode read transfer cycle time 90 ∞ L8T47 Read command width 56 ∞ ns L8T48 Read command inactive time 34 ∞ ns L8T49 Read data delay time (EP1_RDB↓) − 56 ns L8T50 Buffer direction change time (EP1_RDB↓) − 14 ns L8T51 Read data hold time (EP1_RDB↑) 4 − ns L8T54 EP1_STOPB delay time (EP1_RDB↓) − 15 ns L8T55 EP1_STOPB delay time (EP1_RDB↑) 3 − ns L8T56 DMA request off time (EP1_RDB↑) − 60 ns L8T57 DMA request acknowledge hold time (EP1_RDB↑) 0 ∞ ns Remarks 1. Use of EP1_TCB is prohibited in the 8-bit external local bus mode. Clamp this signal to the inactive status. 2. LD15 to 8 are undefined in the 8-bit external local bus mode (these signals are invalid when input and undefined when output). 3. It is assumed that the external pin capacitance is 15 pF (data bus = 50 pF). (Overall) EP1_DRQB L8t45 L8t56 EP1_DACKB L8t46 L8t57 L8t48 L8t47 EP1_RDB L8t51 L8t49 N − 1 cycle 1 cycle LD7 to LD0 N cycle L8t50 EP1_TCB High level EP1_STOPB High level L8t54 L8t55 EP1_STOPB is not asserted in the case of a full Packet. 60 Data Sheet S16685EJ2V0DS µPD720122 (Start timing) EP1_DRQB L8t45 EP1_DACKB L8t47 L8t48 EP1_RDB L8t49 L8t51 L8t50 VALID VALID LD7 to LD0 EP1_TCB High level (End timing) EP1_DRQB L8t57 L8t56 EP1_DACKB Last − 1 EP1_RDB Last VALID LD7 to LD0 EP1_TCB High level EP1_STOPB High level VALID L8t54 L8t55 EP1_STOPB is not asserted in the case of a full packet. Data Sheet S16685EJ2V0DS 61 µPD720122 (d) External local bus 8-bit mode DMA demand write transfer timing Symbol L8T58 Parameter Min. DMA request acknowledge setup time (EP2_WRB↓) Typ. Max. Unit 0 ∞ ns ns L8T59 DMA demand mode write transfer cycle time 72 ∞ L8T60 Write command width 38 ∞ ns L8T61 Write command inactive time 34 ∞ ns L8T62 Write data setup time (EP2_WRB↑) 10 ∞ ns L8T63 Write data hold time (EP2_WRB↑) 0 ∞ ns L8T66 DMA request off time (EP2_WRB↑) − 60 ns L8T67 DMA request acknowledge hold time (EP2_WRB↑) 0 ∞ ns Remarks 1. Use of EP1_TCB is prohibited in the 8-bit external local bus mode. Clamp this signal to the inactive status. 2. LD15 to 8 are undefined in the 8-bit external local bus mode (these signals are invalid when input and undefined when output). 3. It is assumed that the external pin capacitance is 15 pF (data bus = 50 pF). (Overall) EP2_DRQB L8t67 L8t66 EP2_DACKB L8t59 L8t58 L8t60 L8t61 EP2_WRB L8t62 LD7 to LD0 EP2_TCB 62 L8t62 L8t63 L8t63 N − 1 cycle 1 cycle High level Data Sheet S16685EJ2V0DS N cycle µPD720122 (Start timing) EP2_DRQB L8t58 EP2_DACKB L8t59 L8t60 L8t61 EP2_WRB L8t62 LD7 to LD0 EP2_TCB L8t63 VALID VALID High level (End timing) L8t66 EP2_DRQB L8t67 EP2_DACKB EP2_WRB Last − 1 Last L8t63 L8t62 LD7 to LD0 VALID VALID EP2_TCB Data Sheet S16685EJ2V0DS 63 µPD720122 (e) External local bus 8-bit mode DMA EP1_Read transfer vs. EP2_Write transfer timing Symbol L8T68 Parameter Min. EP1_RDB vs. EP2_WRB command inactive time 34 Remark It is assumed that the external pin capacitance is 15 pF (data bus = 50 pF). EP1_DRQB Low level EP1_DACKB L8t45 L8t57 EP1_RDB EP2_DRQB Low level EP2_DACKB L8t68 EP2_WRB L8t58 64 Data Sheet S16685EJ2V0DS Typ. Max. Unit ∞ ns µPD720122 2.6.5 USB interface timing Parameter Symbol Conditions Min. Max. Unit Full-speed source electrical characteristics Rise time TFR CL = 50 pF, RS = 36 Ω 4 20 ns Fall time TFF CL = 50 pF, RS = 36 Ω 4 20 ns Differential rise and fall time matching TFRFM (TFR/TFF) 90 111.11 % Full-speed data rate for hubs and devices that are high-speed capable TFDRATHS Average bit rate 11.9940 12.0060 Mb/s Frame interval TFRAME 0.9995 1.0005 ms Consecutive frame interval jitter TRFI 42 ns Source jitter total (including frequency tolerance): To next transition For paired transitions TDJ1 TDJ2 −3.5 −4.0 3.5 4.0 ns ns −2 5 ns −18.5 −9 18.5 9 ns ns 175 ns Source jitter for differential transition to SE0 transition No clock adjustment TFDEOP Receiver jitter: To next transition For paired transitions TJR1 TJR2 Source SE0 interval of EOP TFEOPT 160 Receiver SE0 interval of EOP TFEOPR 82 Width of SE0 interval during differential transition TFST ns 14 ns High-speed source electrical characteristics Rise time (10% to 90%) THSR 500 ps Fall time (10% to 90%) THSF 500 ps Driver waveform requirements See Figure 2-6 High-speed data rate THSDRAT 479.760 480.240 Mb/s Microframe interval THSFRAM 124.9375 125.0625 µs Consecutive microframe interval difference THSRFI 4 high-speed Bit times Data source jitter See Figure 2-6. Receiver jitter tolerance See Figure 2-4. Data Sheet S16685EJ2V0DS 65 µPD720122 Parameter Symbol Conditions Min. Max. Unit TSIGATT 100 ms Debounce interval provided by USB system software after attach TATTDB 100 ms Inter-packet delay (for low-/full-speed) TIPD Inter-packet delay for device response w/detachable cable for low-/full-speed TRSPIPD1 High-speed detection start time from suspend TSCA 2.5 Sample time for suspend vs. reset TCSR 100 Power down under suspend TSUS SUSPEND set time (SPNDOUT) TSSP 0 − SUSPEND clear time (RSUMOUT) TCSP 0 − Reversion time from suspend to high-speed TRHS SUSPEND setup time (RSUMIN) TSRW 0 − RSUMIN active pulse width TRWP 1 15 Drive chirp K width TCKO 1 Finish chirp K assertion TFCA 7 ms Start sequencing chirp K-J-K-J-K-J TSSC 100 µs Finish sequencing chirp K-J TFSC −500 −100 µs Detect sequencing chirp K-J width TCSI 2.5 Sample time for sequencing chirp TSCS 1.0 Reversion time to high-speed TRHA High-speed detection start time THDS 2.5 Reset completed time TDRS 10 Device event timing Time from internal power good to device pulling D+/D− beyond VIHZ (min.) (signaling attach) 66 2 Bit times 6.5 µs 875 µs 10 ms 1.333 Data Sheet S16685EJ2V0DS Bit times µs ms ms µs 2.5 ms 500 µs 3000 µs ms µPD720122 Figure 2-6. Transmit Waveform for Transceiver at D+/D− − Level 1 +400 mV differential Point 3 Point 4 Point 1 0V differential Point 2 Point 5 Point 6 –400 mV differential Level 2 Unit interval 0% 100% Figure 2-7. Transmitter Measurement Fixtures Test supply voltage 15.8 Ω USB connector nearest device Vbus D+ D– Gnd 15.8 Ω 143 Ω 50 Ω Coax 50 Ω Coax + To 50-Ω input of a high-speed differential oscilloscope, or 50-Ω output of a high speed differential data generator – 143 Ω Data Sheet S16685EJ2V0DS 67 µPD720122 (1) Power-on and connection events Figure 2-8. Power-on and Connection Event Timing Hub port power OK Reset recovery time Attach detected Hub port power-on ≥ 4.01 V ∆t4 ∆t5 VBUS USB system software reads device speed VIH(min) VIH D+ or D− ∆t1 10 ms 100 ms TSIGATT 100 ms TATTDB (2) USB signals Figure 2-9. USB Differential Data Jitter for Full-Speed TPERIOD Differential data lines Crossover points Consecutive transitions N * TPERIOD + TxDJ1 Paired transitions N * TPERIOD + TxDJ2 68 Data Sheet S16685EJ2V0DS ∆t6 µPD720122 Figure 2-10. USB Differential-to-EOP Transition Skew and EOP Width for Full-Speed TPERIOD Differential data lines Crossover point Crossover point extended Diff. Data-toSE0 skew N * TPERIOD + TxDEOP Source EOP width: TFEOPT TLEOPT Receiver EOP width: TFEOPR, TLEOPR Data Sheet S16685EJ2V0DS 69 µPD720122 Figure 2-11. USB Receiver Jitter Tolerance for Full-Speed TPERIOD Differential data lines TxJR TxJR1 TxJR2 Consecutive transitions N * TPERIOD + TxJR1 Paired transitions N * TPERIOD + TxJR2 (3) USB connection sequence on USB1.1 bus The PHY core implemented on the µPD720122 automatically determines the Up port. Check the SP_MODE bit (SP_MODE) of the Int Status 2 register after an EPC2_STG bus reset interrupt has occurred to determine whether the USB is connected to FS or HS. Figure 2-12. USB Connection Sequence on USB 1.1 Bus USB bus Pull-up is active. Reversion to full-speed mode Chirp K device out FS J FS J tHDS tSCA tCKO tCKI tFCA tDRS T0 USBRST SPMODE 70 High Data Sheet S16685EJ2V0DS tSCS µPD720122 (4) USB connection sequence on USB 2.0 bus Figure 2-13. USB Connection Sequence on USB 2.0 Bus Chirp state from host/hub Pull-up is active. USB bus Reversion to high-speed mode Chirp K device out K FS J tHDS tCKO tCKI tSCA tSSC J K J K J tCSO tCSI K Reset Complete J tRHA tFCA tFSC tSCS T0 USBRST SPMODE (5) Bus reset sequence (1) The bus reset sequence when connected to a USB 1.1 bus is shown below. Figure 2-14. Bus Reset Sequence (1) Pull-up is inactive. Reversion to full-speed mode Chirp K device out High-speed packet USB bus FS J tSPD tCSR tCKO tCKI tSCA tSCS tFCA tDRS T0 USBRST SPMODE Data Sheet S16685EJ2V0DS 71 µPD720122 (6) Bus reset sequence (2) The bus reset sequence when connected to a USB 2.0 bus is shown below. Figure 2-15. Bus Reset Sequence (2) Pull-up is inactive High-speed packet Reversion to full-speed mode K USB bus tSPD tCSR tSCA tFCA tCKO tCKI tSSC J K tCSO tCSI J K J K Reset Complete J tRHA tSCS T0 USBRST SPMODE 72 Reversion to high-speed mode Chirp state from host/hub Chirp K device out Data Sheet S16685EJ2V0DS tFSC µPD720122 (7) USB reset from suspend state (1) Figure 2-16. USB Reset from Suspend State (1) USB bus Pull-up is active. Chirp K device out FS J FS J tCKO tCKI tSCA tSCS tFCA tDRS T0 USB_RST SPMODE (8) USB reset from suspend state (2) Figure 2-17. USB Reset from Suspend State (2) Pull-up is inactive. USB bus K FS J tCKO tCKI tSCA tFCA tSSC Reversion to high-speed mode Chirp state from host/hub Chirp K device out J K tCSO tCSI J K J K Reset Complete J tRHA tSCS tFSC T0 USBRST SPMODE Data Sheet S16685EJ2V0DS 73 µPD720122 (9) Suspend and resume on USB1.1 bus Figure 2-18. Suspend and Resume on USB 1.1 Bus FS EOP USB bus FS J tSPD FS K FS J Current source and PLL, etc. are disabled. tSUS SPNDOUT SUSPEND tSSP RSUMOUT tCSP SPMODE High 74 Data Sheet S16685EJ2V0DS Note time required to relock PLL and stabilize oscillator. µPD720122 (10) Suspend and resume on USB2.0 bus Figure 2-19. Suspend and Resume on USB 2.0 Bus Reversion to high-speed mode Reversion to full-speed mode High-speed packet High-speed packet USB bus FS K FS J tSPD tCSR tRHS Current source and PLL, etc. are disabled. tSUS T0 SPNDOUT SUSPEND tSSP RSUMOUT tCSP Note time required to relock PLL and stabilize oscillator. Low SPMODE (11) Remote wakeup on USB1.1 Figure 2-20. Remote Wakeup on USB 1.1 FS EOP USB bus FS K FS J FS J tSPD tSUS SPNDOUT SUSPEND tSSP RSUMOUT Current source and PLL, etc. are disabled. RSUMIN tRWP SPMODE High tSRW Data Sheet S16685EJ2V0DS 75 µPD720122 (12) Remote wakeup on USB2.0 Figure 2-21. Remote Wakeup on USB 2.0 Reversion to full-speed mode Reversion to high-speed mode High-speed packet High-speed packet USB bus FS K FS J tSPD tCSR tRHS tSUS T0 SPNDOUT SUSPEND tSSP RSUMOUT Current source and PLL, etc. are disabled. RSUMIN tRWP SPEEDMODE 76 Low tSRW Data Sheet S16685EJ2V0DS µPD720122 3. PACKAGE DRAWING 100-PIN PLASTIC TQFP (FINE PITCH) (14x14) A B 75 76 51 50 detail of lead end S C D P T R 100 1 26 25 L U Q F J G H I M K S N S M NOTE Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition. ITEM A B MILLIMETERS 16.0±0.2 14.0±0.2 C 14.0±0.2 D F 16.0±0.2 1.0 G 1.0 H 0.22±0.05 I 0.08 J K 0.5 (T.P.) 1.0±0.2 L 0.5 M 0.17 +0.03 −0.07 N 0.08 P 1.0 Q 0.1±0.05 R 3° +4° −3° S 1.1±0.1 T 0.25 U 0.6±0.15 P100GC-50-9EU Data Sheet S16685EJ2V0DS 77 µPD720122 109-PIN PLASTIC FBGA (11x11) D w S A ZD ZE A 12 11 10 9 8 7 6 5 4 3 2 1 B E M L K J H G F E D C B A w S B INDEX MARK (UNIT:mm) A y1 A2 S S y e S φb A1 φx M S AB ITEM D DIMENSIONS 11.00±0.10 E 11.00±0.10 w 0.20 A 1.28±0.10 A1 0.35±0.06 A2 0.93 e 0.80 b 0.50 +0.05 –0.10 x 0.08 y 0.10 y1 0.20 ZD 1.10 ZE 78 Data Sheet S16685EJ2V0DS 1.10 P109F1-80-DN2 µPD720122 4. RECOMMENDED SOLDERING CONDITIONS The µPD720122 should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact your NEC Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) • µ PD720122GC-9EU : 100-pin plastic TQFP (Fine pitch) (14 × 14) Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher), Symbol IR35-103-2 Count: Two times or less Exposure limit: 3 daysNote (after that, prebake at 125°C for 10 hours) Partial heating Pin temperature: 300°C max., Time: 3 seconds max. (per pin row) – Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period. • µ PD720122F1-GN2 : 109-pin plastic FBGA (11 × 11) Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher), Symbol IR35-103-3 Count: Three times or less Exposure limit: 3 daysNote (after that, prebake at 125°C for 10 hours) Partial heating Pin temperature: 300°C max., Time: 3 seconds max. (per pin row) – Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period. Data Sheet S16685EJ2V0DS 79 µPD720122 [MEMO] 80 Data Sheet S16685EJ2V0DS µPD720122 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet S16685EJ2V0DS 81 µPD720122 EEPROM is a trademark of NEC Electronics Corporation. USB logo is a trademark of USB Implementers Forum, Inc. • The information in this document is current as of June, 2003. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. 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