DATA SHEET MOS INTEGRATED CIRCUIT µPD753304 4-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION The µPD753304 is one of the 75XL series 4-bit single-chip microcontroller chips and has a data processing capability comparable to that of an 8-bit microcontroller. Since it inherits the 75X series CPU, it has upward compatibility. While the conventional 75X series products with an on-chip LCD controller/driver use an 80-pin package, the µPD753304 is sold as a pellet/wafer to make it possible to be built into portable devices with an LCD display function, etc. For detailed function descriptions, refer to the following user’s manual. µPD753304 User’s Manual: U12020E FEATURES • RC oscillation circuit on chip · Main system clock: fCC = 3.6 MHz (typical value with 6.8-kΩ external resistor connected. An internal 10-pF (typ.) capacitor is provided.) · Subsystem clock : fCT = 47 kHz (typ.) (Both a resistor and a capacitor are provided internally.) • Processing can be started immediately after standby mode is released. • Oscillation of the subsystem clock can be stopped in STOP mode. • Supply voltage: VDD = 2.5 to 5.5 V • On-chip memory · Program memory (ROM) : 4096 × 8 bits · Data memory (RAM) : 256 × 4 bits • Variable instruction execution time function useful for power saving · 1.1, 2.2, 4.4, 17.8 µs (in fCC = 3.6 MHz operation) · 85.1 µs (in fCT = 47 kHz operation) • Programmable LCD controller/driver on chip • Sold as a pellet/wafer to make it possible to be built into portable devices with an LCD display function APPLICATION Small LCD display device, etc. ORDERING INFORMATION Part Number µPD753304P-XXX µPD753304W-XXX Package Pellet Wafer Caution The µPD753304 is sold as a pellet/wafer. However, an ES product in 42-pin ceramic shrink DIP is also available. Remark XXX is a ROM code suffix. For the pellet/wafer, consult NEC because an agreement concerning quality must be made. The information in this document is subject to change without notice. Document No. U11874EJ1V0DS00 (1st edition) Date Published October 1997 N Printed in Japan The mark shows major revised points. © 1997 µPD753304 FUNCTIONAL OUTLINE Parameter Function Instruction execution time • 1.1, 2.2, 4.4, 17.8 µs (@ 3.6 MHz with main system clock) • 85.1 µs (@ 47 kHz with subsystem clock) On-chip memory ROM 4096 × 8 bits RAM 256 × 4 bits General-purpose register • 4-bit operation: 8 × 4 banks • 8-bit operation: 4 × 4 banks Input/ output port 12 CMOS input/output LCD controller/driver On-chip pull-up resistors which can be specified by software: 4 Also used for segment pins: 4 • Segment selection: 20/24 segments (can be changed to CMOS input/output port in 4 time-unit; max. 4) • Display mode selection: Static 1/2 duty (1/2 bias) 1/3 duty (1/2 bias) 1/3 duty (1/3 bias) 1/4 duty (1/3 bias) • LCD display modes can be selected by mask option 2 Timer 3 • • • channels 8-bit timer counter: 1 channel (with subclock source input function) Basic interval timer/watchdog timer: 1 channel Watch timer: 1 channel Clock output (PCL) • Φ, 3.6 MHz, 450 kHz, 225 kHz (@ 3.6 MHz with main system clock) Buzzer output (BUZ) • 2.94, 5.88, 47 kHz (@ 47 kHz with subsystem clock) • 1.76, 3.52, 28.13 kHz (@ 3.6 MHz with main system clock) Vectored interrupts External: 1, Internal: 2 Test input Internal: 1 System clock oscillation circuit • Main system clock oscillation RC oscillation circuit (with external resistor and 10 pF (typ.) on-chip capacitor) • Subsystem clock oscillation RC oscillation circuit (with on-chip resistor and capacitor) Standby function STOP mode/HALT mode Supply voltage VDD = 2.5 to 5.5 V Operating ambient temperature TA = –10 to +60 °C Package • Volume production product: Pellet/wafer • ES product (for evaluation): 42-pin ceramic shrink DIP (600 mil) µPD753304 TABLE OF CONTENTS 1. PIN CONFIGURATION ............................................................................................................. 4 2. BLOCK DIAGRAM ................................................................................................................... 7 3. PIN 3.1 3.2 3.3 3.4 FUNCTIONS ...................................................................................................................... 8 Port Pins .......................................................................................................................... 8 Non-Port Pins .................................................................................................................. 9 Pin Input/Output Circuits ............................................................................................. 10 Recommended Connections for Unused Pins ........................................................... 12 4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE ............................ 13 4.1 Difference between Mk I and Mk II Modes .................................................................. 13 4.2 Setting Method of Stack Bank Select Register (SBS) ............................................... 14 5. MEMORY CONFIGURATION ................................................................................................. 15 6. PERIPHERAL HARDWARE FUNCTION .............................................................................. 18 6.1 Digital I/O Port ............................................................................................................... 18 6.2 Clock Generator ............................................................................................................ 18 6.3 Clock Output Circuit ..................................................................................................... 20 6.4 Basic Interval Timer/Watchdog Timer ......................................................................... 21 6.5 Watch Timer .................................................................................................................. 22 6.6 Timer Counter ............................................................................................................... 23 6.7 LCD Controller/Driver ................................................................................................... 24 7. INTERRUPT FUNCTION AND TEST FUNCTION .............................................................. 25 8. STANDBY FUNCTION ............................................................................................................ 26 9. RESET FUNCTION ................................................................................................................. 27 10. MASK OPTION ..................................................................................................................... 30 11. INSTRUCTION SET .............................................................................................................. 31 12. ELECTRICAL SPECIFICATIONS ........................................................................................ 41 13. CHARACTERISTIC CURVE (reference) ............................................................................ 48 APPENDIX A. µPD75308B, 753108 AND 753304 FUNCTIONAL LIST .............................. 49 APPENDIX B. DEVELOPMENT TOOLS .................................................................................. 51 APPENDIX C. RELATED DOCUMENTS .................................................................................. 53 3 µPD753304 1. PIN CONFIGURATION • Pin configuration of volume production product (Pad configuration) · Pellet µPD753304P-XXX Chip size : 3.36 × 2.86 mm 2 Pad intervals : 150 µm Pad size : 120 × 120 µm Y Axis 150 µ m 14 13 12 11 10 8 7 6 5 17 4 18 3 19 2 20 1 21 42 22 41 23 40 24 39 25 38 26 27 28 29 30 31 32 3.36 mm 4 9 120 µ m 15 33 34 35 36 37 D753304 2.86 mm 16 120 µ m X Axis µPD753304 Pad Coordinates (unit: µm: pad center coordinates) No. Pin Name X Axis Y Axis No. Pin Name X Axis Y Axis 1 CL2 1549 311 22 S6 –1549 –351.5 2 CL1 1549 540 23 S5 –1549 –597.5 3 V DD 1549 769 24 S4 –1549 –843.5 4 IC 1549 998 25 S3 –1549 –1089.5 5 P80/S23 1422.5 1299 26 S2 –1301 –1299 6 P81/S22 1169.5 1299 27 S1 –1055 –1299 7 P82/S21 916.5 1299 28 S0 –809 –1299 8 P83/S20 663.5 1299 29 COM0 –563 –1299 9 S19 410.5 1299 30 COM1 –317 –1299 10 S18 157.5 1299 31 COM2 –71 –1299 11 S17 –216.5 1299 32 COM3 289 –1299 12 S16 –469.5 1299 33 RESET 518 –1299 13 S15 –715.5 1299 34 P30/PCL 747 –1299 14 514 –961.5 1299 35 P31/BUZ 976 –1299 15 S13 –1207.5 1299 36 P32 1205 –1209 16 S12 –1453.5 1299 37 P33 1434 –1299 17 S11 –1549 992.5 38 P100 1549 –997 18 S10 –1549 746.5 39 P101 1549 –768 19 S9 –1549 500.5 40 P102 1549 –539 20 S8 –1549 254.5 41 P103/INT1 1549 –310 21 S7 –1549 –105.5 42 V SS 1549 0.5 Caution Connect the rear side of the pellet to GND. 5 µPD753304 • Pin configuration of ES product (Top View) · 42-pin ceramic shrink DIP (600 mil) CL2 1 42 VSS CL1 2 41 P103/INT1 VDD 3 40 P102 IC 4 39 P101 P80/S23 5 38 P100 P81/S22 6 37 P33 P82/S21 7 36 P32 P83/S20 8 35 P31/BUZ S19 9 34 P30/PCL S18 10 33 RESET S17 11 32 COM3 S16 12 31 COM2 S15 13 30 COM1 S14 14 29 COM0 S13 15 28 S0 S12 16 27 S1 S11 17 26 S2 S10 18 25 S3 S9 19 24 S4 S8 20 23 S5 S7 21 22 S6 IC: Internally Connected (Connect directly to VDD.) Caution The µPD753304 is sold as pellet/wafer. The above pin configuration applies to an ES product. Pin Name BUZ CL1, CL2 COM0-COM3 IC INT1 P30-P33 P80-P83 6 : : : : : : : Buzzer Clock RC Oscillator Common Output0-3 Internally Connected External Vectored Interrupt1 Port3 Port8 P100-P103 PCL RESET S0-S23 VDD VSS : : : : : : Port10 Programmable Clock Reset Segment Output0-23 Positive Power Supply Ground µPD753304 2. BLOCK DIAGRAM BUZ/P31 WATCH TIMER INTW fLCD BASIC INTERVAL TIMER/ WATCHDOG TIMER CY PROGRAM COUNTER (12) SP(8) ALU BANK INTBT ROM PROGRAM MEMORY 4096 × 8 BITS DECODE AND CONTROL INT1 INT1/P103 PORT3 4 P30 to P33 4 PORT8 4 P80 to P83 4 PORT10 4 P100 to P103 GENERAL REG. 8-BIT TIMER COUNTER #0 INTT0 4 RAM DATA MEMORY 256 × 4 BITS INTERRUPT CONTROL LCD CONTROLLER/ DRIVER fCC/2 N fLCD CPU CLOCK Φ 20 S0 to S19 4 S20/P83 to S23/P80 4 COM0 to COM3 CLOCK CLOCK SYSTEM CLOCK STAND BY OUTPUT DIVIDER GENERATOR CONTROL CONTROL MAIN SUB PCL/P30 CL1 CL2 IC VDD VSS RESET 7 µPD753304 3. PIN FUNCTIONS 3.1 Port Pins Pin Name P30 Input/output Input/output P31 DualFunction Pin PCL BUZ P32 — P33 — P80 Input/output S23 P81 S22 P82 S21 P83 S20 P100 Input/output — P101 — P102 — P103 INT1 Notes 1. 2. Function 8-Bit I/O After Reset Input I/O Circuit Type Note 1 Note 2 Programmable 4-bit input/output port (PORT3) Input/output specifiable bit-wise Input/output mode after reset specifiable (mask option) Note 2 X 4-bit input/output port (PORT8) X Input H Programmable 4-bit input/output port (PORT10) Input/output specifiable bit-wise Connection of on-chip pull-up resistor specifiable in 4-bit units by software X Input with pull-up resistor E-B F -A denotes Schmitt trigger input. Input/output mode after reset can be specified by mask option. For details, refer to Table 3-1. Table 3-1. State after Reset by Mask Option of Port 3 State after Reset Pin Names Mask Option <1> P30/PCL Input Mask Option <2> Low-level output Mask Option <3> Low-level output P31/BUZ P32 P33 8 E High-level output µPD753304 3.2 Non-Port Pins Pin Name PCL Input/output Output BUZ INT1 Input DualFunction Pin Function After Reset P30 Clock output P31 Arbitrary frequency output (for buzzers or system clock trimming) P103 Edge detected vectored interrupt input (detected edge is selectable) Note 2 E Input with pull-up resistor F -A Segment signal output Highimpedance G-B Segment signal output Input Highimpedance G-B Asynchronous S0-S19 Output S20-S23 Output COM0-COM3 Output — Common signal output CL1 — — — — CL2 — Main system clock oscillation resistor (R) connection pin. No external clock can be input. Input — System reset input (low level active). On-chip pull-up resistor specifiable (mask option) — B -A IC — — Internally connected. Connect directly to VDD. — — V DD — — Positive power supply — — V SS — — Ground potential — — RESET Notes 1. 2. — Input I/O Circuit Type Note 1 P83-P80 H denotes Schmitt trigger input. Input/output mode after reset can be specified by mask option. For details, refer to Table 3-1. 9 µPD753304 3.3 Pin Input/Output Circuits The µPD753304 pin input/output circuits are shown schematically. (1/2) TYPE A TYPE D VDD VDD data P-ch OUT P-ch IN N-ch CMOS specification input buffer. N-ch output disable Push-pull output that can be placed in output high-impedance (both P-ch, N-ch off). TYPE E TYPE B data IN IN/OUT Type D output disable Type A Schmitt triggered input with hysteresis characteristic. TYPE E-B TYPE B-A VDD P.U.R. P.U.R. enable VDD P.U.R. (Mask option) P-ch data Type D output disable IN Type A P.U.R. : Pull-Up Resistor Schmitt triggered input with hysteresis characteristic. 10 P.U.R. : Pull-Up Resistor (At RESET active: Enable) IN/OUT µPD753304 (2/2) TYPE F-A TYPE H VDD P.U.R. P.U.R. enable P-ch SEG data data TYPE G-A IN/OUT IN/OUT Type D output disable data output disable TYPE E Type B P.U.R. : Pull-Up Resistor TYPE G-A VLC0 VLC1 P-ch N-ch OUT SEG data N-ch VLC2 N-ch TYPE G-B VLC0 VLC1 P-ch N-ch OUT COM data N-ch P-ch VLC2 N-ch 11 µPD753304 3.4 Recommended Connections for Unused Pins Table 3-2. List of Recommended Connections for Unused Pins Pin P30/PCL Recommended Connection Input state: Connect independently to VSS or VDD P31/BUZ P32 via resistor Output state: Leave open P33 P100 P101 P102 P103/INT1 S0-S19 Leave open COM0-COM3 12 S20/P83-S23/P80 Input state: Connect independently to VSS or VDD via resistor Output state: Leave open IC Connect directly to V DD µPD753304 4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE 4.1 Difference between Mk I and Mk II Modes The CPU of the µPD753304 has the following two modes: Mk I and Mk II, either of which can be selected. The mode can be switched by bit 3 of the Stack Bank Select register (SBS). • Mk I mode: Can be used in the 75XL CPU with a ROM capacity of up to 16K bytes. • Mk II mode: Can be used in all the 75XL CPU’s including those products whose ROM capacity is more than 16K bytes. Table 4-1. Differences between Mk I Mode and Mk II Mode Mk I mode Mk II mode Number of stack bytes for subroutine instructions 2 bytes 3 bytes BRA !addr1 instruction CALLA !addr1 instruction Not available Available CALL !addr instruction 3 machine cycles 4 machine cycles CALLF !faddr instruction 2 machine cycles 3 machine cycles Caution The Mk II mode supports a program area which exceeds 16K bytes in the 75X and 75XL series. This mode enhances the software compatibility with products which have more than 16K bytes. When Mk II mode is selected, the number of stack bytes (usable area) in the execution of a subroutine call instruction increases by 1 per stack compared to Mk I mode. Furthermore, when a CALL !addr, or CALLF !faddr instruction is used, each instruction takes another machine cycle. Therefore, when more importance is attached to RAM utilization or throughput than software compatibility, use the Mk I mode. 13 µPD753304 4.2 Setting Method of Stack Bank Select Register (SBS) Switching between the Mk I mode and Mk II mode can be done by the SBS. Figure 4-1 shows the format. The SBS is set by a 4-bit memory manipulation instruction. When using the Mk I mode, the SBS must be initialized to 1000B at the beginning of a program. When using the Mk II mode, it must be initialized to 0000B. Figure 4-1. Stack Bank Select Register Format Address 3 F84H SBS3 2 1 SBS2 SBS1 0 Symbol SBS0 SBS Stack area specification 0 0 Memory bank 0 Other than above setting prohibited 0 0 must be assigned to the bit 2 position. Mode switching specification 0 Mk II mode 1 Mk I mode Caution Since SBS. 3 is set to “1” after a RESET signal is generated, the CPU operates in the Mk I mode. When executing an instruction in the Mk II mode, set SBS. 3 to “0” to select the Mk II mode. 14 µPD753304 5. MEMORY CONFIGURATION • Program Memory (ROM) .... 4096 × 8 bits • Addresses 0000H and 0001H Vector table wherein the program start address and the values set for the RBE and MBE at the time a RESET signal is generated are written. Reset and start are possible at an any address. • Addresses 0002H to 000DH Vector table wherein the program start address and values set for the RBE and MBE by the vectored interrupts are written. Interrupt execution can be started at an any address. • Addresses 0020H to 007FH Table area referenced by the GETI instruction Note . Note The GETI instruction realizes a 1-byte instruction on behalf of an any 2-byte instruction, 3-byte instruction, or two 1-byte instructions. It is used to decrease the program steps. • Data Memory (RAM) • Data area ... 256 words × 4 bits (000H to 0FFH) • Peripheral hardware area ... 128 words × 4 bits (F80H to FFFH) 15 µPD753304 Figure 5-1. Program Memory Map Address 7 6 0 0 0 H MBE RBE 0 0 2 H MBE RBE 0 0 6 H MBE RBE 0 0 A H MBE RBE 5 4 0 0 0 0 0 0 0 0 0 Internal reset start address (high-order 4 bits) Internal reset start address (low-order 8 bits) INTBT start address (high-order 4 bits) INTBT start address (low-order 8 bits) INT1 start address (high-order 4 bits) INT1 start address (low-order 8 bits) INTT0 start address (high-order 4 bits) INTT0 start address (low-order 8 bits) CALLF !faddr instruction entry address Branch address of BR BCXA, BR BCDE, BR !addr, BRA !addr1 Note or CALLA !addr1 Note instruction CALL !addr instruction subroutine entry address BR $addr instruction relative branch address 020H GETI instruction reference table –15 to –1, +2 to +16 Branch address of BRCB !caddr instruction 07FH 080H Branch destination address and subroutine entry address when GETI instruction is executed 7FFH 800H FFFH Note Can be used in Mk II mode only. Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order eight bits of PC by executing the BR PCDE or BR PCXA instruction. 16 µPD753304 Figure 5-2. Data Memory Map Data memory 000H General-purpose register area Memory bank (32 x 4) 01FH 020H Data area static RAM (256 x 4) 0 256 x 4 (224 x 4) Stack area 0FFH 100H Not incorporated 256 x 4 1 Display data memoryNote 1DFH 1E0H (24 x 4) 1F7H 1F8H 1FFH Not incorporated Not incorporated F80H 128 x 4 Peripheral hardware area 15 FFFH Note Write only. 17 µPD753304 6. PERIPHERAL HARDWARE FUNCTION 6.1 Digital I/O Port There are three kinds of I/O port. • CMOS input/output ports (PORT 3, 8, 10): 12 Table 6-1. Types and Features of Digital Ports Port PORT3 Function 4-bit I/O Operation & features Remarks Can be set to input mode or output mode in 1-bit unit. Also used for the PCL and BUZ pins. PORT8 Can be set to input mode or output mode in 4-bit units. Also used for the S20 to S23 pins. PORT10 Can be set to input mode or output mode in 1-bit unit. Also used for the INT1 pin. 6.2 Clock Generator The clock generator is a device that generates the clock fed to peripheral hardware on the CPU and is configured as shown in Figure 6-1. The clock generator operates according to how the processor clock control register (PCC) and system clock control register (SCC) are set. There are two kinds of clocks, main system clock and subsystem clock. The instruction execution time can also be changed. • 1.1, 2.2, 4.4, 17.8 µs (main system clock: in 3.6-MHz operation) • 85.1 µs (subsystem clock: in 47-kHz operation) 18 µPD753304 Figure 6-1. Clock Generator Block Diagram · Basic interval timer (BT) · Timer counter · Watch timer · LCD controller/driver · Clock output circuit CL1 Main system clock oscillator (with RC CL2 oscillation and capacitor) Subsystem clock oscillator (with RC oscillation, resistor and capacitor) WM.3 SOS SOS3 SCC 1/1 to 1/4096 fCC Divider 1/2 1/4 1/16 · Timer counter · LCD controller/driver · Watch timer fCT Oscillation stop Selector Oscillation stop Divider Selector SCC3 1/4 Φ Internal bus SCC0 · CPU · Clock output circuit PCC PCC0 PCC1 HALT F/F 4 PCC2 S HALT Note STOP Note PCC3 PCC2, PCC3 Clear R STOP F/F Q Q Wait release signal from BT S RESET signal R Standby release signal from interrupt control circuit Note Instruction execution Remarks 1. fCC = Main system clock frequency 2. fXT = Subsystem clock frequency 3. Φ = CPU clock 4. PCC: Processor Clock Control Register 5. SCC: System Clock Control Register 6. One clock cycle (tCY) of the CPU clock is equal to one machine cycle of the instruction. 19 µPD753304 6.3 Clock Output Circuit The clock output circuit is provided to output the clock pulses from the PCL/P30 pin to the remote control waveform outputs and peripheral LSI’s. • Clock Output (PCL): Φ, 3.6 MHz, 450 kHz, 225 kHz (in 3.6-MHz operation) Figure 6-2. Clock Output Circuit Block Diagram From clock generator Φ Output buffer fCC Selector fCC/23 PCL/P30 fCC/24 PORT3.0 CLOM3 0 CLOM1 CLOM0 P30 output latch CLOM Bit 0 of PMGA Port 3 I/O mode specification bit 4 Internal bus Remark Special care has been taken in designing the chip so that small-width pulses may not be output when switching clock output enable/disable. 20 µPD753304 6.4 Basic Interval Timer/Watchdog Timer The basic interval timer/watchdog timer has the following functions. • Interval timer operation to generate a reference time interrupt • Watchdog timer operation to detect an inadvertent program loop and reset the CPU • Reads the contents of counting Figure 6-3. Basic Interval Timer/Watchdog Timer Block Diagram From clock generator Clear fCC/25 fCC/27 MPX Clear Basic interval timer (8-bit frequency divider) Set fCC/29 BT fCC/212 3 Wait release signal when standby is released. BTM3 BTM2 BTM1 BTM0 BTM SET1 Note 4 BT interrupt request flag Vectored interrupt IRQBT request signal Internal reset signal WDTM SET1 Note 8 1 Internal bus Note Instruction execution 21 µPD753304 6.5 Watch Timer The µPD753304 has one watch timer channel which has the following functions. • Sets the test flag (IRQW) at fW/2 14 intervals. The standby mode can be released by the IRQW. • Convenient for program debugging and checking as interval becomes 128 times longer (fW/27) with the fast feed mode. • Outputs the frequencies (fW, fW/23, fW/2 4) to the BUZ/P31 pin, usable for buzzer and trimming of system clock frequencies. • Clears the frequency divider to make the watch start with zero seconds. Figure 6-4. Watch Timer Block Diagram fW 26 fLCD fW 27 fCC 128 From clock generator Selector fW Divider fCT 4 kHz 2 kHz fW fW 23 24 fW 214 Selector INTW IRQW set signal Clear Selector Output buffer BUZ/P31 WM PORT3.1 Note WM7 0 WM5 WM4 WM3 WM2 WM1 WM0 8 Internal bus Note Set WM2 to 1 when using the LCD controller/driver. 22 P31 output-latch PMGA bit 1 Port 3 input/ output mode µPD753304 6.6 Timer Counter The µPD753304 has one channel of timer counter. Its configuration is shown in Figure 6-5. The timer counter has the following functions. • Programmable interval timer operation • Read the count value. Figure 6-5. Timer Counter Block Diagram Internal bus Note 8 SET1 8 8 TMOD0 TM0 0 TM06 TM05 TM04 TM03 TM02 0 Modulo register (8) 0 8 Match Comparator (8) 8 T0 4 From clock generator fCC/2 fCC/26 Count register (8) MPX fCC/28 fCC/210 fCT CP Clear INTT0 IRQT0 set signal Timer operation start RESET IRQT0 clear signal Note Instruction execution Caution When setting data to the TM0, be sure to set bits 0, 1, 7 to 0. 23 µPD753304 6.7 LCD Controller/Driver The µPD753304 incorporates a display controller which generates segment and common signals according to the display data memory contents and incorporates segment and common drivers which can drive the LCD panel directly. The µPD753304 LCD controller/driver has the following functions: • Display data memory is read automatically by DMA operation and segment and common signals are generated. • Display mode can be selected from among the following five: <1> Static <2> 1/2 duty (time multiplexing by 2), 1/2 bias <3> 1/3 duty (time multiplexing by 3), 1/2 bias <4> 1/3 duty (time multiplexing by 3), 1/3 bias <5> 1/4 duty (time multiplexing by 4), 1/3 bias • A frame frequency can be selected from among four in each display mode. • A maximum of 24 segment signal output pins (S0 to S23) and four common signal output pins (COM0 to COM3). • The segment signal output pins (S20 to S23) can be changed to the I/O ports (PORT8). • LCD display modes can be selected (mask option). • It can also operate by using the subsystem clock. Figure 6-6. LCD Controller/Driver Block Diagram Internal bus 4 4 8 4 Port 8 output latch Port mode LCD/port selection register 3 2 1 0 register group C 0 4 8 1F7H 3 2 1 0 1F4H 1F3H 3 2 1 0 3 2 1 0 1E0H 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 Display mode register 4 Display control register Decoder Port 8 Input/Output buffer 0 1 2 Segment driver Common driver 3 S23/P80 24 Segment driver Timing fLCD controller S20/P83 S19 S0 COM3 COM2 COM1 COM0 LCD drive voltage control µPD753304 7. INTERRUPT FUNCTION AND TEST FUNCTION The µPD753304 has three different interrupt sources and one types of test source. The interrupt control circuit of the µPD753304 has the following functions. (1) Interrupt function • Vectored interrupt function for hardware control, enabling/disabling the interrupt acceptance by the interrupt enable flag (IExxx) and interrupt master enable flag (IME). • Can set any interrupt start address. • Multiple interrupts wherein the order of priority can be specified by the interrupt priority select register (IPS). • Test function of interrupt request flag (IRQxxx). An interrupt generation can be checked by software. • Release the standby mode. An interrupt to be released can be selected by the interrupt enable flag. (2) Test function • Test request flag (IRQxxx) generation can be checked by software. • Release the standby mode. The test source to be released can be selected by the test enable flag. Figure 7-1. Interrupt Control Circuit Block Diagram Internal bus 1 IME IPS Interruput enable flag (IExxx) IM1 INTBT INT1/P103 Edge detector IRQBT IST1 IST0 Decoder VRQn IRQ1 INTT0 IRQT0 INTW IRQW Priority control circuit Vector table address generator Standby release signal 25 µPD753304 8. STANDBY FUNCTION In order to reduce power dissipation while a program is in a standby mode, two types of standby modes (STOP mode and HALT mode) are provided for the µPD753304. Table 8-1. Operation Status in Standby Mode Mode Item STOP mode HALT mode Set instruction STOP instruction System clock for setting Can be set by either main system clock or subsystem clock. Operating status Clock generator Only CPU clock Φ is stopped (oscillation Oscillation of main system clock is continues.) stopped. Setting the sub oscillation circuit stop enable flag (SOS.3) to 1 also stops oscillation of the subsystem clock. Basic interval timer/ watchdog timer Operation stopped Operates only when main system clock is oscillating BT mode : Sets IRQBT at reference time intervals WT mode : Generates reset signal when BT overflows Timer counter Operation possible only when SOS.3 is set to 0 and f CT is selected as count clock. Operation impossible only when a divided main system clock is selected as count clock when the main system clock is stopped. LCD control/driver Operation possible only when SOS.3 is set to 0 and f CT is selected as LCDCL. Operation possible Watch timer Operation possible only when SOS.3 is set to 0 and f CT is selected as count clock. Operation possible External interrupt Operation possible only when SOS.3 is set to 0. CPU Operation stopped Release signal 26 HALT instruction Generation of an interrupt request signal from hardware whose operation is enabled by an interrupt enable flag or RESET signal. µPD753304 9. RESET FUNCTION There are two reset inputs: external RESET signal and reset signal sent from the basic interval timer/watchdog timer. When either one of the reset signals are input, an internal reset signal is generated. Figure 9-1 shows the circuit diagram of the above two inputs. Figure 9-1. Configuration of Reset Function RESET Internal reset signal Reset signal sent from the basic interval timer/watchdog timer WDTM Internal bus Generation of the RESET signal initializes each device as listed in Table 9-1. Figure 9-2 shows the timing chart of the reset operation. Figure 9-2. Reset Operation by RESET Signal Generation Wait Note RESET signal generated Operation mode or standby mode HALT mode Operation mode Internal reset operation Note 56/fCC (15.6 µs: @ 3.6-MHz operation) 27 µPD753304 Table 9-1. Status of Each Device After Reset (1/2) RESET signal generation in the standby mode RESET signal generation in operation Sets the low-order 4 bits of program memory’s address 0000H to the PC11-PC8 and the contents of address 0001H to the PC7-PC0. Sets the low-order 4 bits of program memory’s address 0000H to the PC11-PC8 and the contents of address 0001H to the PC7-PC0. Held Undefined Skip flag (SK0 to SK2) 0 0 Interrupt status flag (IST0) 0 0 Sets the bit 6 of program memory’s address 0000H to the RBE and bit 7 to the MBE. Sets the bit 6 of program memory’s address 0000H to the RBE and bit 7 to the MBE. Undefined Undefined 1000B 1000B Data memory (RAM) Held Undefined General-purpose register (X, A, H, L, D, E, B, C) Held Undefined Bank select register (MBS, RBS) 0, 0 0, 0 Undefined Undefined Hardware Program counter (PC) PSW Carry flag (CY) Bank enable flag (MBE, RBE) Stack pointer (SP) Stack bank select register (SBS) Basic interval Counter (BT) timer/watchdog Mode register (BTM) 0 0 timer Watchdog timer enable flag (WDTM) 0 0 Timer Counter (T0) 0 0 counter (T0) Modulo register (TMOD0) FFH FFH 0 0 Mode register (TM0) 28 µPD753304 Table 9-1. Status of Each Device After Reset (2/2) Hardware RESET signal generation in the standby mode RESET signal generation in operation Watch timer Mode register (WM) 0 0 Clock generator, Processor clock control register (PCC) 0 0 clock output System clock control register (SCC) 0 0 circuit Clock output mode register (CLOM) 0 0 Subsystem clock oscillator control register (SOS) 0 0 LCD controller/ Display mode register (LCDM) 0 0 driver Display control register (LCDC) 0 0 LCD/port selection register (LPS) 0 0 Reset (0) Reset (0) Interrupt Interrupt request flag (IRQxxx) function Interrupt enable flag (IExxx) 0 0 Interrupt priority select register (IPS) 0 0 INT1 mode registers (IM1) 0 0 Output buffer (P30-P33) On On Output buffer (P80-P83, P100-P103) Off Off Cleared (0) Cleared (0) Set (1) Set (1) I/O mode registers (PMGA) 0FH 0FH I/O mode registers (PMGC, D) 00H 00H Pull-up resistor setting register (POGB) 01H 01H Digital port Output latch (P30-P32, P80-P83, P100-P103) Output latch (P33) 29 µPD753304 10. MASK OPTION The µPD753304 has the following mask options. • RESET pin mask option An on-chip pull-up resistor can be selected. <1> Specifies an on-chip pull-up resistor. <2> Specifies no on-chip pull-up resistor. • LCD display mode mask option LCD display modes can be selected. <1> Static display mode (BIAS-V LC0 shorted, VLC0 – VLC1 opened) <2> 1/2 bias mode (BIAS-VLC0 shorted, VLC1 – VLC2 shorted) <3> 1/3 bias mode (BIAS-VLC0 shorted) • Standby function mask option Wait time can be selected after STOP mode is released. <1> 512/fCC (142 µs: in 3.6 MHz operation) <2> No waits • Port 3 mask option Input/output mode after reset can be specified Status after Reset Pin Names Mask Option <1> P30/PCL Input Mask Option <2> Low-level output Mask Option <3> Low-level output P31/BUZ P32 P33 30 High-level output µPD753304 11. INSTRUCTION SET (1) Expression formats and description methods of operands The operand is written in the operand column of each instruction in accordance with the method of use of the instruction operand identifier. For details, refer to “RA75X ASSEMBLER PACKAGE USER’S MANUAL—LANGUAGE (U12385E)”. If there are several elements, one of them is selected. Capital letters and the + and – symbols are key words and are written as they are. For immediate data, appropriate numbers and labels are written. Instead of the labels such as mem, fmem, pmem, and bit, the symbols of the registers can be written. However, there are restrictions in the labels that can be written for fmem and pmem. For details, refer to User’s Manual (U12020E). Identifier Format reg reg1 X, A, B, C, D, E, H, L X, B, C, D, E, H, L rp rp1 rp2 rp' rp'1 XA, BC, BC, XA, BC, rpa rpa1 HL, HL+, HL–, DE, DL DE, DL n4 n8 4-bit immediate data or label 8-bit immediate data or label mem bit 8-bit immediate data or label 2-bit immediate data or label fmem pmem FB0H-FBFH, FF0H-FFFH immediate data or label FC0H-FFFH immediate data or label addr, addr1 caddr faddr 0000H-0FFFH immediate data or label 12-bit immediate data or label 11-bit immediate data or label taddr 20H-7FH immediate data (where bit 0 = 0) or label PORTn IExxx RBn MBn PORT3, PORT8, PORT10 IEBT, IET0, IE1, IEW RB0-RB3 MB0, MB1, MB15 BC, DE, DE BC, DE, DE, HL HL DE, HL, XA', BC', DE', HL' HL, XA', BC', DE', HL' Note Note mem can be only used for even address in 8-bit data processing. 31 µPD753304 (2) Legend in explanation of operation 32 A : A register, 4-bit accumulator B : B register C : C register D : D register E : E register H : H register L : L register X : X register XA : XA register pair; 8-bit accumulator BC : BC register pair DE : DE register pair HL : HL register pair XA’ : XA’ expanded register pair BC’ : BC’ expanded register pair DE’ : DE’ expanded register pair HL’ : HL’ expanded register pair PC : Program counter SP : Stack pointer CY : Carry flag, bit accumulator PSW : Program status word MBE : Memory bank enable flag RBE : Register bank enable flag PORTn : Port n (n = 3, 8, 10) IME : Interrupt master enable flag IPS : Interrupt priority selection register IExxx : Interrupt enable flag RBS : Register bank selection register MBS : Memory bank selection register PCC : Processor clock control register . : Separation between address and bit (xx) : The contents addressed by xx xxH : Hexadecimal data µPD753304 (3) Explanation of symbols under addressing area column *1 MB = MBE·MBS (MBS = 0, 1, 15) *2 MB = 0 *3 MBE = 0 : MB = 0 (000H to 07FH) MB = 15 (F80H to FFFH) MBE = 1 : MB = MBS (MBS = 0, 1, 15) *4 MB = 15, fmem = FB0H to FBFH, FF0H to FFFH *5 MB = 15, pmem = FC0H to FFFH *6 addr = 000H to FFFH *7 addr = (Current PC) – 15 to (Current PC) – 1 (Current PC) + 2 to (Current PC) + 16 addr1 = (Current PC) – 15 to (Current PC) – 1 (Current PC) + 2 to (Current PC) + 16 *8 caddr = 000H to FFFH *9 faddr = 0000H to 07FFH *10 taddr = 0020H to 007FH *11 addr1 = 000H to FFFH Remarks 1. Data memory addressing Program memory addressing MB indicates memory bank that can be accessed. 2. In *2, MB = 0 independently of how MBE and MBS are set. 3. In *4 and *5, MB = 15 independently of how MBE and MBS are set. 4. *6 to *11 indicate the areas that can be addressed. 33 µPD753304 (4) Explanation of number of machine cycles column S denotes the number of machine cycles required by skip operation when a skip instruction is executed. The value of S varies as follows. • When no skip is made: S = 0 • When the skipped instruction is a 1- or 2-byte instruction: S = 1 • When the skipped instruction is a 3-byte instruction Note: S = 2 Note 3-byte instruction: BR !addr, BRA !addr1, CALL !addr or CALLA !addr1 instruction Caution The GETI instruction is skipped in one machine cycle. One machine cycle is equal to one cycle of CPU clock (= tCY); time can be selected from among four types by setting PCC. 34 µPD753304 Instruction group Transfer instruction Mnemonic MOV XCH Table reference MOVT Number of bytes Machine cycles A, #n4 1 1 A ← n4 reg1, #n4 2 2 reg1 ← n4 XA, #n8 2 2 XA ← n8 String effect A HL, #n8 2 2 HL ← n8 String effect B rp2, #n8 2 2 rp2 ← n8 A, @HL 1 1 A ← (HL) *1 A, @HL+ 1 2+S A ← (HL), then L ← L+1 *1 L=0 A, @HL– 1 2+S A ← (HL), then L ← L–1 *1 L = FH A, @rpa1 1 1 A ← (rpa1) *2 XA, @HL 2 2 XA ← (HL) *1 @HL, A 1 1 (HL) ← A *1 @HL, XA 2 2 (HL) ← XA *1 A, mem 2 2 A ← (mem) *3 XA, mem 2 2 XA ← (mem) *3 mem, A 2 2 (mem) ← A *3 mem, XA 2 2 (mem) ← XA *3 A, reg 2 2 A ← reg XA, rp' 2 2 XA ← rp' reg1, A 2 2 reg1 ← A rp'1, XA 2 2 rp'1 ← XA Operand Addressing area Skip condition String effect A A, @HL 1 1 A ↔ (HL) *1 A, @HL+ 1 2+S A ↔ (HL), then L ← L+1 *1 L=0 A, @HL– 1 2+S A ↔ (HL), then L ← L–1 *1 L = FH A, @rpa1 1 1 A ↔ (rpa1) *2 XA, @HL 2 2 XA ↔ (HL) *1 A, mem 2 2 A ↔ (mem) *3 XA, mem 2 2 XA ↔ (mem) *3 A, reg1 1 1 A ↔ reg1 XA, rp' 2 2 XA ↔ rp' XA, @PCDE 1 3 XA ← (PC11–8+DE)ROM XA, @PCXA 1 3 XA ← (PC11–8+XA)ROM XA, @BCDE 1 3 XA ← (BCDE)ROM Note *6 3 XA ← (BCXA)ROM *6 XA, @BCXA Note Operation 1 Note Be sure to assign “0” to register B. 35 µPD753304 CY, fmem.bit 2 2 CY ← (fmem.bit) *4 CY, pmem.@L 2 2 CY ← (pmem7–2+L3–2.bit(L1–0)) *5 CY, @H+mem.bit 2 2 CY ← (H+mem3–0.bit) *1 fmem.bit, CY 2 2 (fmem.bit) ← CY *4 pmem.@L, CY 2 2 (pmem7–2+L3–2.bit(L1–0)) ← CY *5 @H+mem.bit, CY 2 2 (H+mem3–0.bit) ← CY *1 ADDS A, #n4 1 1+S A ← A+n4 carry XA, #n8 2 2+S XA ← XA+n8 carry A, @HL 1 1+S A ← A+(HL) ADDC SUBS SUBC AND OR XOR Addressing area *1 Skip condition carry XA, rp' 2 2+S XA ← XA+rp' carry rp'1, XA 2 2+S rp'1 ← rp'1+XA carry A, @HL 1 1 A, CY ← A+(HL)+CY XA, rp' 2 2 XA, CY ← XA+rp'+CY rp'1, XA 2 2 rp'1, CY ← rp'1+XA+CY A, @HL 1 1+S A ← A–(HL) XA, rp' 2 2+S XA ← XA–rp' borrow rp'1, XA 2 2+S rp'1 ← rp'1–XA borrow A, @HL 1 1 A, CY ← A–(HL)–CY XA, rp' 2 2 XA, CY ← XA–rp'–CY rp'1, XA 2 2 rp'1, CY ← rp'1–XA–CY *1 *1 A, #n4 2 2 A←A > MOV1 Operation A, @HL 1 1 A←A > Operation Machine cycles Operand XA, rp' 2 2 XA ← XA rp'1, XA 2 2 rp'1 ← rp'1 A, #n4 2 2 A ← A ∨ n4 A, @HL 1 1 A ← A ∨ (HL) XA, rp' 2 2 XA ← XA ∨ rp' rp'1, XA 2 2 rp'1 ← rp'1 ∨ XA A, #n4 2 2 A ← A v n4 A, @HL 1 1 A ← A v (HL) XA, rp' 2 2 XA ← XA v rp' rp'1, XA 2 2 rp'1 ← rp'1 v XA borrow *1 n4 (HL) > Bit transfer Number of bytes Mnemonic *1 rp' > Instruction group XA *1 *1 Accumulator manipulation instructions RORC A 1 1 CY ← A0, A3 ← CY, An–1 ← An NOT A 2 2 A←A Increment and Decrement instructions INCS reg 1 1+S reg ← reg+1 reg = 0 rp1 1 1+S rp1 ← rp1+1 rp1 = 00H @HL 2 2+S (HL) ← (HL)+1 *1 (HL) = 0 mem 2 2+S (mem) ← (mem)+1 *3 (mem) = 0 reg 1 1+S reg ← reg–1 reg = FH rp' 2 2+S rp' ← rp'–1 rp' = FFH DECS 36 µPD753304 Memory bit manipulation instructions reg, #n4 2 2+S Skip if reg = n4 @HL, #n4 2 2+S Skip if (HL) = n4 *1 (HL) = n4 A, @HL 1 1+S Skip if A = (HL) *1 A = (HL) XA, @HL 2 2+S Skip if XA = (HL) *1 XA = (HL) A, reg 2 2+S Skip if A = reg A = reg XA, rp' 2 2+S Skip if XA = rp' XA = rp' SET1 CY 1 1 CY ← 1 CLR1 CY 1 1 CY ← 0 SKT CY 1 1+S NOT1 CY 1 1 CY ← CY SET1 mem.bit 2 2 (mem.bit) ← 1 *3 fmem.bit 2 2 (fmem.bit) ←1 *4 pmem.@L 2 2 (pmem7–2+L3–2.bit(L1–0)) ←1 *5 @H+mem.bit 2 2 (H+mem3–0.bit) ←1 *1 mem.bit 2 2 (mem.bit) ←0 *3 fmem.bit 2 2 (fmem.bit) ←0 *4 pmem.@L 2 2 (pmem7–2+L3–2.bit(L1–0)) ←0 *5 @H+mem.bit 2 2 (H+mem3–0.bit) ←0 *1 mem.bit 2 2+S Skip if (mem.bit) = 1 *3 (mem.bit) = 1 fmem.bit 2 2+S Skip if (fmem.bit) = 1 *4 (fmem.bit) = 1 pmem.@L 2 2+S Skip if (pmem7–2+L3–2.bit(L1–0)) = 1 *5 (pmem.@L) = 1 @H+mem.bit 2 2+S Skip if (H+mem3–0.bit) = 1 *1 (@H+mem.bit) = 1 mem.bit 2 2+S Skip if (mem.bit) = 0 *3 (mem.bit) = 0 fmem.bit 2 2+S Skip if (fmem.bit) = 0 *4 (fmem.bit) = 0 pmem.@L 2 2+S Skip if (pmem7–2+L3–2.bit(L1–0)) = 0 *5 (pmem.@L) = 0 @H+mem.bit 2 2+S Skip if (H+mem3–0.bit) = 0 *1 (@H+mem.bit) = 0 fmem.bit 2 2+S Skip if (fmem.bit) = 1 and clear *4 (fmem.bit) = 1 pmem.@L 2 2+S Skip if (pmem7–2+L3–2.bit(L1–0)) = 1 and clear *5 (pmem.@L) = 1 @H+mem.bit 2 2+S Skip if (H+mem3–0.bit) = 1 and clear *1 (@H+mem.bit) = 1 CY, fmem.bit 2 2 CY ← CY (fmem.bit) *4 CY, pmem.@L 2 2 CY ← CY (pmem7–2+L3–2.bit(L1–0)) *5 CY, @H+mem.bit 2 2 CY ← CY (H+mem3–0.bit) CY, fmem.bit 2 2 CY ← CY ∨ (fmem.bit) *4 CY, pmem.@L 2 2 CY ← CY ∨ (pmem7–2+L3–2.bit(L1–0)) *5 CY, @H+mem.bit 2 2 CY ← CY ∨ (H+mem3–0.bit) *1 CY, fmem.bit 2 2 CY ← CY v (fmem.bit) *4 CY, pmem.@L 2 2 CY ← CY v (pmem7–2+L3–2.bit(L1–0)) *5 CY, @H+mem.bit 2 2 CY ← CY v (H+mem3–0.bit) *1 SKE CLR1 SKT SKF SKTCLR AND1 OR1 XOR1 Operation Addressing area Skip condition reg = n4 Skip if CY = 1 > Carry flag manipulation instruction Machine cycles Operand > Comparison instruction Number of bytes Mnemonic > Instruction group CY = 1 *1 37 µPD753304 Instruction group Branch instructions Number of bytes Machine cycles – – PC11–0 ← addr Select appropriate instruction from among BR !addr, BRCB !caddr and BR $addr according to the assembler being used. *6 – – PC11-0 ← addr1 Select appropriate instruction from among BR !addr BRA !addr1, BRCB !caddr and BR $addr1 according to the assembler being used. *11 !addr 3 3 PC11–0 ← addr *6 $addr 1 2 PC11–0 ← addr *7 1 2 PC11–0 ← addr1 *7 PCDE 2 3 PC11–0 ← PC11-8+DE PCXA 2 3 PC11–0 ← PC11-8+XA BCDE 2 3 PC11–0 ← BCDE Note 2 *6 BCXA 2 3 PC11–0 ← BCXA Note 2 *6 !addr1 3 3 PC11–0 ← addr1 *11 !caddr 2 2 PC11–0 ← caddr11–0 *8 CALLA Note 1 !addr1 3 3 (SP–2) ← x, x, MBE, RBE (SP–6) (SP–3) (SP–4) ← PC11–0 (SP–5) ← 0, 0, 0, 0 PC11–0 ← addr1, SP ← SP–6 *11 3 3 (SP–3) ←MBE, RBE, 0, 0 (SP–4) (SP–1) (SP–2) ← PC11–0 PC11–0 ← addr, SP ← SP–4 *6 4 (SP–2) ←x, x, MBE, RBE (SP–6) (SP–3) (SP–4) ← PC11–0 (SP–5) ← 0, 0, 0, 0 PC11–0 ← addr, SP ← SP–6 2 (SP–3) ← MBE, RBE, 0, 0 (SP–4) (SP–1) (SP–2) ← PC11–0 PC11–0 ← 0+faddr, SP ← SP–4 3 (SP–2) ← x, x, MBE, RBE (SP–6) (SP–3) (SP–4) ← PC11–0 (SP–5) ← 0, 0, 0, 0 PC11–0 ← 0+faddr, SP ← SP–6 Mnemonic BR Note 1 Operand addr addr1 BR BRA Note 1 BRCB Subroutine stack control instructions CALL Note 1 $addr1 !addr CALLF Note 1 !faddr Notes 1. 2 Operation 38 Skip condition *9 The above operations in the double boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. 2. Addressing area “0” must be assigned to B register. µPD753304 Instruction group Subroutine stack control instructions Mnemonic Operand RET Note 1 Number of bytes Machine cycles 1 3 Addressing area Operation Skip condition PC11–0 ← (SP) (SP+3) (SP+2) MBE, RBE, 0, 0 ← (SP+1), SP ← SP+4 x, x, MBE, RBE ← (SP+4) 0, 0, 0, 0, ← (SP+1) PC11–0 ← (SP) (SP+3) (SP+2), SP ← SP+6 RETS Note 1 1 3+S MBE, RBE, 0, 0 ← (SP+1) PC11–0 ← (SP) (SP+3) (SP+2) SP ← SP+4 then skip unconditionally Unconditional 0, 0, 0, 0 ← (SP+1) PC11–0 ← (SP) (SP+3) (SP+2) x, x, MBE, RBE ← (SP+4) SP ← SP+6 then skip unconditionally RETI Note 1 1 3 MBE, RBE, 0, 0 ← (SP+1) PC11–0 ← (SP) (SP+3) (SP+2) PSW ← (SP+4) (SP+5), SP ← SP+6 0, 0, 0, 0 ← (SP+1) PC11–0 ← (SP) (SP+3) (SP+2) PSW ← (SP+4) (SP+5), SP ← SP+6 rp 1 1 (SP–1)(SP–2) ← rp, SP ← SP–2 BS 2 2 (SP–1) ← MBS, (SP–2) ← RBS, SP ← SP–2 rp 1 1 rp ← (SP+1) (SP), SP ← SP+2 BS 2 2 MBS ← (SP+1), RBS ← (SP), SP ← SP+2 2 2 IME (IPS.3) ← 1 2 2 IExxx ← 1 2 2 IME (IPS.3) ← 0 IExxx 2 2 IExxx ← 0 IN Note 2 A, PORTn 2 2 A ← PORTn (n = 3, 8, 10) OUT Note 2 PORTn, A 2 2 PORTn ← A (n = 3, 8, 10) HALT 2 2 Set HALT Mode (PCC.2 ← 1) STOP 2 2 Set STOP Mode (PCC.3 ← 1) NOP 1 1 No Operation RBn 2 2 RBS ← n (n = 0-3) MBn 2 2 MBS ← n (n = 0, 15) PUSH POP Interrupt control instructions EI IExxx DI Input/output instructions CPU control instructions Special instructions Notes 1. SEL The above operations in the double boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. 2. While the IN instruction and OUT instruction are being executed, the MBE must be set to 0 or 1 and MBS must be set to 15. 39 µPD753304 Instruction group Special instructions Mnemonic GET Note 1, 2 Operand taddr Number of bytes Machine cycles 1 3 Operation • When TBR instruction PC11–0 ← (taddr) 3–0 + (taddr+1) Addressing area Skip condition *10 –––––––––––––––––––––––––––––––––– ––––––––––––– • When TCALL instruction (SP–4) (SP–1) (SP–2) ← PC11–0 (SP–3) ← MBE, RBE, 0, 0 PC11–0 ← (taddr) 3–0 + (taddr+1) SP ← SP–4 –––––––––––––––––––––––––––––––––– ––––––––––––– • When instruction other than TBR and TCALL instructions (taddr) (taddr+1) instruction is executed. 3 • When TBR instruction PC11–0 ← (taddr) 3–0 + (taddr+1) ––––––––––––––––––––––––––––––––––––– –––– 4 Notes 1. 2. • When instruction other than TBR and TCALL instructions (taddr) (taddr+1) instruction is executed. ––––––––––––– ––––––––––––– Depending on the reference instruction The TBR and TCALL instructions are the table definition assembler directives of the GETI instruction. The above operations in the double boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. 40 *10 • When TCALL instruction (SP–6) (SP–3) (SP–4) ← PC11–0 (SP–5) ← 0, 0, 0, 0 (SP–2) ← x, x, MBE, RBE PC11–0 ← (taddr) 3–0 + (taddr+1) SP ← SP–6 ––––––––––––––––––––––––––––––––––––– –––– 3 Depending on the reference instruction µPD753304 12. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25 °C) Parameter Symbol Conditions Ratings Unit –0.3 to +7.0 V Supply voltage VDD Input voltage VI –0.3 to VDD + 0.3 V Output voltage VO –0.3 to VDD + 0.3 V High-level output current IOH Per pin –10 mA Total of all pins –30 mA Per pin 30 mA Total of all pins 220 mA Low-level output current IOL Ambient operating temperature TA –10 to +60 °C Storage temperature Tstg –65 to +150 °C Caution If any of the parameters exceeds the absolute maximum ratings, even momentarily, the quality of the product may be impaired. The absolute maximum ratings are values that may physically damage the product(s). Be sure to use the product(s) within the ratings. Capacitance (TA = 25 °C, V DD = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Input capacitance CIN f = 1 MHz 15 pF Output capacitance COUT Pins other than tested pins: 0 V 15 pF I/O capacitance CIO 15 pF 41 µPD753304 Main System Clock Oscillation Circuit Characteristics (TA = –10 to +60 °C, VDD = 2.5 to 5.5 V) Oscillator Recommended Constants RC oscillation CL1 Note CL2 Parameter Conditions MIN. Oscillation frequency (fCC) Note VDD = 4.5 to 5.5 V VDD = 2.5 to 4.5 V TYP. MAX. Unit 1.0 6.0 MHz 1.0 5.0 MHz The oscillation frequency indicates characteristics of the oscillation circuit only. For the instruction execution time and oscillation frequency characteristics, refer to AC Characteristics. Caution When using the main system clock frequency circuit, wire the portion enclosed by the dotted line in the above figure as follows to prevent adverse influence from wiring capacitance: • Keep the wiring length as short as possible. • Do not cross the wiring with any other signal lines. • Do not route the wiring in the vicinity of line through which a high alternating current flows. • Do not extract any signal from the oscillation circuit. Subsystem Clock Oscillation Circuit Characteristics (TA = –10 to +60 °C, V DD = 2.5 to 5.5 V) Oscillation RC oscillation Notes 1. Note 1 Parameter Oscillation frequency (fCT) Note 2 Conditions MIN. TYP. MAX. Unit VDD = 5.0 V ± 10 % 27 47 74 kHz VDD = 3.0 V ± 10 % 27 47 74 kHz The subsystem clock oscillation circuit incorporates a resistor (R) and a capacitor (C), and does not have external pins. 2. The oscillation frequency indicates characteristics of the oscillation circuit only. For the instruction execution time and oscillation frequency characteristics, refer to AC Characteristics. 42 µPD753304 DC Characteristics (TA = –10 to +60 °C, VDD = 2.5 to 5.5 V) Parameter Low-level output current High-level input voltage Symbol IOL Conditions MIN. TYP. MAX. Unit Par pin 15 mA Total of all pins 150 mA VIH1 Ports 3, 8, P100-P102 0.7VDD VDD V VIH2 P103, RESET 0.8VDD VDD V VIL1 Ports 3, 8, P100-P102 0 0.3VDD V VIL2 P103, RESET 0 0.2VDD V VOH1 P31-P33, Ports 8, 10 VOH2 P30 (HCLK) VOL1 P31-P33, Ports 8, 10 VOL2 P30 (HCLK) High-level input leakage current ILIH1 VIN = VDD Low-level input leakage current ILIL1 High-level output leakage current ILOH Low-level output leakage current Internal pull-up resistor Low-level input voltage High-level output voltage Low-level output voltage IOH = –1.0 mA VDD – 0.5 V VDD – 0.12 V 0.4 V 0.19 V Pins other than CL1 3 µA CL1 20 µA Pins other than CL1 –3 µA CL1 –20 µA VOUT = VDD 3 µA ILOL VOUT = 0 V –3 µA RL1 Port 10 50 100 200 kΩ RL2 RESET (Mask option) 30 60 120 kΩ 5.5 V 200 kΩ 0 ±0.2 V 0 ±0.2 V ILIH2 VIN = 0 V ILIL2 IOL = 1.6 mA LCD drive voltage VLCD 2.5 LCD divider resistor RLCD 50 LCD output voltage deviation Note 1 (common) VODC LCD output voltage deviation Note 1 (segment) VODS Notes 1. Note 2 2.5 V ≤ VLCD ≤ VDD 100 “Voltage deviation” means a difference between the output voltage and the ideal value of the segment and common outputs (VLCDn: n = 0, 1, or 2). 2. The LCD controller/driver can select the following three display modes using a mask option: (1) Static : VLCD0 = V LCD (2) 1/2 bias: VLCD0 = V LCD VLCD1 = V LCD × 1/2 (3) 1/3 bias: VLCD0 = V LCD VLCD1 = V LCD × 2/3 VLCD2 = V LCD × 1/3 43 µPD753304 DC Characteristics (TA = –10 to +60 °C, VDD = 2.5 to 5.5 V) Parameter Supply current Note 1 Symbol IDD1 Note 2 Conditions Main system clock 3.6 MHz RC oscillation Operation mode IDD2 Note 2 Main system clock 3.6 MHz RC oscillation HALT mode IDD3 Note 5 Subsystem clock RC oscillation Operation mode IDD4 Note 5 Subsystem clock RC oscillation HALT mode IDD4 Note 8 STOP mode Notes 1. 2. TYP. MAX. Unit 2.1 5.3 mA VDD = 5.0 V ± 10 %, TA = 25 °C Note 3 2.1 4.2 mA VDD = 3.0 V ± 10 % Note 4 0.70 1.8 mA VDD = 3.0 V ± 10 %, TA = 25 °C Note 4 0.70 1.5 mA VDD = 5.0 V ± 10 % 1.4 3.5 mA VDD = 5.0 V ± 10 %, TA = 25 °C 1.4 2.8 mA VDD = 3.0 V ± 10 % 0.65 1.6 mA VDD = 3.0 V ± 10 %, TA = 25 °C 0.65 1.3 mA VDD = 5.0 V ± 10 % Note 6 65 163 µA VDD = 5.0 V ± 10 %, TA = 25 °C Note 6 65 130 µA VDD = 3.0 V ± 10 % Note 7 18 45 µA VDD = 3.0 V ± 10 %, TA = 25 °C Note 7 18 36 µA VDD = 5.0 V ± 10 % Note 6 58 150 µA VDD = 5.0 V ± 10 %, TA = 25 °C Note 6 58 120 µA VDD = 3.0 V ± 10 % Note 7 9.5 25 µA VDD = 3.0 V ± 10 %, TA = 25 °C Note 7 9.5 20 µA VDD = 5.0 V ± 10 % 0.05 10 µA VDD = 5.0 V ± 10 %, TA = 25 °C 0.05 5 µA VDD = 3.0 V ± 10 % 0.02 5 µA VDD = 3.0 V ± 10 %, TA = 25 °C 0.02 3 µA VDD = 5.0 V ± 10 % MIN. Note 3 The current flowing through the internal pull-up resistor and LCD divider resistor is not included. When an external 6.8-kΩ resistor is connected. However, the temperature characteristics of the resistor are not included. 3. When the µPD753304 operates in the high-speed mode with the processor clock control resistor (PCC) set to 0011. 4. When the µPD753304 operates in the low-speed mode with the PCC reset to 0000. 5. When the µPD753304 operates with the subsystem clock by setting the system clock control resistor (SCC) to 1001 and stopping the main system clock oscillation. 6. The subsystem clock oscillation frequency (fCT) is 60 kHz when V DD = 5.0 V ± 10%. 7. The subsystem clock oscillation frequency (fCT) is 55 kHz when V DD = 3.0 V ± 10%. 8. When both the main system clock and subsystem clock are stopped by setting the sub oscillation circuit stop enable flag (SOS.3) to 1. 44 µPD753304 AC Characteristics (TA = –10 to +60 °C, VDD = 2.5 to 5.5 V) Parameter Symbol Main system clock frequency deviation fCC Conditions MIN. TYP. MAX. Unit 3.1 3.7 4.3 MHz 3.3 3.7 4.0 MHz 2.8 3.6 4.2 MHz 3.0 3.6 3.9 MHz VDD = 5.0 V ± 10 % 27 47 74 kHz VDD = 3.0 V ± 10 % 27 47 74 kHz VDD = 5.0 V ± 10 % 45 55 % VDD = 3.0 V ± 10 % 40 60 % VDD = 4.5 to 5.5 V 0.67 64 µs VDD = 2.5 to 4.5 V 0.80 64 µs Operates with subsystem clock 54 148 µs INT1 10 µs 10 µs VDD = 5.0 V ± 10 %, R = 6.8 kΩ VDD = 3.0 V ± 10 %, R = 6.8 kΩ Subsystem clock frequency deviation fCT Main system clock duty factor Note 1 fduty Note 2 CPU clock cycle time (Minimum instruction execution time = 1 machine cycle) tCY Interrupt input high-, low-level width tINTH, tINTL RESET low-level width tRSL 2. TA = 25 °C Main system clock duty factor = high- tCY vs VDD level width of 1 clock/1 cycle of clock (Operates with main system clock) The cycle time (minimum instruction 64 60 execution time) of the CPU clock (Φ) when the device operates with the main 6 system clock is determined by the time 5 constant of the internal capacitor (C: Operation guaranteed range 10-pF typ.) and an externally connected resistor (R), and by the system clock control register (SCC) and processor clock control register (PCC). The cycle time of the CPU clock (Φ) when the device operates with the 4 Cycle time tCY (µs) Notes 1. Operates with main system clock TA = 25 °C 3 2 subsystem clock is determined by the time constant of the internal capacitor (C) and an internal resistor (R). 1 The figure on the right shows the 0.8 dependency of the cycle time tCY on 0.67 supply voltage V DD when the device operates with the main system clock. 0.5 0 1 2 2.5 3 3.3 4 4.5 5 5.5 6 Supply voltage VDD [V] 45 µPD753304 AC timing test points VIH (MIN.) VIH (MIN.) VIL (MAX.) VIL (MAX.) VOH (MIN.) VOH (MIN.) VOL (MAX.) VOL (MAX.) Interrupt input timing tINTL INT1 RESET input timing tRSL RESET 46 tINTH µPD753304 Data retention characteristics of data memory in STOP mode and at low supply voltage (TA = –10 to +60 °C) Parameter Symbol Release signal setup time tSREL Oscillation stabilization wait time Note 1 tWAIT Notes 1. Conditions MIN. TYP. MAX. Unit µs 0 Released by RESET 56/fCC µs Released by interrupt request Note 2 µs The oscillation stabilization wait time is the time during which the CPU stops operating to prevent unstable operation when oscillation is started. 2. Either 29/fCC or no wait can be selected by mask option. Data retention timing (when STOP mode released by RESET) Internal reset operation HALT mode STOP mode Operation mode Data retention mode VDD tSREL STOP instruction execution RESET tWAIT Data retention timing (standby release signal: when STOP mode released by interrupt signal) HALT mode STOP mode Operation mode Data retention mode VDD tSREL STOP instruction execution Standby release signal (interrupt request) tWAIT 47 µPD753304 13. CHARACTERISTIC CURVE (reference) IDD vs VDD (main system clock : 3.6 MHz RC oscillation (with 6.8-kΩ external resistor connected), subsystem clock : 60 kHz RC oscillation) (TA = 25 °C) 10 5.0 PCC = 0011 PCC = 0010 PCC = 0001 PCC = 0000 Main system clock HALT mode + 60 kHz oscillation 1.0 Supply current IDD (mA) 0.5 0.1 Subsystem clock operation mode Subsystem clock HALT mode and main system clock STOP mode + 60 kHz oscillation 0.05 0.01 0.005 CL1 CL2 RC oscillation 6.8 kΩ 0.001 48 0 1 2 3 5 4 Supply voltage VDD (V) 6 7 8 µPD753304 APPENDIX A. µ PD75308B, 753108 AND 753304 FUNCTIONAL LIST µPD75308B Parameter µPD753108 Program memory Mask ROM 0000H to 1F7FH (8064 × 8 bits) Data memory 000H to 1FFH (512 × 4 bits) CPU 75X Standard Main system clock oscillation circuit Crystal/ceramic oscillation circuit Subsystem clock oscillation circuit Crystal oscillation circuit 17 Mask ROM 0000H to 1FFFH (8192 × 8 bits) µPD753304 Mask ROM 0000H to 0FFFH (4096 × 8 bits) 000H to 0FFH (256 × 4 bits) 75XL CPU RC oscillation circuit RC oscillation circuit 17 15 Wait time when released by RESET signal 2 /fX Wait time when STOP mode is released by interrupt occurrence 220/fX, 217/fX, 215/fX, 213/fX (Selected by setting of BTM) 512/fCC, with no wait (Selected by mask option) Clock oscillation circuit which can executes STOP instruction Main system clock oscillation circuit Main system clock oscillation circuit and subsystem clock oscillation circuit When main system clock is selected 0.95, 1.91, 15.3 µs (during 4.19-MHz operation) 1.1, 2.2, 4.4, 17.8 µs (during 3.6-MHz operation) When subsystem clock is selected 122 µs (during 32.768-kHz operation) SBS register None SBS.3 = 1: Mk I mode selection SBS.3 = 0: Mk II mode selection Stack area 000H to 0FFH 000H to 1FFH Subroutine call instruction stack operation 2-byte stack When Mk I mode: 2-byte stack When Mk II mode: 3-byte stack BRA !addr1 CALLA !addr1 Unavailable When Mk I mode: unavailable When Mk II mode: available Instruction execution time Stack Instruction MOVT XA, @BCDE MOVT XA, @BCXA BR BCDE BR BCXA I/O port 2 /fX, 2 /fX (Selected by mask option) • 0.95, 1.91, 3.81, 15.3 µs (during 4.19-MHz operation) • 0.67, 1.33, 2.67, 10.7 µs (during 6.0-MHz operation) 56/fCC 85.1 µs (during 47-kHz operation) 0000H to 0FFH Available CALL !addr 3 machine cycles Mk I mode: 3 machine cycles, Mk II mode: 4 machine cycles CALLF !faddr 2 machine cycles Mk I mode: 2 machine cycles, Mk II mode: 3 machine cycles CMOS input 8 8 0 CMOS input/output 16 20 12 Bit port output 8 0 0 N-ch open-drain input/output 8 4 0 Total 40 32 12 49 µPD753304 µPD75308B µPD753108 µPD753304 Segment selection: 24/28/32 segments (can be changed to CMOS I/O port in 4 time-unit; max. 8) Segment selection: 16/20/24 segments (can be changed to CMOS I/O port in 4 time-unit; max. 8) Segment selection: 20/24 segments (can be changed to CMOS I/O port in 4-time unit; max. 4) Parameter LCD controller/driver Display mode selection: static, 1/2 duty (1/2 bias), 1/3 duty (1/2 bias), 1/3 duty (1/3 bias), 1/4 duty (1/3 bias) On-chip split resistor for LCD driver can be specified by using mask option On-chip split resistor for LCD driver LCD driving voltage can not be selected Timer 3 channels • Basic interval timer: 1 channel • 8-bit timer/event counter: 1 channel • Watch timer: 1 channel 5 channels • Basic interval timer/ watchdog timer: 1 channel • 8-bit timer/event counter: 3 channels (can be used as 16-bit timer/event counter) • Watch timer: 1 channel 3 channels • Basic interval timer/ watchdog timer: 1 channel • 8-bit timer counter: 1 channel (with subclock source input function) • Watchtimer: 1 channel Clock output (PCL) • Φ, 524, 262, 65.5 kHz (Main system clock: during 4.19-MHz operation) • Φ, 524, 262, 65.5 kHz (Main system clock: during 4.19-MHz operation) • Φ, 750, 375, 93.8 kHz (Main system clock: during 6.0-MHz operation) • Φ, 3.6 MHz, 450 kHz, 225 kHz (Main system clock: during 3.6-MHz operation) BUZ output (BUZ) 2 kHz (Main system clock: during 4.19-MHz operation) • 2, 4, 32 kHz (Main system clock: during 4.19-MHz operation or subsystem clock: during 32.768-kHz operation) • 2.93, 5.86, 46.9 kHz (Main system clock: 6.0-MHz operation) • 2.94, 5.88, 47 kHz (Subsystem clock: during 47-kHz operation) • 1.76, 3.52, 28.13-kHz (Main system clock: during 3.6-MHz operation) Serial interface 3 modes are available • 3-wire serial I/O mode ... MSB/LSB can be selected for transfer first bit • 2-wire serial I/O mode • SBI mode None Feedback resistor cut flag (SOS.0) None Contained None Subsystem clock oscillation circuit current cut flag (SOS.1) None Contained None Sub oscillation circuit stop enable flag (SOS.3) None SOS register Contained Register bank selection register (RBS) None Yes Vectored interrupt External: 3, internal: 3 External: 3, internal: 5 External: 1, internal: 2 Supply voltage VDD = 2.0 to 6.0 V VDD = 1.8 to 5.5 V VDD = 2.5 to 5.5 V Operating ambient temperature TA = –40 to +85 ˚C Package • 80-pin plastic QFP (14 × 20 mm) • 80-pin plastic QFP (14 × 14 mm) • 80-pin plastic TQFP (Fine pitch) (12 × 12 mm) 50 TA = –10 to +60 °C • 64-pin plastic QFP (14 × 14 mm) • 64-pin plastic QFP (12 × 12 mm) • Volume production product: Pellet/wafer • ES product (for evaluation): 42-pin ceramic shrink DIP (600 mil) µPD753304 APPENDIX B. DEVELOPMENT TOOLS The following development tools are provided for system development using the µPD753304. In the 75XL series, the relocatable assembler which is common to the series is used in combination with the device file of each product. Language processor RA75X relocatable assembler Host machine OS PC-9800 series 3.5-inch 2HD µS5A13RA75X Ver. 3.30 to 5-inch 2HD µS5A10RA75X Note IBM PC/AT™ and Refer to 3.5-inch 2HC µS7B13RA75X compatible machines “OS for IBM PC” 5-inch 2HC µS7B10RA75X Host machine OS PC-9800 series Distribution media MS-DOS Ver. 3.30 to Ver. 6.2 Note Part number (product name) MS-DOS™ Ver. 6.2 Device file Distribution media Part number (product name) 3.5-inch 2HD µS5A13DF753304 5-inch 2HD µS5A10DF753304 Note IBM PC/AT and Refer to 3.5-inch 2HC µS7B13DF753304 compatible machines “OS for IBM PC” 5-inch 2HC µS7B10DF753304 Ver.5.00 and later have the task swap function, but it cannot be used for this software. Remark Operation of the assembler and the device file are guaranteed only on the above host machine and OSs. 51 µPD753304 Debugging tool The in-circuit emulators (IE-75000-R and IE-75001-R) are available as the program debugging tool for the µPD753304. The system configurations are described as follows. Hardware IE-75000-R Note 1 IE-75001-R In-circuit emulator for debugging the hardware and software when developing the application systems that use the 75X series and 75XL series. When developing a µPD753304, the emulation board IE-75300-R-EM and emulation probe EP-753304DU-R that are sold separately must be used with the IE-75000-R. By connecting with the host machine, efficient debugging can be made. It contains the emulation board IE-75000-R-EM which is connected. In-circuit emulator for debugging the hardware and software when developing the application systems that use the 75X series and 75XL series. When developing a µPD753304, the emulation board IE-75300-R-EM and emulation probe EP-753304DU-R which are sold separately must be used with the IE-75001-R. It can debug the system efficiently by connecting the host machine. Software IE-75300-R-EM Emulation board for evaluating the application systems that use a µPD753304. It must be used with the IE-75000-R or IE-75001-R. EP-753304DU-R Emulation probe for ES products. It must be connected to IE-75000-R (or IE-75001-R) and IE-75300-R-EM. IE control program Connects the IE-75000-R or IE-75001-R to a host machine via RS-232-C and Centronix I/F and controls the above hardware on a host machine. Host machine OS PC-9800 series Distribution media MS-DOS Ver. 3.30 to Ver. 6.2 IBM PC/AT and compatible machines Notes 1. 3.5-inch 2HD µS5A13IE75X 5-inch 2HD µS5A10IE75X 3.5-inch 2HC µS7B13IE75X 5-inch 2HC µS7B10IE75X Note 2 Refer to “OS for IBM PC” Maintenance parts. 2. Remark Part No. (product name) Ver.5.00 and later have the task swap function, but it cannot be used for this software. Operation of the IE control program is guaranteed only on the above host machines and OSs. OS for IBM PC The following IBM PC OS’s are supported. OS Version PC DOS™ Ver. 5.02 to Ver. 6.3 J6.1/V Note to J6.3/V Note MS-DOS Ver. 5.0 to Ver. 6.22 5.0/V Note to 6.2/V Note IBM DOS™ J5.02/V Note Note Only the English mode is supported. Caution 52 Ver. 5.0 and later have the task swap function, but it cannot be used for this software. µPD753304 APPENDIX C. RELATED DOCUMENTS The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Device Related Documents Document No. Document Name English Japanese µPD753304 Data Sheet This document U11874J µPD753304 User’s Manual U12020E U12020J 75XL Series Selection Guide U10453E U10453J Development Tool Related Documents Document No. Document Name English Hardware Software Japanese IE-75000-R/IE-75001-R User’s Manual EEU-1416 EEU-846 IE-75300-R-EM User’s Manual U11354E U11354J EP-753304DU-R User’s Manual U12173E U12173J RA75X Assembler Package Operation EEU-1346 U12622J User’s Manual Language EEU-1363 U12385J Other Related Documents Document No. Document Name English Japanese IC Package Manual C10943X Semiconductor Device Mounting Technology Manual C10535E C10535J Quality Grades on NEC Semiconductor Devices C11531E C11531J NEC Semiconductor Device Reliability/Quality Control System C10983E C10983J Electrostatic Discharge (ESD) Test C11892E C11892J Guide to Quality Assurance for Semiconductor Devices MEI-1202 C11893J — U11416J Microcomputer related Product Guide - Other Manufacturers Caution The above related documents are subject to change without notice. For design purpose, etc., be sure to use the latest documents. 53 µPD753304 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 54 µPD753304 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics Hong Kong Ltd. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860 United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583 NEC Electronics (France) S.A. NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics Italiana s.r.1. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics Taiwan Ltd. NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951 NEC do Brasil S.A. Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689 J96. 8 55 µPD753304 MS-DOS is a registered trademark or trademark of Microsoft Corporation in the United States and/or other countries. IBM DOS, PC/AT, and PC DOS are trademarks of IBM Corporation. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5 46