DATA SHEET MOS INTEGRATED CIRCUIT µPD754264 4-BIT SINGLE-CHIP MICROCONTROLLERS DESCRIPTION The µPD754264 is a 4-bit single-chip microcontroller which incorporates the EEPROMTM for key-less entry application. It incorporates a 32 × 8-bit EEPROM, a CPU performing operation, a 4-Kbyte mask ROM to store software, a 128 × 4-bit RAM to store the operation data, an 8-bit resolution A/D converter, and a carrier generator which easily outputs waveforms for infrared remote controller. The details of functions are described in the following user’s manual. Be sure to read it before designing. µPD754264 User’s Manual: U12287E FEATURES • On-chip EEPROM: 32 × 8 bits (mapped to the data memory) • On-chip key return reset function for key-less entry • On-chip low-voltage A/D converter (AVREF = 1.8 to 6.0 V), 8-bit resolution × 2 channels • Low-voltage operation: VDD = 1.8 to 6.0 V • Timer function (4 channels) • Basic interval timer/watchdog timer : 1 channel • 8-bit timer counter : 3 channels • On-chip memory • Program memory (ROM) 4096 × 8 bits • Data memory (static RAM) 128 × 4 bits • Instruction execution time variable function suited for high-speed operation and power saving. 0.95, 1.91, 3.81, 15.3 µs (@ fX = 4.19-MHz operation) 0.67, 1.33, 2.67, 10.7 µs (@ fX = 6.0-MHz operation) APPLICATIONS Automotive appliances such as key-less entry, compact data carrier, etc. ORDERING INFORMATION Part Number µPD754264GS-×××-BA5 Package 20-pin plastic SOP (300 mil, 1.27-mm pitch) Remark ××× indicates ROM code suffix. The information in this document is subject to change without notice. Document No. U12487EJ1V1DS00 Date Published January 1999 N CP(K) Printed in Japan The mark shows major revised points. © 1997 µPD754264 Functional Outline Parameter Function Instruction execution time • 0.95, 1.91, 3.81, 15.3 µs (@ f X = 4.19-MHz operation) • 0.67, 1.33, 2.67, 10.7 µs (@ f X = 6.0-MHz operation) On-chip memory Mask ROM 4096 × 8 bits (0000H-0FFFH) RAM 128 × 4 bits (000H-07FH) EEPROM 32 × 8 bits (400H-43FH) System clock oscillator General-purpose register Crystal/ceramic oscillator • 4-bit operation: 8 × 4 banks • 8-bit operation: 4 × 4 banks 2 Input/output CMOS input 4 On-chip pull-up resistor can be specified by mask option. port CMOS input/output 9 On-chip pull-up resistor connection can be specified by means of software. Total 13 Start-up time after reset 217/f X, 2 15/f X, 2 13/f X (selected by mask option) Stand-by mode release time 220/f X, 2 17/f X, 215/f X, 213/f X (selected by the setting of BTM) Timer 4 channels • 8-bit timer counter (can be used as 16-bit timer counter) : 3 channels • Basic interval/watchdog timer : 1 channel A/D converter 8-bit resolution × 2 channels (1.8 V ≤ AV REF ≤ V DD) Bit sequential buffer 16 bits Vectored interrupt External: 1, Internal: 5 Test input External: 1 (key return reset function available) Standby function STOP/HALT mode Operating ambient temperature TA = –40 to +85 °C Operating supply voltage VDD = 1.8 to 6.0 V Package 20-pin plastic SOP (300 mil, 1.27-mm pitch) µPD754264 CONTENTS 1. PIN CONFIGURATION (TOP VIEW) ................................................................................................... 5 2. BLOCK DIAGRAM ............................................................................................................................... 6 3. PIN FUNCTION .................................................................................................................................... 7 3.1 Port Pins ..................................................................................................................................... 7 3.2 Non-port Pins ............................................................................................................................. 8 3.3 Pin Input/Output Circuits .......................................................................................................... 9 3.4 Recommended Connection of Unused Pins ......................................................................... 10 4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE ............................................... 11 4.1 Difference between Mk I and Mk II Modes ............................................................................. 11 4.2 Setting Method of Stack Bank Select Register (SBS) .......................................................... 12 5. MEMORY CONFIGURATION ............................................................................................................ 13 6. EEPROM ............................................................................................................................................ 16 7. PERIPHERAL HARDWARE FUNCTIONS ........................................................................................ 7.1 Digital Input/Output Ports ....................................................................................................... 7.2 Clock Generator ....................................................................................................................... 7.3 Basic Interval Timer/Watchdog Timer ................................................................................... 7.4 Timer Counter .......................................................................................................................... 7.5 A/D Converter ........................................................................................................................... 7.6 Bit Sequential Buffer ............................................................................................................... 8. INTERRUPT FUNCTION AND TEST FUNCTION ............................................................................. 26 9. STANDBY FUNCTION ....................................................................................................................... 28 17 17 17 19 20 24 25 10. RESET FUNCTION ............................................................................................................................ 29 10.1 Configuration and Operation Status of RESET Function .................................................... 29 10.2 Watchdog Flag (WDF), Key Return Flag (KRF) ..................................................................... 33 11. MASK OPTION .................................................................................................................................. 35 12. INSTRUCTION SETS ........................................................................................................................ 36 13. ELECTRICAL SPECIFICATIONS ..................................................................................................... 45 14. CHARACTERISTICS CURVES (REFERENCE VALUES) ................................................................ 55 15. PACKAGE DRAWINGS..................................................................................................................... 58 16. RECOMMENDED SOLDERING CONDITIONS................................................................................. 59 3 µPD754264 APPENDIX A. COMPARISON OF FUNCTIONS BETWEEN µPD754264 AND 75F4264 ...................... 60 APPENDIX B. DEVELOPMENT TOOLS ................................................................................................. 61 APPENDIX C. RELATED DOCUMENTS ................................................................................................ 64 4 µPD754264 1. PIN CONFIGURATION (TOP VIEW) • 20-pin Plastic SOP (300 mil, 1.27-mm pitch) µPD754264GS-×××-BA5 RESET 1 20 KRREN X1 2 19 P80 X2 3 18 P30/PTO0 VSS 4 17 P31/PTO1 IC 5 16 P32/PTO2 VDD 6 15 P33 P60/AVREF 7 14 P70/KR4 P61/INT0 8 13 P71/KR5 P62/AN0 9 12 P72/KR6 P63/AN1 10 11 P73/KR7 IC: Internally Connected (Connect to VDD directly) Pin Identification AN0, AN1 : Analog input 0,1 P70 to P73 : Port 7 AVREF : Analog reference P80 : Port 8 IC : Internally connected PTO0 to PTO2 : Programmable timer outputs 0 to 2 INT0 : External vectored interrupt 0 RESET : Reset KR4 to KR7 : Key returns 4 to 7 VDD : Positive power supply KRREN : Key return reset enable VSS : Ground P30 to P33 : Port 3 X1 and X2 : System clock (crystal/ceramic) P60 to P63 : Port 6 5 µPD754264 2. BLOCK DIAGRAM BASIC INTERVAL TIMER/WATCHDOG TIMER PORT3 4 P30 to P33 PORT6 4 P60 to P63 PORT7 4 P70 to P73 SP (8) INTBT RESET CY ALU PTO0/P30 8-BIT TIMER COUNTER#0 INTT0 TOUT SBS PROGRAM COUNTER INTT1 PTO1/P31 PTO2/P32 BANK 8-BIT TIMER COUNTER#1 CASCADED 8-BIT TIMER COUNTER#2 16-BIT TIMER COUNTER GENERAL REG. PROGRAM MEMORY (ROM) 4096 × 8 BITS INTT2 DATA MEMORY (RAM) 128 × 4 BITS PORT8 P80 EEPROM 32 × 8 BITS INT0/P61 KRREN INTERRUPT CONTROL BIT SEQ. BUFFER (16) DECODE AND CONTROL KR4/P70 to 4 KR7/P73 fX/2N AVREF/P60 AN0/P62 CPU CLOCK φ CLOCK SYSTEM CLOCK STAND BY CONTROL DIVIDER GENERATOR A/D CONVERTER X1 AN1/P63 6 X2 IC VDD VSS RESET µPD754264 3. PIN FUNCTION 3.1 Port Pins Pin Name P30 Input/Output Alternate Function Input/Output PTO0 P31 PTO1 P32 PTO2 P33 – P60 Input/Output AVREF P61 INT0 P62 AN0 P63 AN1 P70 Input KR4 P71 KR5 P72 KR6 P73 KR7 P80 Input/Output – Function 8-bit I/O Circuit After Reset I/O TYPE Note 1 Programmable 4-bit input/output port (PORT3). This port can be specified input/output bitwise. On-chip pull-up resistor connection can be specified by software in 4-bit units. – Input E-B Programmable 4-bit input/output port (PORT6). This port can be specified input/output bitwise. On-chip pull-up resistor can be specified by software in 4-bit unitsNote2. – Input F -A Noise eliminator can be selected with P61/ INT0. 4-bit input port (PORT7). On-chip pull-up resistor can be specified by software bit-wise. – Input B -A 1-bit input/output port (PORT8). On-chip pull-up resistor connection can be specified by software. – Input F -A Notes 1. Circled characters indicate the Schmitt-trigger input. 2. Do not specify an on-chip pull-up resistor connection when using the A/D converter. 7 µPD754264 3.2 Non-port Pins Pin Name PTO0 Input/Output Alternate Function Output P30 PTO1 P31 PTO2 P32 INT0 Input P61 KR4 to KR7 Input P70 to P73 AN0 Input P62 AN1 I/O Circuit TYPE Note 1 Input E-B Input F -A Falling edge detection testable input pins Input B -A Analog signal input Input F -A Key return reset enable pin The reset signal is generated at the falling edge of KRn while KRREN is high in STOP mode. Input B A/D converter reference voltage Input F -A Timer counter output pins Edge detection vectored interrupt input pin (detected edge can be selected) Noise elimination circuit can be selected. Noise elimination circuit can be selected. Asynchronous input P63 KRREN Input – AVREF Input P60 X1 Input – – – X2 – Crystal/ceramic resonator (for system clock oscillation) connection pin When inputting the external clock, input the external clock to pin X1 and input the inverted phase of the external clock to pin X2. Input – System reset input pin (low-level active) Pull-up resistor can be incorporated (mask option). – B -A IC – – Internally Connected – – V DD – – Positive supply pin – – V SS – – Ground potential – – RESET Note 8 After Reset Function Circled characters indicate the Schmitt-trigger input. Connect directly to VDD. µPD754264 3.3 Pin Input/Output Circuits The µPD754264 pin input/output circuits are shown schematically. TYPE A TYPE D VDD VDD data P-ch OUT P-ch IN N-ch CMOS specification input buffer. N-ch output disable Push-pull output that can be placed in output high-impedance (both P-ch, N-ch off). TYPE E-B TYPE B VDD P.U.R. P.U.R. enable IN P-ch data Type D IN/OUT output disable Type A Schmitt-trigger input having hysteresis characteristic. P.U.R. : Pull-Up Resistor TYPE F-A TYPE B-A VDD VDD P.U.R. P.U.R. enable P.U.R. (Mask Option) P-ch data IN output disable P.U.R. : Pull-Up Resistor IN/OUT Type D Type B P.U.R. : Pull-Up Resistor 9 µPD754264 3.4 Recommended Connection of Unused Pins Table 3-1. List of Recommended Connection of Unused Pins Pin Recommended Connecting Method P30/PTO0 Input state : Independently connect to VSS or V DD via a resistor. P31/PTO1 Output state: Leave open. P32/PTO2 P33 P60/AVREF P61/INT0 P62/AN0 P63/AN1 P70/KR4 Connect to VDD. P71/KR5 P72/KR6 P73/KR7 P80 Input state : Independently connect to VSS or VDD via a resistor. Output state: Leave open. 10 KRREN When this pin is connected to VDD, internal reset signal is generated at the falling edge of the KRn pin in the STOP mode. When this pin is connected to VSS, internal reset signal is not generated even if the falling edge of KRn pin is detected in the STOP mode. IC Connect directly to VDD. µPD754264 4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE 4.1 Difference between Mk I and Mk II Modes The µPD754264 75XL CPU has the following two modes: Mk I and Mk II, either of which can be selected. The mode can be switched by the bit 3 of the Stack Bank Select register (SBS). • Mk I mode: Instructions are compatible with the 75X Series. Can be used in the 75XL CPU with a ROM capacity of up to 16 Kbytes. • Mk II mode: Incompatible with 75X Series. Can be used in all the 75XL CPU’s including those products whose ROM capacity is more than 16 Kbytes. Table 4-1. Differences between Mk I Mode and Mk II Mode Mk I Mode Mk II Mode Number of stack bytes for subroutine instructions 2 bytes 3 bytes BRA !addr1 instruction CALLA !addr1 instruction Not available Available CALL !addr instruction 3 machine cycles 4 machine cycles CALLF !faddr instruction 2 machine cycles 3 machine cycles Caution The Mk II mode supports a program area exceeding 16 Kbytes for the 75X and 75XL Series. Therefore, this mode is effective for enhancing software compatibility with products that have a program area of more than 16 Kbytes. With regard to the number of stack bytes during execution of subroutine call instructions, the usable area increases by 1 byte per stack compared to the Mk I mode when the Mk II mode is selected. However, when the CALL !addr and CALLF !faddr instructions are used, the machine cycle becomes longer by 1 machine cycle. Therefore, if more emphasis is placed on RAM use efficiency and processing performance than on software compatibility, the Mk I mode should be used. 11 µPD754264 4.2 Setting Method of Stack Bank Select Register (SBS) Switching between the Mk I mode and Mk II mode can be done by the SBS. Figure 4-1 shows the format. The SBS is set by a 4-bit memory manipulation instruction. When using the Mk I mode, the SBS must be initialized to 1000B at the beginning of a program. When using the Mk II mode, it must be initialized to 0000B. Figure 4-1. Stack Bank Select Register Format Address 3 F84H SBS3 2 1 SBS2 SBS1 0 Symbol SBS0 SBS Stack area specification 0 0 Memory bank 0 Other than above setting prohibited 0 0 must be set in the bit 2 position Mode switching specification 0 Mk II mode 1 Mk I mode Caution Because SBS. 3 is set to “1” after a RESET signal is generated, the CPU operates in the Mk I mode. When executing an instruction in the Mk II mode, set SBS. 3 to “0” to select the Mk II mode. 12 µPD754264 5. MEMORY CONFIGURATION • Program memory (ROM) • • • 4096 × 8 bits • Addresses 0000H and 0001H Vector table wherein the program start address and the values set for the RBE and MBE at the time a RESET signal is generated are written. Reset and start are possible at an arbitrary address. • Addresses 0002H to 000FH Vector table wherein the program start address and values set for the RBE and MBE by the vectored interrupts are written. Interrupt service can be started at an arbitrary address. • Addresses 0020H to 007FH Table area referenced by the GETI instructionNote. Note The GETI instruction realizes a 1-byte instruction on behalf of an arbitrary 2-byte instruction, 3-byte instruction, or two 1-byte instructions. It is used to decrease the program steps. • Data memory • Data area Static RAM • • • 128 words × 4 bits (000H to 07FH) EEPROM ••• • Peripheral hardware area 32 words × 8 bits (400H to 43FH) • • • 128 words × 4 bits (F80H to FFFH) 13 µPD754264 Figure 5-1. Program Memory Map Address 0000H 7 6 5 4 MBE RBE 0 0 0001H 0002H MBE RBE 0 0 0003H 0004H MBE RBE 0 0 0005H 0 Internal reset start address (high-order 4 bits) Internal reset start address (low-order 8 bits) INTBT start address (high-order 4 bits) INTBT start address (low-order 8 bits) INT0 start address (high-order 4 bits) INT0 start address (low-order 8 bits) CALLF !faddr instruction entry address 0006H 0007H 0008H 0009H 000AH MBE RBE 0 0 000BH 000CH MBE RBE 0 0 000DH 000EH 000FH MBE RBE 0 0 INTT0 start address (high-order 4 bits) INTT0 start address (low-order 8 bits) INTT1/INTT2 start address (high-order 4 bits) INTT1/INTT2 start address (low-order 8 bits) INTEE start address (high-order 4 bits) INTEE start address (low-order 8 bits) Branch address of BR !addr BRCB !caddr BR BCDE BR BCXA BRA !addrNote CALL !addr CALLA !addrNote instructions GETI Branch/call Addresses BR $addr instruction relative branch address (–15 to –1, +2 to +16) 0020H GET instruction reference table 007FH 0080H 07FFH 0800H 0FFFH Note Can be used in the MkII mode only. Remark In addition to the above, a branch can be made to an address with the low-order 8-bits only of the PC changed by means of a BR PCDE or BR PCXA instruction. 14 µPD754264 Figure 5-2. Data Memory Map Data memory 000H General-purpose register area 01FH 020H Data area static RAM (128 × 4) Memory bank (32 × 4) Stack area 128 × 4 (96 × 4) 0 07FH 080H 0FFH Not incorporated 400H Data area EEPROM (32 × 8) 32 × 8 4 43FH 440H 4FFH Not incorporated F80H 128 × 4 Peripheral hardware area 15 FFFH 15 µPD754264 6. EEPROM The µPD754264 incorporates 32 words × 8 bit EEPROM (Electrically Erasable PROM) as well as static RAM (128 words × 4 bit) as a data memory. The EEPROM incorporated into the µPD754264 has the following features. (1) Written data is retained if power is turned off. (2) 8-bit data manipulation (auto-erase/auto-write) is available by memory manipulation instruction as well as for static RAM. However available instructions are restricted. (3) It can reduce loads of software because the auto-erase and/or auto-write operation is performed by hardware. (4) Write operation control using the interrupt request The interrupt request is generated under following conditions. • Terminates write operation • Write status flag It is possible to check whether enables or disables write operation by bit manipulation instructions. 16 µPD754264 7. PERIPHERAL HARDWARE FUNCTIONS 7.1 Digital Input/Output Ports The following two types of I/O ports are provided. • CMOS input (Port 7) : 4 • CMOS I/O (Ports 3, 6, 8) : 9 Total : 13 Table 7-1. Types and Features of Digital Ports Port Name PORT3 Function 4-bit I/O Operation and Features Can be set to input or output mode bit-wise. PORT6 PORT7 Remarks Also used as PTO0 to PTO2 pins. Also used as AVREF, INT0, AN0, and AN1 pins. 4-bit input 4-bit input only port On-chip pull-up resistor connection can be specified Also used as KR4 to KR7 pins. by mask option bit-wise. PORT8 1-bit I/O Can be set to input or output mode bit wise. – 7.2 Clock Generator The clock generator provides the clock signals to the CPU and peripheral hardware. Its configuration is shown in Figure 7-1. The operation of the clock generator is set with the processor clock control register (PCC). The instruction execution time can be changed. • 0.95, 1.91, 3.81, 15.3 µs (when the system clock fX operates at 4.19 MHz) • 0.67, 1.33, 2.67, 10.7 µs (when the system clock fX operates at 6.0 MHz) 17 µPD754264 Figure 7-1. Clock Generator Block Diagram · Basic interval timer (BT) · Timer counter · INT0 noise eliminator X1 X2 System clock oscillator 1/1~1/4096 fX Divider Oscillation stops Selector 1/2 1/4 1/16 Divider Internal bus 1/4 Φ · CPU · INT0 noise eliminator PCC PCC0 PCC1 HALT F/F 4 PCC2 S HALTNote PCC3 R STOPNote PCC2, PCC3 clear Q STOP F/F Q S R Wait release signal from BT Reset signal Standby release signal from interrupt control circuit Note Instruction execution Remarks 1. fX: System clock frequency 2. F = CPU clock 3. PCC: Processor Clock Control Register 4. One clock cycle (tCY) of the CPU clock is equal to one machine cycle of the instruction. 18 µPD754264 7.3 Basic Interval Timer/Watchdog Timer The basic interval timer/watchdog timer has the following functions. (a) Interval timer operation to generate a reference time interrupt (b) Watchdog timer operation to detect a runaway of program and reset the CPU (c) Selects and counts the wait time when the standby mode is released (d) Reads the contents of counting Figure 7-2. Basic Interval Timer/Watchdog Timer Block Diagram From clock generator Clear fX/25 fX/27 MPX Clear Basic interval timer (8-bit frequency divider) Set fX/29 BT fX/212 3 Wait release signal when standby is releasedNote 1. BTM3 BTM2 BTM1 BTM0 BTM SET1Note 2 4 BT interrupt request flag Vectored interrupt IRQBT request signal Internal reset signal WDTM SET1Note 2 8 1 Internal bus Notes 1. The wait time can be specified when the standby mode is released. 2. Instruction execution. 19 µPD754264 7.4 Timer Counter The µPD754264 incorporates three channels of timer counters. Its configuration is shown in Figures 7-3 to 7-5. The timer counter has the following functions. (a) Programmable interval timer operation (b) Square wave output of any frequency to PTO0-PTO2 pins (c) Count value read function The timer counter can operate in the following four modes as set by the mode register. Table 7-2. Mode List Channel Mode Channel 0 Channel 1 Channel 2 8-bit timer counter mode TM21 TM20 0 0 0 0 0 0 0 1 × 16-bit timer counter mode × 1 0 1 0 Carrier generator mode × 0 0 1 1 : Available × : Not available 20 TM10 PWM pulse generator mode Remark × TM11 Figure 7-3. Timer Counter (Channel 0) Block Diagram Internal bus 8 SET1Note 8 8 – TM06 TM05 TM04 TM03 TM02 0 TOE0 TMOD0 TM0 T0 enable flag Modulo register (8) 0 PORT3.0 P30 Output latch PMGA bit 0 Port 3 input/output mode 8 Match Comparator (8) TOUT F/F P30/PTO0 Output buffer 8 Reset T0 fx/24 From clock fx/26 generator fx/28 fx/210 MPX CP Count register (8) Clear Timer operation start INTT0 IRQT0 set signal RESET IRQT0 clear signal Note Instruction execution Caution When setting data to TM0, be sure to set bits 0 and 1 to 0. µPD754264 21 22 Figure 7-4. Timer Counter (Channel 1) Block Diagram Internal bus 8 SETNote TOE1 TM1 – 8 T1 enable flag TM16 TM15 TM14 TM13 TM12 TM11 TM10 TMOD1 Decoder PORT3.1 P31 Output latch PMGA bit 1 Port 3 input/output mode Modulo register (8) 8 Match Comparator (8) Timer counter (channel 2) output From clock generator fx/25 fx/26 fx/28 TOUT F/F 8 P31/PTO1 Output buffer Reset T1 MPX CP Count register (8) Clear fx/210 fx/212 RESET Timer operation start 16 bit timer counter mode IRQT1 clear signal Selector Timer counter (channel 2) match signal (When 16-bit timer counter mode) Timer counter (channel 2) reload signal INTT1 IRQT1 set signal Timer counter (channel 2) comparator (When 16-bit timer counter mode) µPD754264 Note Instruction execution Figure 7-5. Timer Counter (Channel 2) Block Diagram Internal bus 8 TM2 TM26 TM25 TM24 TM23 TM22 TM21 TM20 8 TMODH High-level period setting modulo register (8) Modulo register (8) 8 – – – TC2 PORT3.2 Output latch TOE2 REMC NRZB NRZ Reload Match TOUT F/F Comparator (8) 8 Reset T2 MPX PMGA bit 2 Port 3 input/output mode MPX (8) 8 From clock generator 0 8 Decoder fx fx/2 fx/24 fx/26 fx/28 fx/210 8 TMOD2 CP Overflow Count register (8) P32/PTO2 Output buffer Selector – SET Selector 8 Note Timer counter (channel 1) clock input Carrier generator mode Clear INTT2 IRQT2 set signal 16-bit timer counter mode IRQT2 clear signal Timer operation start RESET Timer counter (channel 1) clear signal (When 16-bit timer mode) Timer counter (channel 1) match signal (When 16-bit timer counter mode) Timer counter (channel 1) match signal (When Carrier generator mode) Note Instruction execution Caution When setting data to TC2, be sure to set bit 7 to 0. µPD754264 23 µPD754264 7.5 A/D Converter The µPD754264 incorporates an 8-bit resolution A/D converter with 2-channel analog inputs (AN0 and AN1). This A/D converter employes successive approximation. Figure 7-6. A/D Converter Block Diagram Internal bus 8 ADEN 0 0 ADM4 SOC EOC 0 0 ADM 8 Controller Sample hold circuit + AN0/P62 SA register (8) Multiplexer – AN1/P63 Comparator 8 Tap decoder AVREF/P60 R/2 VSS ADEN 24 R R R R/2 µPD754264 7.6 Bit Sequential Buffer ....... 16 Bits The bit sequential buffer (BSB) is a special data memory for bit manipulation and the bit manipulation can be easily performed by changing the address specification and bit specification in sequence, therefore it is useful when processing large data bit-wise. Figure 7-7. Bit Sequential Buffer Format FC3H Address 3 Bit Symbol L register 2 1 FC2H 0 3 2 BSB3 L = FH 1 FC1H 0 3 BSB2 L = CH L = BH 2 1 FC0H 0 3 BSB1 L = 8H L = 7H 2 1 0 BSB0 L = 4H L = 3H L = 0H DECS L INCS L Remarks 1. In the pmem.@L addressing, the specified bit moves corresponding to the L register. 2. In the pmem.@L addressing, the BSB can be manipulated regardless of MBE/MSB specification. 25 µPD754264 8. INTERRUPT FUNCTION AND TEST FUNCTION Figure 8-1 shows the interrupt control circuit. Each hardware device is mapped in the data memory space. The interrupt control circuit of the µPD754264 has the following functions. (1) Interrupt function • Vectored interrupt function for hardware control, enabling/disabling the interrupt acknowledgement by the interrupt enable flag (IE×××) and interrupt master enable flag (IME). • Can set any interrupt start address. • Multiple interrupts wherein the order of priority can be specified by the interrupt priority select register (IPS). • Test function of interrupt request flag (IRQ×××). An interrupt generated can be checked by software. • Release the standby mode. A release interrupt can be selected by the interrupt enable flag. (2) Test function • Test request flag (IRQ2) generation can be checked by software. • Release the standby mode. The test source to be released can be selected by the test enable flag. 26 Figure 8-1. Interrupt Control Circuit Block Diagram Internal bus 2 4 Interrupt enable flag (IE×××) IM2 IME IPS IST1 IST0 IM0 Decoder VRQn INT0/P61 KR4/P70 Note1 Selector INTBT Edge detector IRQBT IRQ0 INTT0 IRQT0 INTT1 IRQT1 INTT2 IRQT2 INTEE IRQEE Falling edge detectorNote2 Priority control ciricuit Vector table address generator IRQ2 KR7/P73 Key return reset circuit IM2 2. The INT2 pin is not provided. Interrupt request flag (IRQ2) is set at the KRn pin falling edge when IM20 = 1 and IM21 = 0. 27 µPD754264 Notes 1. Noise eliminator (Standby release is disable when noise eliminator is selected.) Standby release signal µPD754264 9. STANDBY FUNCTION In order to reduce power dissipation while a program is in a standby mode, two types of standby modes (STOP mode and HALT mode) are provided for the µPD754264. Table 9-1. Operation Status in Standby Mode Mode Item Set instruction Operation Clock generator status STOP Mode HALT Mode STOP instruction Operation stops. HALT instruction Only the CPU clock Φ halts (oscillation continues). Basic interval timer/ watchdog timer Operation stops. Operable BT mode: The IRQBT is set in the basic time interval. WT mode: Reset is generated by the BT overflow. Timer counter Operation stops. External interrupt Operable. Note INT0 is not operable. INT2 is operable during KRn falling period only. CPU Release signal The operation stops. • Reset signal • Reset signal • Interrupt request signal sent from • Interrupt request signal sent from interrupt enabled peripheral hardware interrupt enabled peripheral hardware • System reset signal (key return reset) generated by KRn falling edge when the KRREN pin = 1 Note Can operate only when the noise eliminator is not used (IM02 = 1) by bit 2 of the edge detection mode register (IM0). 28 µPD754264 10. RESET FUNCTION 10.1 Configuration and Operation Status of RESET Function There are three kinds of reset input: the external reset signal (RESET), the reset signal sent from the basic interval/ watchdog timer, and the reset signal generated by a falling edge signal from KRn in the STOP mode. When any of these reset signals is input, an internal reset signal is generated. The configuration is shown in Figure 10-1. Figure 10-1. Configuration of Reset Function VDD Mask option RESET Internal reset signal Output buffer Watchdog timer overflow S R Q WDF Q KRF Instruction KRREN S R Q R S Instruction STOP mode VDD One-shot pulse generator Interrupt Falling edge detector Mask option P71/KR5 P72/KR6 Internal bus P70/KR4 P73/KR7 29 µPD754264 Each hardware is initialized by the RESET signal generation as listed in Table 10-1. Figure 10-2 shows the timing chart of the reset operation. Figure 10-2. Reset Operation by RESET Signal Generation WaitNote RESET signal generated Operation mode or standby mode HALT mode Operation mode Internal reset operation Note The wait time can be selected from the following three time settings by means of the mask option. 217/fX (21.8 ms : @ 6.0-MHz operation, 31.3 ms: @ 4.19-MHz operation) 215/fX (5.46 ms : @ 6.0-MHz operation, 7.81 ms: @ 4.19-MHz operation) 213/fX (1.37 ms : @ 6.0-MHz operation, 1.95 ms: @ 4.19-MHz operation) 30 µPD754264 Table 10-1. Hardware Status After Reset (1/3) Hardware Program counter (PC) PSW Carry flag (CY) Skip flag (SK0 to SK2) Interrupt status flag (IST0, IST1) Bank enable flag (MBE, RBE) Stack pointer (SP) Stack bank select register (SBS) RESET signal generation in the standby mode RESET signal generation in operation Sets the low-order 4 bits of program memory’s address 0000H to the PC11-PC8 and the contents of address 0001H to the PC7-PC0. Sets the low-order 4 bits of program memory’s address 0000H to the PC11-PC8 and the contents of address 0001H to the PC7-PC0. Held Undefined 0 0 0 Sets the bit 6 of program memory’s address 0000H to the RBE and bit 7 to the MBE. Undefined 0 Sets the bit 6 of program memory’s address 0000H to the RBE and bit 7 to the MBE. Undefined 1000B 1000B Held Undefined HeldNote 1 HeldNote 2 0 0 General-purpose register (X, A, H, L, D, E, B, C) Held Undefined Bank select register (MBS, RBS) 0, 0 0, 0 Undefined Undefined Mode register (BTM) 0 0 Watchdog timer enable flag (WDTM) 0 0 Counter (T0) 0 0 FFH FFH Data memory (RAM) Data memory (EEPROM) EEPROM write control register (EWC) Basic interval timer/watchdog timer Timer counter (channel 0) Counter (BT) Modulo register (TMOD0) Mode register (TM0) TOE0, TOUT F/F Timer counter (channel 1) Counter (T1) Modulo register (TMOD1) Mode register (TM1) TOE1, TOUT F/F Timer counter (channel 2) Counter (T2) 0 0 0, 0 0, 0 0 0 FFH FFH 0 0 0, 0 0, 0 0 0 Modulo register (TMOD2) FFH FFH High-level period setting modulo FFH FFH register (TMOD2H) Mode register (TM2) TOE2, TOUT F/F REMC, NRZ, NRZB 0 0 0, 0 0, 0 0, 0, 0 0, 0, 0 Notes 1. Undefined if STOP mode is entered during an EEPROM write operation. Also undefined if HALT mode is entered during a write operation and a RESET signal is input during a write operation. 2. If a RESET signal is input during an EEPROM write operation, the data at that address is undefined. 31 µPD754264 Table 10-1. Hardware Status After Reset (2/3) RESET signal generation in the standby mode RESET signal generation in operation Mode register (ADM) 04H 04H SA register (SA) 7FH 7FH 0 0 Hardware A/D converter Clock generator Processor clock control register (PCC) Interrupt Interrupt request flag (IRQ×××) Reset (0) Reset (0) function Interrupt enable flag (IE×××) 0 0 Interrupt priority selection register (IPS) 0 0 INT0, 2 mode registers (IM0, IM2) 0, 0 0, 0 Output buffer Off Off Output latch Cleared (0) Cleared (0) 0 0 Digital port I/O mode registers (PMGA, C) Pull-up resistor setting register (POGA, B) Bit sequential buffer (BSB0 to BSB3) 0 0 Held Undefined Table 10-1. Hardware Status After Reset (3/3) RESET signal generation by key return reset RESET signal generation in the standby mode RESET signal generation by WDT during operation RESET signal generation during operation Watchdog flag (WDF) Hold the previous status 0 1 0 Key return flag (KRF) 1 0 Hold the previous status 0 Hardware 32 µPD754264 10.2 Watchdog Flag (WDF), Key Return Flag (KRF) The WDF is cleared by a watchdog timer overflow signal, and the KRF is set by a reset signal generated by the KRn pins. As a result, by checking the contents of WDF and KRF, it is possible to know what kind of reset signal is generated. As the WDF and KRF are cleared only by external signal or instruction execution, if once these flags are set, they are not cleared until an external signal is generated or a clear instruction is executed. Check and clear the contents of WDF and KRF after reset start operation by executing SKTCLR instruction and so on. Table 10-2 lists the contents of WDF and KRF corresponding to each signal. Figure 10-3 shows the WDF operation in generating each signal, and Figure 10-4 shows the KRF operation in generating each signal. Table 10-2. WDF and KRF Contents Correspond to Each Signal Reset signal Reset signal External RESET generation by watch- generation by the signal generation dog timer overflow KRn input Hardware WDF clear instruction execution KRF clear instruction execution Watchdog flag (WDF) 0 1 Hold 0 Hold Key return flag (KRF) 0 Hold 1 Hold 0 Figure 10-3. WDF Operation in Generating Each Signal Reset signal generation by watchdog timer overflow External RESET signal generation Reset signal generation by watchdog timer overflow WDF clear instruction execution WDF External RESET Operation mode HALT mode Operation mode HALT mode Operation mode HALT mode Operation mode Operation mode Internal reset operation Internal reset operation Internal reset operation 33 µPD754264 Figure 10-4. KRF Operation in Generating Each Signal Reset signal generation by the KRn input Reset signal generation by the KRn input External RESET signal generation STOP instruction execution STOP instruction execution KRF clear instruction execution KRF External RESET Operation mode STOP mode HALT mode Operation mode HALT mode Operation mode STOP mode HALT mode Operation mode Operation mode Internal reset operation 34 Internal reset operation Internal reset operation µPD754264 11. MASK OPTION The µPD754264 has the following mask options: • Mask option of P70/KR4 to P73/KR7 On-chip pull-up resistor connection can be specified for these pins. <1> Do not connect an on-chip pull-up resistor <2> Connect the 30-kΩ (typ.) pull-up resistor bit-wise • Mask option of RESET pin On-chip pull-up resistor connection can be specified for this pin. <1> Do not connect an on-chip pull-up resistor <2> Connect the 100-kΩ (typ.) pull-up resistor • Standby function mask option The wait time when the RESET signal is input can be selected. <1> 217/fX (21.8 ms: @ fX = 6.0-MHz operation, 31.3 ms: @ fX = 4.19-MHz operation) <2> 215/fX (5.46 ms: @ fX = 6.0-MHz operation, 7.81 ms: @ fX = 4.19-MHz operation) <3> 213/fX (1.37 ms: @ fX = 6.0-MHz operation, 1.95 ms: @ fX = 4.19-MHz operation) 35 µPD754264 12. INSTRUCTION SETS (1) Expression formats and description methods of operands The operand is described in the operand column of each instruction in accordance with the description method for the operand expression format of the instruction. For details, refer to “RA75X ASSEMBLER PACKAGE USERS’ MANUAL — LANGUAGE (EEU-1367)”. If there are several elements, one of them is selected. Capital letters and the + and – symbols are key words and are described as they are. For immediate data, appropriate numbers and labels are described. Instead of the labels such as mem, fmem, pmem, and bit, the symbols of the registers can be described. However, there are restrictions in the labels that can be described for fmem and pmem. For details, refer to “µPD754264 user's manual (U12287E)”. Expression format Description method reg reg1 X, A, B, C, D, E, H, L X, B, C, D, E, H, L rp rp1 rp2 rp' rp'1 XA, BC, DE, HL BC, DE, HL BC, DE XA, BC, DE, HL, XA', BC', DE', HL' BC, DE, HL, XA', BC', DE', HL' rpa rpa1 HL, HL+, HL–, DE, DL DE, DL n4 n8 4-bit immediate data or label 8-bit immediate data or label mem 8-bit immediate data or labelNote bit 2-bit immediate data or label fmem pmem FB0H-FBFH, FF0H-FFFH immediate data or label FC0H-FFFH immediate data or label addr addr1 caddr 000H-FFFH immediate data or label 000H-FFFH immediate data or label 12-bit immediate data or label faddr 11-bit immediate data or label taddr 20H-7FH immediate data (where bit 0 = 0) or label PORTn IE××× RBn MBn PORT3, 6, 7, 8 IEBT, IET0-IET2, IE0, IE2, IEEE RB0-RB3 MB0, MB4, MB15 Note mem can be only used for even address in 8-bit data processing. 36 µPD754264 (2) Legend in explanation of operation A : A register, 4-bit accumulator B : B register C : C register D : D register E : E register H : H register L : L register X : X register XA : XA register pair; 8-bit accumulator BC : BC register pair DE : DE register pair HL : HL register pair XA’ : XA’ extended register pair BC’ : BC’ extended register pair DE’ : DE’ extended register pair HL’ : HL’ extended register pair PC : Program counter SP : Stack pointer CY : Carry flag, bit accumulator PSW : Program status word MBE : Memory bank enable flag RBE : Register bank enable flag PORTn : Port n (n = 3, 6, 7, 8) IME : Interrupt master enable flag IPS : Interrupt priority selection register IE××× : Interrupt enable flag RBS : Register bank selection register MBS : Memory bank selection register PCC : Processor clock control register . : Separation between address and bit (××) : The contents addressed by ×× ××H : Hexadecimal data 37 µPD754264 (3) Explanation of symbols under addressing area column *1 MB = MBE•MBS (MBS = 0, 4, 15) *2 MB = 0 *3 MBE = 0 : MB = 0 (000H to 07FH) MB = 15 (F80H to FFFH) MBE = 1 : MB = MBS (MBS = 0, 4, 15) *4 MB = 15, fmem = FB0H to FBFH, FF0H to FFFH *5 MB = 15, pmem = FC0H to FFFH *6 addr = 000H to FFFH *7 addr = (Current PC) – 15 to (Current PC) – 1 (Current PC) + 2 to (Current PC) + 16 addr1 = (Current PC) – 15 to (Current PC) – 1 (Current PC) + 2 to (Current PC) + 16 *8 caddr = 000H to FFFH *9 faddr = 0000H to 07FFH *10 taddr = 0020H to 007FH *11 addr1 = 000H to FFFH Data memory addressing Program memory addressing Remarks 1. MB indicates memory bank that can be accessed. 2. In *2, MB = 0 independently of how MBE and MBS are set. 3. In *4 and *5, MB = 15 independently of how MBE and MBS are set. 4. *6 to *11 indicate the areas that can be addressed. (4) Explanation of number of machine cycles column S denotes the number of machine cycles required by skip operation when a skip instruction is executed. The value of S varies as follows. • When no skip is made: S = 0 • When the skipped instruction is a 1- or 2-byte instruction: S = 1 • When the skipped instruction is a 3-byte instructionNote: S = 2 Note 3-byt-e instruction: BR !addr, BRA !addr1, CALL !addr, or CALLA !addr1 instruction Caution The GETI instruction is skipped in one machine cycle. One machine cycle is equal to one cycle of CPU clock (= tCY); time can be selected from among four types by setting PCC. 38 µPD754264 Instruction group Transfer instruction Mnemonic MOV XCH Table reference instructions MOVT Operand Number Number of machine of bytes cycles Operation Addressing area Skip condition A, #n4 1 1 A ← n4 reg1, #n4 2 2 reg1 ← n4 XA, #n8 2 2 XA ← n8 String effect A HL, #n8 2 2 HL ← n8 String effect B rp2, #n8 2 2 rp2 ← n8 A, @HL 1 1 A ← (HL) *1 A, @HL+ 1 2+S A ← (HL), then L ← L+1 *1 L=0 A, @HL– 1 2+S A ← (HL), then L ← L–1 *1 L = FH A, @rpa1 1 1 A ← (rpa1) *2 XA, @HL 2 2 XA ← (HL) *1 @HL, A 1 1 (HL) ← A *1 @HL, XA 2 2 (HL) ← XA *1 A, mem 2 2 A ← (mem) *3 XA, mem 2 2 XA ← (mem) *3 mem, A 2 2 (mem) ← A *3 mem, XA 2 2 (mem) ← XA *3 A, reg 2 2 A ← reg XA, rp' 2 2 XA ← rp' reg1, A 2 2 reg1 ← A rp'1, XA 2 2 rp'1 ← XA A, @HL 1 1 A ↔ (HL) *1 A, @HL+ 1 2+S A ↔ (HL), then L ← L+1 *1 L=0 A, @HL– 1 2+S A ↔ (HL), then L ← L–1 *1 L = FH A, @rpa1 1 1 A ↔ (rpa1) *2 XA, @HL 2 2 XA ↔ (HL) *1 A, mem 2 2 A ↔ (mem) *3 XA, mem 2 2 XA ↔ (mem) *3 A, reg1 1 1 A ↔ reg1 XA, rp' 2 2 XA ↔ rp' XA, @PCDE 1 3 XA ← (PC 11–8+DE)ROM XA, @PCXA 1 3 XA ← (PC11–8+XA)ROM XA, @BCDE 1 3 XA ← (BCDE)ROMNote *6 XA, @BCXA 1 3 XA ← (BCXA)ROMNote *6 String effect A Note Set “0” in register B. 39 µPD754264 Instruction group Bit transfer instructions Operation instructions Mnemonic Operation Addressing area Skip condition 2 2 CY ← (fmem.bit) *4 CY, pmem.@L 2 2 CY ← (pmem7–2+L3–2.bit(L1–0)) *5 CY, @H+mem.bit 2 2 CY ← (H+mem3–0.bit) *1 fmem.bit, CY 2 2 (fmem.bit) ← CY *4 pmem.@L, CY 2 2 (pmem7–2+L3–2.bit(L1–0)) ← CY *5 @H+mem.bit, CY 2 2 (H+mem3–0.bit) ← CY *1 A, #n4 1 1+S A ← A+n4 carry XA, #n8 2 2+S XA ← XA+n8 carry A, @HL 1 1+S A ← A+(HL) XA, rp' 2 2+S XA ← XA+rp' carry rp'1, XA 2 2+S rp'1 ← rp'1+XA carry A, @HL 1 1 A, CY ← A+(HL)+CY XA, rp' 2 2 XA, CY ← XA+rp'+CY rp'1, XA 2 2 rp'1, CY ← rp'1+XA+CY A, @HL 1 1+S A ← A–(HL) XA, rp' 2 2+S XA ← XA–rp' borrow rp'1, XA 2 2+S rp'1 ← rp'1–XA borrow A, @HL 1 1 A, CY ← A–(HL)–CY XA, rp' 2 2 XA, CY ← XA–rp'–CY rp'1, XA 2 2 rp'1, CY ← rp'1–XA–CY A, #n4 2 2 A ← A ∧ n4 A, @HL 1 1 A ← A ∧ (HL) XA, rp' 2 2 XA ← XA ∧ rp' rp'1, XA 2 2 rp'1 ← rp'1 ∧ XA A, #n4 2 2 A ← A ∨ n4 A, @HL 1 1 A ← A ∨ (HL) XA, rp' 2 2 XA ← XA ∨ rp' rp'1, XA 2 2 rp'1 ← rp'1 ∨ XA A, #n4 2 2 A ← A v n4 A, @HL 1 1 A ← A v (HL) XA, rp' 2 2 XA ← XA v rp' rp'1, XA 2 2 rp'1 ← rp'1 v XA RORC A 1 1 CY ← A0, A3 ← CY, An–1 ← An NOT A 2 2 A←A ADDS SUBS SUBC AND OR XOR 40 Number Number of machine of bytes cycles CY, fmem.bit MOV1 ADDC Accumulator manipulation instructions Operand *1 carry *1 *1 *1 *1 *1 *1 borrow µPD754264 Instruction group Increment and Decrement instructions Mnemonic Carry flag manipulation instruction Memory bit manipulation instructions Number Number of machine of bytes cycles Operation Addressing area Skip condition reg 1 1+S reg ← reg+1 reg=0 rp1 1 1+S rp1 ← rp1+1 rp1=00H @HL 2 2+S (HL) ← (HL)+1 *1 (HL)=0 mem 2 2+S (mem) ← (mem)+1 *3 (mem)=0 reg 1 1+S reg ← reg–1 reg=FH rp' 2 2+S rp' ← rp'–1 rp'=FFH reg, #n4 2 2+S Skip if reg = n4 reg=n4 @HL, #n4 1 2+S Skip if (HL) = n4 *1 (HL) = n4 A, @HL 2 1+S Skip if A = (HL) *1 A = (HL) XA, @HL 2 2+S Skip if XA = (HL) *1 XA = (HL) A, reg 2 2+S Skip if A = reg A=reg XA, rp' 2 2+S Skip if XA = rp' XA=rp' SET1 CY 1 1 CY ← 1 CLR1 CY 1 1 CY ← 0 SKT CY 1 1+S NOT1 CY 1 1 CY ← CY SET1 mem.bit 2 2 (mem.bit) ← 1 *3 fmem.bit 2 2 (fmem.bit) ← 1 *4 pmem.@L 2 2 (pmem7–2+L3–2.bit(L1–0)) ← 1 *5 @H+mem.bit 2 2 (H+mem3–0.bit) ← 1 *1 mem.bit 2 2 (mem.bit) ← 0 *3 fmem.bit 2 2 (fmem.bit) ← 0 *4 pmem.@L 2 2 (pmem7–2+L3–2.bit(L1–0)) ← 0 *5 @H+mem.bit 2 2 (H+mem3–0.bit) ← 0 *1 mem.bit 2 2+S Skip if (mem.bit)=1 *3 (mem.bit)=1 fmem.bit 2 2+S Skip if (fmem.bit)=1 *4 (fmem.bit)=1 pmem.@L 2 2+S Skip if (pmem7–2+L3–2.bit(L1–0))=1 *5 (pmem.@L)=1 @H+mem.bit 2 2+S Skip if (H+mem3–0.bit)=1 *1 (@H+mem.bit)=1 mem.bit 2 2+S Skip if (mem.bit)=0 *3 (mem.bit)=0 fmem.bit 2 2+S Skip if (fmem.bit)=0 *4 (fmem.bit)=0 pmem.@L 2 2+S Skip if (pmem7–2+L3–2.bit(L1–0))=0 *5 (pmem.@L)=0 @H+mem.bit 2 2+S Skip if (H+mem3–0.bit)=0 *1 (@H+mem.bit)=0 INCS DECS Comparison instruction Operand SKE CLR1 SKT SKF Skip if CY = 1 CY=1 41 µPD754264 Instruction group Memory bit manipulation instructions Mnemonic SKTCLR AND1 OR1 XOR1 Branch instructions BRNote 1 BRA Note 1 BRCB Operand Number Number of machine of bytes cycles Operation Addressing area fmem.bit 2 2+S Skip if (fmem.bit)=1 and clear *4 (fmem.bit)=1 pmem.@L 2 2+S Skip if (pmem7–2+L3–2.bit(L1–0))=1 and clear *5 (pmem.@L)=1 @H+mem.bit 2 2+S Skip if (H+mem3–0.bit)=1 and clear *1 (@H+mem.bit)=1 CY, fmem.bit 2 2 CY ← CY ∧ (fmem.bit) *4 CY, pmem.@L 2 2 CY ← CY ∧ (pmem7–2+L3–2.bit(L1–0)) *5 CY, @H+mem.bit 2 2 CY ← CY ∧ (H+mem3–0.bit) *1 CY, fmem.bit 2 2 CY ← CY ∨ (fmem.bit) *4 CY, pmem.@L 2 2 CY ← CY ∨ (pmem7–2+L3–2.bit(L1–0)) *5 CY, @H+mem.bit 2 2 CY ← CY ∨ (H+mem3–0.bit) *1 CY, fmem.bit 2 2 CY ← CY v (fmem.bit) *4 CY, pmem.@L 2 2 CY ← CY v (pmem7–2+L3–2.bit(L1–0)) *5 CY, @H+mem.bit 2 2 CY ← CY v (H+mem3–0.bit) *1 addr – – PC11–0 ← addr Select appropriate instruction among BR !addr BRCB !caddr, and BR $addr according to the assembler being used. *6 addr1 – – PC11–0 ← addr Select appropriate instruction among BR !addr BRA !addr1, BRCB !caddr and BR $addr1 according to the assembler being used. *11 ! addr 3 3 PC11–0 ← addr *6 $addr 1 2 PC11–0 ← addr *7 $addr1 1 2 PC11–0 ← addr1 PCDE 2 3 PC11–0 ← PC11-8+DE PCXA 2 3 PC11–0 ← PC11-8+XA BCDE 2 3 PC11–0 ← BCDENote 2 *6 BCXA 2 3 PC11–0 ← BCXANote 2 *6 !addr1 3 3 PC11–0 ← addr1 *11 !caddr 2 2 PC11–0 ← caddr11–0 *8 Notes 1. The above operations in the double boxes can be performed only in the Mk II mode. 2. “0” must be set to B register. 42 Skip condition µPD754264 Instruction group Subroutine stack control instructions Mnemonic Operand Number Number of machine of bytes cycles Operation Addressing area CALLANote !addr1 3 3 (SP–2) ← ×, ×, MBE, RBE (SP–6) (SP–3) (SP–4) ← PC11–0 (SP–5) ← 0, 0, 0, 0 PC11–0 ← addr1, SP ← SP–6 *11 CALLNote !addr 3 3 (SP–3) ← MBE, RBE, 0, 0 (SP–4) (SP–1) (SP–2) ← PC11–0 PC11–0 ← addr, SP ← SP–4 *6 4 (SP–2) ← ×, ×, MBE, RBE (SP–6) (SP–3) (SP–4) ← PC11–0 (SP–5) ← 0, 0, 0, 0 PC11–0 ← addr, SP ← SP–6 2 (SP–3) ← MBE, RBE, 0, 0 (SP–4) (SP–1) (SP–2) ← PC11–0 PC11–0 ← 0+faddr, SP ← SP–4 3 (SP–2) ← ×, ×, MBE, RBE (SP–6) (SP–3) (SP–4) ← PC11–0 (SP–5) ← 0, 0, 0, 0 PC11–0 ← 0+faddr, SP ← SP–6 3 PC11–0 ← (SP) (SP+3) (SP+2) MBE, RBE, 0, 0 ← (SP+1), SP ← SP+4 CALLFNote !faddr RETNote 2 1 Skip condition *9 ×, ×, MBE, RBE ← (SP+4) 0, 0, 0, 0, ← (SP+1) PC11–0 ← (SP) (SP+3) (SP+2), SP ← SP+6 RETSNote 1 3+S MBE, RBE, 0, 0 ← (SP+1) PC11–0 ← (SP) (SP+3) (SP+2) SP ← SP+4 then skip unconditionally Unconditional 0, 0, 0, 0 ← (SP+1) PC11–0 ← (SP) (SP+3) (SP+2) ×, ×, MBE, RBE ← (SP+4) SP ← SP+6 then skip unconditionally RETINote 1 3 MBE, RBE, 0, 0 ← (SP+1) PC11–0 ← (SP) (SP+3) (SP+2) PSW ← (SP+4) (SP+5), SP ← SP+6 0, 0, 0, 0 ← (SP+1) PC11–0 ← (SP) (SP+3) (SP+2) PSW ← (SP+4) (SP+5), SP ← SP+6 PUSH POP rp 1 1 (SP–1) (SP–2) ← rp, SP ← SP–2 BS 2 2 (SP–1) ← MBS, (SP–2) ← RBS, SP ← SP–2 rp 1 1 rp ← (SP+1) (SP), SP ← SP+2 BS 2 2 MBS ← (SP+1), RBS ← (SP), SP ← SP+2 Note The above operations in the double boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. 43 µPD754264 Instruction group Interrupt control instructions Mnemonic Operand 2 IME (IPS.3) ← 1 2 2 IE××× ← 1 2 2 IME (IPS.3) ← 0 IE××× 2 2 IE××× ← 0 A, PORTn 2 2 A ← PORTn (n = 3, 6, 7, 8) PORTn, A 2 2 PORTn ← A (n = 3, 6, 8) HALT 2 2 Set HALT Mode (PCC.2 ← 1) STOP 2 2 Set STOP Mode (PCC.3 ← 1) NOP 1 1 No Operation RBn 2 2 RBS ← n (n = 0-3) MBn 2 2 MBS ← n (n = 0, 4, 15) GETINotes 2, 3 taddr 1 3 • When TBR instruction PC11–0 ← (taddr) 3–0 + (taddr+1) IE××× INNote 1 OUT CPU control instructions Special instructions Addressing area Operation 2 EI DI Input/output instructions Number Number of machine of bytes cycles Note 1 SEL Skip condition *10 –––––––––––––––––––––––––––––––––– ––––––––––––– • When TCALL instruction (SP–4) (SP–1) (SP–2) ← PC11–0 (SP–3) ← MBE, RBE, 0, 0 PC11–0 ← (taddr) 3–0 + (taddr+1) SP ← SP–4 –––––––––––––––––––––––––––––––––– ––––––––––––– • When instruction other than TBR and TCALL instructions (taddr) (taddr+1) instruction is executed. 3 • When TBR instruction PC11–0 ← (taddr) 3–0 + (taddr+1) ––––––––––––––––––––––––––––––––––––– ––– 4 *10 ––––––––––––– • When TCALL instruction (SP–6) (SP–3) (SP–4) ← PC11–0 (SP–5) ← 0, 0, 0, 0 (SP–2) ← ×, ×, MBE, RBE PC11–0 ← (taddr) 3–0 + (taddr+1) SP ← SP–6 ––––––––––––––––––––––––––––––––––––– ––– 3 Depending on the reference instruction • When instruction other than TBR and TCALL instructions (taddr) (taddr+1) instruction is executed. ––––––––––––– Depending on the reference instruction Notes 1. While the IN instruction and OUT instruction are being executed, MBE must be set to 0, or MBE must be set to 1 and MBS must be set to 15. 2. The TBR and TCALL instructions are the table definition assembler pseudo instructions of the GETI instruction. 3. The above operations in the double boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. 44 µPD754264 13. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25°C) Parameter Symbol Test Conditions Ratings Unit –0.3 to +7.0 V Power supply voltage VDD Input voltage VI –0.3 to VDD + 0.3 V Output voltage VO –0.3 to VDD + 0.3 V Output current, high IOH P30, P31, P33, P60 to P63, P80 –10 mA P32 –20 mA Output current, low Operating ambient Per pin For all pins –30 mA Per pin 20 mA For all pins 90 mA TA –40 to +85 °C Tstg –65 to +150 °C IOLNote temperature Storage temperature Caution If any of the parameters exceeds the absolute maximum ratings, even momentarily, the quality of the product may be impaired. The absolute maximum ratings are values that may physically damage the products. Be sure to use the products within the ratings. Capacitance (TA = 25°C, VDD = 0 V) Parameter Input capacitance Symbol Test Conditions CIN f = 1 MHz Output capacitance COUT Unmeasured pins returned to 0 V I/O capacitance CIO MIN. TYP. MAX. Unit 15 pF 15 pF 15 pF 45 µPD754264 System Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 1.8 to 6.0 V) Resonator Recommended Constant Ceramic resonator X1 Testing Conditions Oscillation frequency (fX)Note1 X2 C1 Parameter C2 Crystal Oscillation stabilization timeNote 5 X1 C1 External clock frequency(fX) X2 C2 X1 X2 TYP. 1.0 MAX. 1.0 Unit 6.0Notes2, 3, 4 MHz 4 ms 6.0Notes2, 3, 4 MHz 10 ms 30 ms After VDD reaches MIN. value of oscillation voltage range Oscillation resonator MIN. Note1 Oscillation VDD = 4.5 to 6.0 V stabilization timeNote3 X1 input frequency (fX)Note1 1.0 6.0Notes2, 3, 4 MHz X1 input high- and low-level widths (tXH, tXL) 83.3 500 ns Notes 1. Only the oscillator characteristics are shown. For the instruction execution time, refer to AC Characteristics. 2. If the oscillation frequency is 2.1 MHz < fX ≤ 4.19 MHz at 1.8 V ≤ VDD < 2.0 V, set the processor control register (PCC) to a value other than 0011. If the PCC is set to 0011, the rated machine cycle time of 1.9 µs is not satisfied. 3. If the oscillation frequency is 4.19 MHz < fX ≤ 6.0 MHz at 1.8 V≤ VDD < 2.0 V, set the processor control register (PCC) to a value other than 0011 or 0010. If the PCC is set to 0011 or 0010, the rated machine cycle time of 1.9 µs is not satisfied. 4. If the oscillation frequency is 4.19 MHz < fX ≤ 6.0 MHz at 2.0 V≤ VDD < 2.7 V, set the processor control register (PCC) to a value other than 0011. If the PCC is set to 0011, the rated machine cycle time of 0.95 µs is not satisfied. 5. Oscillation stabilization time is a time required for oscillation to stabilize after application of VDD, or after the STOP mode has been released. Caution When using the oscillation circuit of the system clock, wire the portion enclosed in dotted lines in the figures as follows to avoid adverse influences on the wiring capacitance: • Keep the wire length as short as possible. • Do not cross other signal lines. • Do not route the wiring in the vicinity of lines though which a high fluctuating current flows. • Always keep the ground point of the capacitor of the oscillation circuit as the same potential as VSS. • Do not connect the power source pattern through which a high current flows. • Do not extract signals from the oscillation circuit. 46 µPD754264 Recommended Oscillator Constants Ceramic resonator (TA = –40 to +85°C) Manufacturer Part Number Frequency Recommended Oscillator Constant (pF) (MHz) Note Oscillation Voltage Range (VDD) C1 C2 MIN. (V) MAX. (V) 6.0 Murata Mfg. CSB1000J 1.0 100 100 1.8 Co., Ltd. CSA2.00MG040 2.0 100 100 1.9 — — 4.19 30 30 — — 6.0 30 30 CST6.00MGW — — CSA6.00MGU 30 30 CST6.00MGWU — — CST2.00MG040 CSA4.19MG CST4.19MGW CSA6.00MG Remark Rd = 2.2 kΩ — On-chip capacitor 1.8 — On-chip capacitor 2.0 — On-chip capacitor 1.8 — On-chip capacitor Note When using the CSB1000J (1.0 MHz) made by Murata Mfg. Co., Ltd. as a ceramic resonator, a limiting resistor (Rd = 2.2 kΩ) is necessary (refer to the figure below). This resistor is not necessary when using the other recommended resonators. X1 X2 CSB1000J Rd • • C2 C1 • Caution The oscillator constants and oscillation voltage range indicate conditions for stable oscillation, but do not guarantee oscillation frequency accuracy. If oscillation frequency accuracy is required for actual circuits, it is necessary to adjust the oscillation frequency of the oscillator in the actual circuit. Please contact directly the manufacturer of the resonator to be used. 47 µPD754264 DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 6.0 V) Parameter High-level output current Symbol IOH Conditions Per pin MIN. P30, P31, P33, P60 to P63, P80 IOL current High-level input –15 mA Total of all pins –20 mA Per pin 15 mA Total of all pins 45 mA 0.7VDD VDD V 1.8 V ≤ VDD < 2.7 V 0.9VDD VDD V 2.7 V ≤ VDD ≤ 6.0 V 0.8VDD VDD V 1.8 V ≤ VDD < 2.7 V 0.9VDD VDD V VDD – 0.1 VDD V 2.7 V ≤ VDD ≤ 6.0 V 0 0.3VDD V 1.8 V ≤ VDD < 2.7 V 0 0.1VDD V Ports 6 to 8, 2.7 V ≤ VDD ≤ 6.0 V 0 0.2VDD V KRREN, RESET 1.8 V ≤ VDD < 2.7 V 0 0.1VDD V 0 0.1 V Port 3 VIH2 Ports 6 to 8, KRREN, RESET VIH3 X1 VIL1 Port 3 voltage High-level VIL3 X1 VOH VDD = 4.5 to 6.0 V, IOH = –1.0 mA VDD – 1.0 V VDD = 1.8 to 6.0 V, IOH = –100 µA VDD – 0.5 V output voltage Low-level –7 2.7 V ≤ VDD ≤ 6.0 V VIH1 VIL2 Unit mA voltage Low-level input MAX. –5 P32, VDD = 3.0 V, VOH = VDD – 2.0 V Low-level output TYP. VOL VDD = 4.5 to 6.0 V 2.0 V 0.4 V VDD = 1.8 to 6.0 V, IOH = 400 µA 0.5 V VIN = VDD Pins other than X1 3.0 µA X1 20 µA Pins other than X1 –3.0 µA X1 –20 µA output voltage Port 3, IOL = 15 mA 0.6 Ports 6, 8, IOL = 1.6 mA High-level input ILIH1 leakage current ILIH2 Low-level input ILIL1 leakage current ILIH2 High-level output leakage current ILOH VOUT = VDD 3.0 µA Low-level output leakage current ILOL VOUT = 0 V –3.0 µA On-chip pull-up RL1 VIN = 0 V resistance RL2 48 VIN = 0 V Port 3, 6, 8 50 100 200 kΩ Port 7 (mask option) 15 30 60 kΩ RESET (mask option) 50 100 200 kΩ µPD754264 DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 6.0 V) Parameter Power supply Symbol IDD1 currentNote 1 IDD2 Conditions 4.19-MHz VDD = 5.0 V ±10% crystal VDD = 3.0 V ±10% oscillation C1 = C2 = 22 pF IDD3 MIN. X1 = 0 V Note 2 Note 3 TYP. MAX. Unit 1.5 5.0 mA 0.23 1.0 mA HALT VDD = 5.0 V ±10% 0.64 3.0 mA mode VDD = 3.0 V ±10% 0.20 0.9 mA 5 µA 1 µA 0.1 3 µA 0.1 1 µA VDD = 1.8 to 6.0 V STOP mode TA = 25°C VDD = 3.0 V ± 10% TA = –40 to +40°C Notes 1. The current flowing through the on-chip pull-up resistor, the current during EEPROM writing time, and the current during the A/D converter operation are not included. 2. When the device is operated in the high-speed mode by setting the processor clock control register (PCC) to 0011H 3. When the device is operated in the low-speed mode by setting PCC to 0000H 49 µPD754264 AC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 6.0 V) Parameter Note 1 CPU clock cycle time Symbol tCY (Minimum instruction execution time = 1 machine cycle) Interrupt input high- and tINTH, low-level width tINTL Test Conditions MIN. MAX. Unit VDD = 1.8 to 2.0 V 1.9 64.0 µs VDD = 2.0 to 2.7 V 0.95 64.0 µs VDD = 2.7 to 6.0 V 0.67 64.0 µs INT0 IM02 = 0 Note 2 µs IM02 = 1 10 µs 10 µs 10 µs KR4 to KR7 RESET low-level width TYP. tRSL Notes 1. The CPU clock (Φ) cycle time (minimum tCY vs. VDD instruction execution time) is determined by (During system clock operation) the oscillation frequency of the connected 64 60 resonator (or external clock) and the processor clock control register (PCC). The figure on the right shows the cycle time tCY charac- 6 teristics against the supply voltage VDD when 5 the system clock is used. interrupt mode register (IM0). Operation guranteed range Cycle time tCY (µ s) 2. 2tCY or 128/fX depending on the setting of the 4 3 2 1.9 1 0.95 0.67 0.5 50 0 1 1.8 2 2.7 3 4 5 Supply voltage VDD (V) 6 µPD754264 EEPROM Characteristics (TA = –40 to +85°C, VDD = 1.8 to 6.0 V) Parameter EEPROM Symbol IEEW write current EEPROM write time tEEW EEPROM EEWT overwrite times Conditions MIN. TYP. MAX. Unit 4.19 MHz, VDD = 5.0 V ± 10% 4.5 15 mA crystal oscillation VDD = 3.0 V ± 10% 2.0 6 mA 10.0 ms 3.8 TA = –40 to +50°C 100000 times/byte TA = –40 to +85°C 60000 times/byte A/D Converter Characteristics (TA = –40 to +85°C, VDD = 1.8 to 6.0 V, 1.8 V ≤ AVREF ≤ VDD) Parameter Symbol Conditions Resolution Absolute Accuracy Note 1 AVREF = VDD AVREF ≠ VDD MIN. TYP. 8 8 MAX. Unit 8 bit 2.7 ≤ VDD ≤ 6.0 V ±1.5 LSB 1.8 ≤ VDD < 2.7 V ±3.0 LSB 1.8 ≤ VDD ≤ 5.5 V ±3.0 LSB 1.8 ≤ VDD ≤ 6.0 V ±3.5 LSB 168/fX µs 44/fX µs AVREF V Conversion time tCONV Note 2 Sampling time tSAMP Note 3 Analog input voltage VIAN Analog input impedance RAN 1000 AVREF current IREF 0.25 VSS MΩ 2.0 mA Notes 1. Absolute error except quantizing error (±1/2 LSB) 2. The time from conversion start instruction execution to conversion end (ECC = 1) (40.1 µs: @ fX = 4.19-MHz operation) 3. The time from conversion start instruction execution to sampling end (10.5 µs: @ fX = 4.19-MHz operation) 51 µPD754264 AC Timing Test Points (Excluding X1 Input) VIH (MIN.) VIH (MIN.) VIL (MAX.) VIL (MAX.) VOH (MIN.) VOH (MIN.) VOL (MAX.) VOL (MAX.) Clock Timing 1/fX tXL X1 input tXH VDD – 0.1 V 0.1 V 52 µPD754264 Interrupt Input Timing tINTH tINTL INT0, KR4 to KR7 RESET Input Timing tRSL RESET Data Memory STOP Mode Low-Supply Voltage Data Retention Characteristics (TA = –40 to +85 °C) Parameter Symbol Release signal set time tSREL Oscillation stabilization tWAIT wait time Note 1 Test Conditions MIN. TYP. MAX. Unit µs 0 Release by RESET Note 2 ms Release by interrupt request Note 3 ms Notes 1. The oscillation stabilization wait time is the time during which the CPU operation is stopped to avoid unstable operation at oscillation start. 2. Any of 217/fX, 215/fX or 213/fX can be selected with mask option. 3. Depends on setting of basic interval timer mode register (BTM) (see table below). BTM3 BTM2 BTM1 Wait Time BTM0 When fX = 4.19 MHz – 0 0 0 When fX = 6.0 MHz 20 2 /fX (Approx. 175 ms) 17 2 /fX (Approx. 250 ms) 20 – 0 1 1 2 /fX (Approx. 31.3 ms) 217/fX (Approx. 21.8 ms) – 1 0 1 215/fX (Approx. 7.81 ms) 215/fX (Approx. 5.46 ms) – 1 1 1 213/fX (Approx. 1.95 ms) 213/fX (Approx. 1.37 ms) 53 µPD754264 Data Retention Timing (on releasing STOP mode by RESET) Internal reset operation HALT mode Operation mode STOP mode Data retention mode VDD tSREL Execution of STOP instruction RESET tWAIT Data Retention Timing (Standby release signal: on releasing STOP mode by interrupt signal) HALT mode STOP mode Operation mode Data retention mode VDD tSREL Execution of STOP instruction Standby release signal (interrupt request) tWAIT 54 µPD754264 14. CHARACTERISTICS CURVES (REFERENCE VALUES) IDD vs VDD (System Clock: 6.0-MHz Crystal Resonator) (TA = 25°C) 10 5.0 PCC = 0011 PCC = 0010 PCC = 0001 PCC = 0000 System clock HALT mode 1.0 Supply current IDD (mA) 0.5 0.1 0.05 0.01 0.005 X1 X2 Crystal resonator 6.0 MHz 22 pF 0.001 0 1 2 3 4 5 22 pF 6 7 8 Supply voltage VDD (V) 55 µPD754264 IDD vs VDD (System Clock: 4.19-MHz Crystal Resonator) (TA = 25°C) 10 5.0 PCC = 0011 PCC = 0010 1.0 PCC = 0001 PCC = 0000 System clock HALT mode Supply current IDD (mA) 0.5 0.1 0.05 0.01 0.005 X1 X2 Crystal resonator 4.19 MHz 22 pF 0.001 0 1 2 3 4 Supply voltage VDD (V) 56 5 22 pF 6 7 8 µPD754264 IDD vs VDD (System Clock: 2.0-MHz Crystal Resonator) (TA = 25ºC) 10 5.0 PCC = 0011 PCC = 0010 PCC = 0001 PCC = 0000 System Clock HALT Mode 1.0 Supply Current IDD (mA) 0.5 0.1 0.05 0.01 0.005 X1 X2 Crystal Resonator 2.0 MHz 47 pF 0.001 0 1 2 3 4 5 47 pF 6 7 8 Supply Voltage VDD (V) 57 µPD754264 15. PACKAGE DRAWINGS 20 PIN PLASTIC SOP (300 mil) 20 11 P detail of lead end 1 10 A H J E K F G I C N D M L B M NOTE Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 13.00 MAX. 0.512 MAX. B 0.78 MAX. 0.031 MAX. C 1.27 (T.P.) 0.050 (T.P.) D 0.40 +0.10 –0.05 0.016 +0.004 –0.003 E 0.1±0.1 0.004±0.004 F 1.8 MAX. 0.071 MAX. G 1.55 0.061 H 7.7±0.3 0.303±0.012 I 5.6 0.220 J 1.1 0.043 K 0.20 +0.10 –0.05 0.008 +0.004 –0.002 L 0.6±0.2 0.024 +0.008 –0.009 M 0.12 0.005 N 0.10 0.004 P 3° +7° –3° 3° +7° –3° P20GM-50-300B, C-4 58 µPD754264 16. RECOMMENDED SOLDERING CONDITIONS Solder the µPD754264 under the following recommended conditions. For the details on the recommended soldering conditions, refer to the Information Document Semiconductor Device Mounting Technology Manual (C10535E). For the soldering method and conditions other than those recommended, consult an NEC representative. Table 16-1. Soldering Conditions of Surface Mount Type µPD754264GS-×××-BA5: 20-pin plastic SOP (300 mil, 1.27-mm pitch) Soldering Method Infrared ray reflow Soldering Conditions Package peak temperature: 235°C, Reflow time: 30 seconds max. (210°C min.), Number of reflow process: 2 max. Symbol IR35-107-2 Exposure limit: 7 daysNote (afterward, 10-hour pre-baking at 125°C is required) VPS Package peak temperature: 215°C, Reflow time: 40 seconds max. (200°C min.), Number of reflow process: 2 max. Exposure limit: 7 daysNote (afterward, 10-hour pre-baking at 125°C is required) VP15-107-2 Wave soldering Solder bath temperature: 260°C max., Flow time: 10 seconds max., Number of flow process: 1 Preheating temperature: 120°C max. (package surface temperature) Exposure limit: 7 daysNote (afterward, 10-hour pre-baking at 125°C is required) WS65-107-1 Partial heating Pin temperature: 300°C max., Time: 3 seconds max. (per side of device) – Note Maximum number of days during which the product can be stored at a temperature of 25°C and a relative humidity of 65% or less after dry-pack package is opened. Caution Do not use different soldering methods together (except for partial heating). 59 µPD754264 APPENDIX A. COMPARISON OF FUNCTIONS BETWEEN µPD754264 AND 75F4264 µPD754264 Item Program memory Data memory µPD75F4264 Mask ROM 0000H to 0FFFH (4096 × 8 bits) Static RAM 000H to 07FH (128 × 4 bits) EEPROM 400H to 43FH (32 × 8 bits) Flash memory 0000H to 0FFFH (4096 × 8 bits) CPU 75XL CPU General-purpose register (4 bits × 8 or 8 bits × 4) × 4 banks Instruction execution time • 0.67, 1.33, 2.67, 10.7 µs (@ fX = 6.0-MHz operation) • 0.95, 1.91, 3.81, 15.3 µs (@ fX = 4.19-MHz operation) I/O port 4 (on-chip pull-up resistor can be connected by mask option) CMOS input Note CMOS I/O 9 (on-chip pull-up resistor connection can be specified by means of software) Total 13 System clock oscillator Crystal/ceramic oscillator Start-up time after reset 217/fX, 215/fX, 213/fX (can be selected by mask option) Timer 4 channels • 8-bit timer counter: 3 channels (can be used as 16-bit timer counter) • Basic interval timer/watchdog timer: 1 channel A/D converter • 8-bit resolution × 2 channels (successive approximation, hardware control) • Can be operated from VDD = 1.8 V Programmable threshold port None Vectored interrupt External: 1, internal: 5 Test input External: 1 (key return reset function available) Power supply voltage VDD = 1.8 to 6.0 V Operating ambient temperature TA = –40 to +85°C Package • 20-pin plastic SOP (300 mil, 1.27-mm pitch) Note Under development 60 215/fX 2 channels µPD754264 APPENDIX B DEVELOPMENT TOOLS The following development tools are provided for system development using the µPD754264. In the 75XL Series, the relocatable assembler which is common to the series is used in combination with the device file of each product. Language processor RA75X relocatable assembler Host machine PC-9800 Series IBM PC/ATTM and compatible machines Device file Host machine PC-9800 Series OS Distribution media Part number (product name) MS-DOS™ 3.5-inch 2HD µS5A13RA75X Ver. 3.30 to Ver. 6.2Note 5-inch 2HD µS5A10RA75X 3.5-inch 2HC µS7B13RA75X 5-inch 2HC µS7B10RA75X Refer to the OS for IBM PC OS MS-DOS Ver. 3.30 to Distribution media Part number (product name) 3.5-inch 2HD µS5A13DF754264 5-inch 2HD µS5A10DF754264 3.5-inch 2HC µS7B13DF754264 5-inch 2HC µS7B10DF754264 Ver. 6,2Note IBM PC/AT and compatible machines Refer to the OS for IBM PC Note Ver.5.00 or later have the task swap function, but it cannot be used for this software. Remark Operation of the assembler and device file are guaranteed only on the above host machine and OSs. 61 µPD754264 Debugging tool The in-circuit emulators (IE-75000-R and IE-75001-R) are available as the program debugging tool for the µPD754264. The system configurations are described as follows. Hardware IE-75000-R Note 1 IE-75001-R In-circuit emulator for debugging the hardware and software when developing application systems that use the 75X Series and 75XL Series. When developing the µPD754264, the emulation board IE-75300-R-EM and emulation probe EP-754144GS-R which are sold separately must be used with the IE-75001-R. By connecting the host machine, efficient debugging can be made. IE-75300-R-EM Emulation board for evaluating the application systems that use the µPD754264. It must be used with the IE-75000-R or IE-75001-R. EP-754144GS-R Emulation probe for the µPD754264GS. It must be connected to IE-75000-R (or IE-75001-R) and IE-75300-R-EM. It is supplied with the flexible boards EV-9500GS-20 (supporting 20-pin plastic shrink SOPs) and EV-9501GS-20 (supporting 20-pin plastic SOPs) which facillitate connection to a target system. The µPD754264GS uses only EV-9501GS-20. EV-9501GS-20 Software In-circuit emulator for debugging the hardware and software when developing application systems that use the 75X Series and 75XL Series. When developing the µPD754264, the emulation board IE-75300-R-EM and emulation probe EP-754144GS-R that are sold separately must be used with the IE-75000-R. By connecting with the host machine, efficient debugging can be made. It contains the emulation board IE-75000-R-EM which is connected. IE control program Connects the IE-75000-R or IE-75001-R to a host machine via RS-232-C and Centronix I/ F and controls the above hardware on a host machine. Host machine PC-9800 Series OS MS-DOS Ver. 3.30 to Ver. 6.2Note 2 IBM PC/AT and its compatible machine Refer to the OS for IBM PC Part number (product name) Distribution media 3.5-inch 2HD µS5A13IE75X 5-inch 2HD µS5A10IE75X 3.5-inch 2HC µS7B13IE75X 5-inch 2HC µS7B10IE75X Notes 1. Maintenance parts 2. Ver.5.00 or later have the task swap function, but it cannot be used for this software. Remark Operation of the IE control program is guaranteed only on the above host machines and OSs. 62 µPD754264 OS for IBM PC The following IBM PC OSs are supported. OS Version PC DOS™ Ver. 5.02 to Ver. 6.3 J6.1/VNote to J6.3/VNote MS-DOS Ver. 5.0 to Ver. 6.22 5.0/VNote to J6.2/VNote IBM DOS™ J5.02/VNote Note Supported only English mode. Caution Ver. 5.0 or later have the task swap function, but it cannot be used for operating systems above. 63 µPD754264 APPENDIX C. RELATED DOCUMENTS The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Device related documents Document Number Document Name Japanese English µPD754264 Data Sheet U12487J This document µPD754264 User’s Manual U12287J U12287E 75XL Series Selection Guide U10453J U10453E Development tool related documents Document Number Document Name Hardware Japanese IE-75000-R/IE-75001-R User's Manual EEU-846 EEU-1416 IE-75300-R-EM User's Manual U11354J U11354E EP-754144GS-R User's Manual Software English RA75X Assembler Package User's Manual U10695J U10695E Operation EEU-731 EEU-1346 Language EEU-730 EEU-1363 Other related documents Document Name IC Package Manual Document Number Japanese English C10943X Semiconductor Device Mounting Technology Manual C10535J C10535E Quality Grades on NEC Semiconductor Devices C11531J C11531E NEC Semiconductor Device Reliability/Quality Control System C10983J C10983E Static Electricity Discharge (ESD) Test MEM-539 Guide to Quality Assurance for Semiconductor Devices C11893J Microcomputer Related Product Guide - Other Manufacturers U11416J Caution 64 – MEI-1202 – These documents are subject to change without notice. Be sure to read the latest documents. µPD754264 [MEMO] 65 µPD754264 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 66 µPD754264 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860 United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583 NEC Electronics Italiana s.r.l. NEC Electronics (Germany) GmbH Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 NEC Electronics (France) S.A. NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (UK) Ltd. NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829 J98. 11 67 µPD754264 The µPD754244 is manufactured and sold based on a licence contract with CP8 Transac regarding the EEPROM microcomputer patent. This product cannot be used for an IC card (SMART CARD). EEPROM is a trademark of NEC Corporation. MS-DOS is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5 68