NEC UPD78323LP

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD78323,78324
16/8-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The µPD78324 is a 16/8-bit single-chip microcontroller that incorporates a high-performance 16-bit CPU. The µPD78324
is one of 78K/III series. The internal capacity is significantly increased compared with the conventional µPD78322.
A realtime pulse unit for realtime pulse control required in motor control, an A/D converter, a ROM, and a RAM have been
integrated into one chip.
The µPD78324 incorporates 32K-byte mask ROM and 1024-byte RAM.
The µPD78323 is a ROM-less version of the µPD78324. Also, It is provided the µPD78P324 as an on-chip PROM
product.
Detailed information about product features and specifications can be found in the following document.
µPD78322 User’s Manual : IEU-1248
FEATURES
• Internal 16-bit architecture and external 8-bit data bus
• High-speed processing by pipeline control and instruction prefetch
• Minimum instruction execution time: 250 ns (with 16 MHz external clock in operation)
• Instruction set suitable for control operations (µPD78312 upward compatible)
• Multiply/divide instructions (16 bits × 16 bits, 32 bits ÷ 16 bits)
• Bit manipulation instruction
• String instruction, etc.
• On-chip high-function interrupt controller
• 3-level priority specifiable
• 3-type interrupt processing mode selectable
(Vectored interrupt function, context switching function, and macro service function)
• Variety of peripheral hardware
• Realtime pulse unit
• 8-channel, 10-bit A/D converter
• Watchdog timer
• Powerful serial interface (with an on-chip dedicated baud rate generator)
• UART
• SBI (NEC Standard Serial Bus Interface)
····· 1 channel
····· 1 channel
• 3-wire serial I/O
APPLICATIONS
• Motor control devices
Unless there are any particular diferences, the µPD78324 is described as the representative model in this document.
The information in this document is subject to change without notice.
Document No. U10456EJ4V0DS00 (4th edition)
(Previous No. IC-2870)
Date Published November 1995 P
Printed in Japan
The mark
shows major revised points.
©
1991
µPD78323, 78324
ORDERING INFORMATION
Part Number
µPD78323GJ-5BJ
µPD78323LP
µPD78324GJ-× × ×-5BJ
µPD78324LP-× × ×
Package
74-pin
68-pin
74-pin
68-pin
plastic
plastic
plastic
plastic
Remark × × × Indicates ROM code number.
2
QFP (20 × 20 mm)
QFJ ( 950 mil)
QFP (20 × 20 mm)
QFJ ( 950 mil)
On-chip ROM
None
None
Mask ROM
Mask ROM
µPD78323, 78324
PIN CONFIGURATION
NC
P01/RTP1
P02/RTP2
P03/RTP3
P04/RTP4
P05/RTP5
P06/RTP6
P07/RTP7
EA
V SS
P93/TMD
P92/TAS
P91/WR
P90/RD
ASTB
P40/AD0
P41/AD1
P42/AD2
• 74-pin plastic QFP (20 × 20 mm)
µPD78323GJ-5BJ
µPD78324GJ-×××-5BJ
74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57
56
P00/RTP0
P43/AD3
1
55
WDTO
P44/AD4
2
54
V SS
P45/AD5
3
53
NC
P46/AD6
4
52
X1
P47/AD7
5
51
X2
P50/A8
6
50
RESET
P51/A9
7
49
P85/TO11
P52/A10
8
48
P84/TO10
P53/A11
9
47
P83/TO03
P54/A12
10
46
P82/TO02
P55/A13
11
45
P81/TO01
NC
12
44
P80/TO00
P56/A14
13
43
NC
P57/A15
14
42
P34/SCK
V DD
15
41
P33/SI/SB1
AV SS
16
40
P32/SO/SB0
P70/AN0
17
39
P31/R X D
P71/AN1
18
38
P30/T X D
NC
P27/INTP6/TI
P26/INTP5
P25/INTP4
P24/INTP3
P23/INTP2
P22/INTP1
P21/INTP0
P20/NMI
V DD
AV DD
AV REF
P77/AN7
P76/AN6
P75/AN5
P74/AN4
P73/AN3
NC
P72/AN2
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
Caution The NC pin should be connected to VSS for noise control (can also be left open).
3
µPD78323, 78324
2
1 68 67 66 65 64 63 62 61
P72/AN2
V SS
3
P73/AN3
P20/NMI
4
P74/AN4
P21/INTP0
5
P75/AN5
P22/INTP1
6
P76/AN6
P23/INTP2
7
P77/AN7
P24/INTP3
8
AV REF
P25/INTP4
9
AV DD
P26/INTP5
950 mil)
P27/INTP6/TI
• 68-pin plastic QFJ (
µPD78323LP
µPD78324LP-×××
P30/T X D
10
60
P71/AN1
P31/R X D
11
59
P70/AN0
P32/SO/SB0
12
58
AV SS
P33/SI/SB1
13
57
V DD
P34/SCK
14
56
P57/A15
P80/TO00
15
55
P56/A14
16
54
P55/A13
P82/TO02
17
53
P54/A12
P83/TO03
18
52
P53/A11
P84/TO10
19
51
P52/A10
P85/TO11
20
50
P51/A9
RESET
21
49
P50/A8
X2
22
48
P47/AD7
X1
23
47
P46/AD6
V SS
24
46
P45/AD5
WDTO
25
45
P44/AD4
26
44
P43/AD3
P81/TO01
RTP0/P00
4
P42/AD2
P41/AD1
P40/AD0
ASTB
P90/RD
P91/WR
P92/TAS
P93/TMD
V SS
EA
RTP7/P07
RTP6/P06
RTP5/P05
RTP4/P04
RTP3/P03
RTP2/P02
RTP1/P01
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
µPD78323, 78324
P00 to P07
P20 to P27
P30 to P34
P40 to P47
P50 to P57
P70 to P77
P80 to P85
P90 to P93
NMI
INTP0 to INTP6
RTP0 to RTP7
TI
T XD
R XD
SB0/SO
SB1/SI
SCK
TO00 to TO03
TO10 to TO11
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
Port0
Port2
Port3
Port4
Port5
Port7
Port8
Port9
Nonmaskable Interrupt
Interrupt From Peripherals
Realtime Port
Timer Input
Transmit Data
Receive Data
Serial Bus/Serial Output
Serial Bus/Serial Input
Serial Clock
Timer Output
RESET
X1, X2
WDTO
EA
TMD
TAS
WR
RD
ASTB
AD0 to AD7
A8 to A15
AN0 to AN7
AVREF
AVSS
AVDD
VDD
VSS
NC
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
Reset
Crystal
Watchdog Timer Output
External Access
Turbo Mode
Turbo Access Strobe
Write Strobe
Read Strobe
Address Strobe
Address/Data Bus
Address Bus
Analog Input
Analog Reference Voltage
Analog VSS
Analog VDD
Power Supply
Ground
Non-connection
5
µPD78323, 78324
GENERAL DESCRIPTION OF FUNCTIONS
Basic instructions
111
Minimum instruction
execution time
250 ns (with 16 MHz external clock in operation)
Internal memory
• ROM : 32K bytes (µPD78324)
None (µPD78323)
• RAM : 1K bytes
Memory space
64K bytes
General registers
8 bits × 16 × 8 banks (memory mapping)
I/O line
• Input port
: 16 (dual-function as analog input: 8)
• Input/output port : 39 (µPD78324)
21 (µPD78323)
Real-time pulse unit
•
•
•
•
•
•
Serial communication
interface
Serial interface with a dedicated baud rate generator
• UART
: 1 channel
• SBI (NEC Serial Bus Interface) : 1 channel
A/D converter
10-bit resolution (8 analog inputs)
Interrupt
• External : 8, internal : 14 (dual-function as external : 2)
• 3 processing modes
(vectored interrupt function, context switching function, and macro service function)
Test factor
Internal : 1
Standby
STOP mode/HALT mode
Instruction set
16-bit transfer/operation instruction, multiplication/division instruction (16 × 16, 32 ÷ 16), bit manipulation instruction, string instruction, etc.
Others
On-chip watchdog timer
Package
6
18/16-bit free running timer × 1
16-bit timer/event counter × 1
16-bit compare register × 6
18-bit capture register × 4
18-bit capture/compare register × 2
Realtime output port × 8
• 68-pin plastic QFJ (
950 mil)
• 74-pin plastic QFP (20 × 20 mm)
µPD78323, 78324
DIFFERENCES BETWEEN µPD78324 AND 78323
Product Name
µPD78324
Item
Internal ROM
32K bytes
Input
I/O line
µPD78323
None
16 (dual-function as analog input: 8)
Input
/output
39
21
Port 4
(P40 to P47)
Specifiable as I/O as an 8-bit unit.
Functions as multiplexed address/data buses
(AD0 to AD7) in the external memory expansion
mode.
Functions always as multiplexed address/data
buses.
Port 5
(P50 to P57)
Specifiable as I/O bit-wise.
Functions as address bus (A8 to A15) in the
external memory expansion mode.
Functions always as address bus.
Port 9
(P90 to P93)
Specifiable as I/O bit-wise.
In the external memory expansion mode, P90
and P91 function as RD strobe signal output
and WR strobe signal output, respectively. In
the external memory high-speed fetch mode,
P92 P93 function as TAS output and TMD output respectively.
Always P90 and P91 function as RD strobe and
WR strobe signal output, respectively.
Memory expansion
mode register (MM)
Port 4 I/O mode is set as an 8-bit unit .
Port 5 mode register
(PM5)
Port 5 I/O mode is set bit-wise.
In the µPD78324 emulation mode, turbo acces
acces manager (µPD71P301)Note PA and PB pins
are controlled as port 4 and port 5 emulation
pins.
Note Maintenance product
7
ROM/RAM
BLOCK DIAGRAM
8
EXU
BCU
Main RAM
X1
(P20) NMI
INTP0–INTP5
(P21–P26)
(P80) TO00
(P81) TO01
(P82) TO02
(P83) TO03
(P84) TO10
(P85) TO11
(P27) TI/INTP6
PROGRAMMABLE
INTERRUPT
CONTROLLER
X2
GENERAL
REGISTERS
128 bytes
&
DATA
MEMORY
128 bytes
RESET
ASTB
ALU
SYSTEM
CONTROL
&
BUS
CONTROL
&
PREFETCH
CONTROL
Note
ROM
32K
bytes
Peripheral
RAM
768
bytes
RD (P90)
WR (P91)
TAS (P92)
TMD (P93)
MICRO SEQUENCE
CONTROL
TIMER/COUNTER UNIT
(REALTIME PULSE UNIT)
EA
A8–A15 (P50–P57)
MICRO ROM.
AD0–AD7 (P40–P47)
(P34) SCK
(P32) SO/SB0
(P33) SI/SB1
SERIAL INTERFACE
(SBI)
(UART)
A/D CONVERTER
(10 BIT)
VDD
VSS
PORT
WDT
(P30) TXD
(P31) RXD
µPD78323, 78324
P00–P07 (REALTIME PORT)
P20–P27
P30–P34
P40–P47
P50–P57
P70–P77
P80–P85
P90–P93
WDTO
AVREF
AVSS
AVDD
AN0–AN7
(P70–P77)
Note The µPD78323 does not incorporate ROM.
µPD78323, 78324
CONTENTS
1.
2.
LIST OF PIN FUNCTIONS ..................................................................................................................... 11
1.1
PORT PINS ...................................................................................................................................................... 11
1.2
PINS OTHER THAN PORTS .......................................................................................................................... 12
1.3
PIN INPUT/OUTPUT CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS ................... 14
CPU ARCHITECTURE ............................................................................................................................ 16
2.1
2.2
2.3
3.
MEMORY SPACE ............................................................................................................................................ 16
PROCESSOR REGISTERS ............................................................................................................................ 19
2.2.1
Control Registers ........................................................................................................................... 20
2.2.2
General Registers ........................................................................................................................... 22
2.2.3
Special Function Registers (SFR) ................................................................................................ 24
DATA MEMORY ADDRESSING ..................................................................................................................... 29
2.3.1
General Register Addressing ....................................................................................................... 29
2.3.2
Short Direct Addressing ................................................................................................................ 29
2.3.3
Special Function Register (SFR) Addressing ............................................................................ 29
BLOCK FUNCTIONS .............................................................................................................................. 30
3.1
BUS CONTROL UNIT (BCU) .......................................................................................................................... 30
3.2
EXECUTION UNIT (EXU) ................................................................................................................................ 30
3.3
ROM/RAM ........................................................................................................................................................ 30
3.4
INTERRUPT CONTROLLER .......................................................................................................................... 30
3.5
PORT FUNCTIONS ......................................................................................................................................... 31
3.6
CLOCK GENERATOR .................................................................................................................................... 32
3.7
REALTIME PULSE UNIT (RPU) ..................................................................................................................... 34
3.7.1
Configuration .................................................................................................................................. 34
3.7.2
Realtime Output Function ............................................................................................................. 36
3.8
A/D CONVERTER ........................................................................................................................................... 37
3.9
SERIAL INTERFACE ...................................................................................................................................... 37
3.10 WATCHDOG TIMER ....................................................................................................................................... 40
4.
INTERRUPT FUNCTIONS ...................................................................................................................... 41
4.1
OVERVIEW ...................................................................................................................................................... 41
4.2
MACRO SERVICE ........................................................................................................................................... 42
4.3
CONTEXT SWITCHING FUNCTION .............................................................................................................. 44
4.3.1
Context Switching Function at Interrupt Request ..................................................................... 44
4.3.2
Context Switching Function by BRKCS Instruction ................................................................. 45
5.
STANDBY FUNCTIONS ......................................................................................................................... 46
6.
EXTERNAL DEVICE EXPANSION FUNCTION .................................................................................... 47
7.
OPERATION AFTER RESET ................................................................................................................. 48
8.
INSTRUCTION SET ................................................................................................................................ 49
9.
ELECTRICAL SPECIFICATIONS .......................................................................................................... 63
9
µPD78323, 78324
10. PACKAGE DRAWINGS .......................................................................................................................... 74
11. RECOMMENDED SOLDERING CONDITIONS ..................................................................................... 76
APPENDIX A. LIST OF 78K/III SERIES PRODUCTS ................................................................................ 77
APPENDIX B. TOOLS .................................................................................................................................... 79
B.1
DEVELOPMENT TOOLS ................................................................................................................................ 79
B.2
EVALUATION TOOLS .................................................................................................................................... 83
B.3 EMBEDDED SOFTWARE ................................................................................................................................ 83
10
µPD78323, 78324
1. LIST OF PIN FUNCTIONS
1.1
PORT PINS
Pin Name
P00 to P07
I/O
Input/
output
Function
Port 0
8-bit input/output port
Input/output can be specified bit-wise
Also serves as a realtime output port.
DualFunction Pin
RTP0 to
RTP7
P20
NMI
P21
INTP0
P22
INTP1
P23
P24
Input
Port 2
Dedicated port for 8-bit input
INTP2
INTP3
P25
INTP4
P26
INTP5
P27
INTP6/TI
P30
T XD
P31
P32
Input/
output
Port 3
5-bit input/output port
Input/output can be specified bit-wise
P33
SCK
P40 to P47
Input/
output
Port 4
8-bit input/output port
Input/output can be specified in 8-bit unit.
P50 to P57
Input/
output
Port 5
8-bit input/output port
Input/output can be specified bit-wise
P70 to P77
Input
Port 7
Dedicated port for 8-bit input
AD0 to AD7
A8 to A15
AN0 to AN7
TO00
P80
TO01
P81
P83
SO/SB0
SI/SB1
P34
P82
R XD
Input/
output
Port 8
6-bit input/output port
Input/output can be specified bit-wise
TO02
TO03
P84
TO10
P85
TO11
RD
P90
P91
P92
P93
Input/
output
Port 9
4-bit input/output port
Input/output can be specified bit-wise
WR
TAS
TMD
11
µPD78323, 78324
1.2
PINS OTHER THAN PORTS (1/2)
Pin Name
I/O
RTP0 to RTP7 Output
NMI
Input
Function
Realtime output port which generates pulses in synchronization with the trigger signal
transmitted from the realtime pulse unit (RPU).
Nonmaskable interrupot request input capable of specifying the effective at the rising or
falling edge by a mode register.
DualFunction Pin
P00 to P07
P20
INTP0
P21
INTP1
P22
P23
INTP2
INTP3
Input
External interrupt request input capable of specifying the effective edgy by a mode
register.
P24
INTP4
P25
INTP5
P26
INTP6
P27/TI
Input
External count clock input to timer 1 (TM1)
T XD
Output
Serial data output of asynchronous serial interface (UART)
P30
R XD
Input
Serial data input of asynchronous serial interface (UART)
P31
SO
Output
Serial data output of clock synchronous serial interface in 3-wire mode
P32/SB0
SI
Input
Serial data input of clock synchronous serial interface in 3-wire mode
P33/SB1
Input
/output
Serial data output of clock synchronous serial interface in SBI mode
SCK
Input
/output
Serial clock input/output of clock synchronous serial interface
P34
AD0 to AD7
Input
/output
Multiplexed address/data bus for external memory expansion
P40 to P47
A8 to A15
Output
Address bus for external memory expansion
P50 to P57
TI
SB0
SB1
P27/INTP6
P32/SO
P33/SI
TO00
P80
TO01
P81
P82
TO02
Output
TO03
Pulse output from the realtime pulse unit
P83
TO10
P84
TO11
P85
RD
WR
Strobe signal output generated for external memory read operation
P90
Strobe signal output generated for external memory write operation
P91
Output
TAS
Control signal output generated for access to turbo access manager µPD71P301Note
TMD
P93
WDTO
Output
Signal output indicating that the watchdog timer has generated a nonmascable
interrupt.
––
ASTB
Output
Timing signal output generated for externally latching the address information output from
pins AD0 to AD7 in order to access the external memory.
––
Note Maintenance product
12
P92
µPD78323, 78324
1.2
PINS OTHER THAN PORTS (2/2)
DualFunction Pin
Pin Name
I/O
Function
EA
Input
In the µPD78324, EA pin is normally connected to VDD. Connecting EA pin to VSS sets
the ROM-less mode and accesses the external memory. In the µPD78323, this pin should
be fixed to “0” (low level). The EA pin level cannot be changed during operation.
AN0 to AN7
Input
A/D converter analog input.
—
AVREF
Input
A/D converter reference voltage input.
—
AVDD
—
A/D converter analog power supply
—
AVSS
—
A/D converter GND
—
RESET
Input
System reset input
—
X1
Input
Crystal connect pin for sysem clock oscillation. When an external clock is supplied,
the clock is input to X1 and the inverted clock is input to X2. (X2 can also be left
—
X2
—
open.)
—
VDD
––
Positive power supply
—
VSS
—
GND pin
—
NC
—
Not internally connected. Connected to VSS (GND) (can also be left open).
—
—
13
µPD78323, 78324
1.3 PIN INPUT/OUTPUT CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS
The pin input/output circuits, partly simplified, are shown in Table 1-1 and Figure 1-1.
Table 1-1. I/O Circuit Types of Pins and Their Recommended
Connection Methods when Unused
Input/Output
Circuit Type
Recommended Connection Method
P00/RTP0 to P07/RTP7
5
Input mode : Individually connected to VDD or VSS via resistor
Output mode: Leave open
P20/NMI
P21/INTP0 to P26/INTP5
P27/INTP6/TI
2
Connected to VSS
P30/TXD
P31/RXD
5
P32/SO/SB0
P33/SI/SB1
P34/SCK
8
P40/AD0 to P47/AD7
P50/A8 to P57/A15
5
P70/AN0 to P77/AN7
9
P80/TO00 to P83/TO03
P84/TO10, P85/TO11
5
Pin
14
Input mode : Individually connected to VDD or VSS via resistor
Output mode: Leave open
Connected to VSS
Input mode : Individually connected to VDD or VSS via resistor
Output mode: Leave open
P90/RD
P91/WR
P92/TAS
P93/TMD
5
WDTO
3
ASTB
4
EA
1
––
RESET
2
––
AVREF, AVSS
––
Connected to VSS
AVDD
––
Connected to VDD
NC
––
Connected to VSS (can also be left open)
Leav open
µPD78323, 78324
Figure 1-1. Pin Input/Output Circuits
Type 5
Type 1
VDD
VDD
data
P-ch
IN/OUT
P-ch
IN
output
disable
N-ch
N-ch
input
enable
Type 8
Type 2
VDD
data
P-ch
IN/OUT
IN
output
disable
N-ch
Schmitt-trigger input having hysteresis characteristics.
Type 9
Type 3
VDD
Comparator
IN
P-ch
P-ch
N-ch
+
–
OUT
VREF
(Threshold Voltage)
N-ch
input
enable
Type 4
VDD
data
output
disable
P-ch
OUT
N-ch
Push-pull output which can become high-impedance
output (with both P-ch and N-ch set to off)
15
µPD78323, 78324
2. CPU ARCHITECTURE
2.1 MEMORY SPACE
In the µPD78324 a maximum of 64K bytes of memory can be addressed (see Figure 2-1).
Program fetches can be performed within the area from 0000H to FDFFH. However, when external memory expansion
is implemented in the area from FE00H to FFFFH (main RAM and special function register area), program fetches can also
be performed on this area. In this case, a program fetch is performed on the external memory, not on the main RAM or special
function registers.
(1)
Vector table area
Interrupt request from the peripheral hardware, reset input, external interrupt request and interrupt branch address by
break instruction are stored in the 0000H to 003FH 64-byte area. Generation of an interrupt request sets the even address
content of each table in the lower 8 bits of the program counter (PC) and the odd address content in the higher 8 bits.
Interrupt Source
RESET
NMI
WDT
TMF0
EXF0
EXF1
EXF2
EXF3
EXF4/CCFX0
EXF5/CCFX1
EXF6/TI
CMF00
CMF01
CMF02
CMF03
CMF10
CMF11
SRF
STF
CSIIF
ADF
Operation code
BRK
Vector Table Address
(RESET pin input) ...........................................
(NMI pin input) ................................................
(Watchdog timer) ............................................
(Realtime pulse unit) .......................................
(INTP0 pin input) .............................................
(INTP1 pin input) .............................................
(INTP2 pin input) .............................................
(INTP3 pin input) .............................................
(INTP4 pin input/realtime pulse unit) .............
(INTP5 pin input/realtime pulse unit) .............
(INTP6/TI pin input) ........................................
(Realtime pulse unit) .......................................
(Realtime pulse unit) .......................................
(Realtime pulse unit) .......................................
(Realtime pulse unit) .......................................
(Realtime pulse unit) .......................................
(Realtime pulse unit) .......................................
(Serial receive complete) ................................
(Serial send complete) ....................................
(Clock synchronous serial interface) ..............
(A/D converter) ................................................
trap ...................................................................
(Break instruction) ...........................................
0000H
0002H
0004H
0006H
0008H
000AH
000CH
000EH
0010H
0012H
0014H
0016H
0018H
001AH
001CH
001EH
0020H
0024H
0026H
0028H
002AH
003CH
003EH
If bit 1 (TPF) of CPU control word (CCW) is set to 1, the 8002H to 803FH external memory area is used as an interrupt
vector table in place of 0002H to 003FH.
16
µPD78323, 78324
(2) CALLT table area
32 tables of call addresses of 1-byte call instruction (CALLT) can be stored in the 0040H to 007FH 64-byte area.
If bit 1 (TPF) of CPU control word (CCW) is set to 1, the 8040H to 807FH external memory area is used as a CALLT
instruction table in place of 0040H to 007FH.
(3) CALLF entry area
The 0800H to 0FFFH area can be directly subroutine-called by 2-byte call instruction (CALLF).
(4) On-chip RAM area
A 1024-byte RAM is built in FB00H to FEFFH. This area is composed of the following 2 RAMs.
• Peripheral RAM : FB00H to FDFFH (768 bytes)
• Main RAM
: FE00H to FEFFH (256 bytes)
The main RAM can be accessed at high speed.
In the main RAM area, the macro service control word and general register group composed of 8 register banks are
mapped onto the 36 bytes from FE06H to FE2BH and the 128 bytes from FE80H to FEFFH, respectively.
(5) Special function register (SFR) area
Registers having specially assigned functions, such as on-chip peripheral hardware mode registers and control registers,
are mapped in the FF00H to FFFFH area. Addresses without mapped registers cannot be accessed.
(6) External memory area
The µPD78324 can add external memories (ROM, RAM) to the 32K-byte (8000H to FFFFH) area.
The µPD78323 can connect external memories (ROM, RAM) to the 64K-byte (0000H to FFFFH) area.
Each external memory can be accessed using P40/AD0 to P47/AD7 (multiplexed address/data bus), P50/A8 to P57/A15
(address bus) and RD, WR and ASTB signals.
The external access area is mapped in the FFD0H to FFDFH 16-byte area of the special function register (SFR). In this
way, the external memory can be accessed by SFR addressing.
Dedicated pins (TAS and TMD pins) are provided to connect turbo access manager (µPD71P301)Note. If the µPD71P301
is used, the program processing speed equal to that of the on-chip ROM can be obtained.
Note Maintenance product
17
18
Figure 2-1. Memory Map
EA = L
• µPD78323
• µPD78324 ROM-Less Mode
EA = H
( µ PD78324)
FFFFH
FF00H
FEFFH
Special Function Register
(SFR)
(256 × 8)
FEFFH
FE80H
Main RAM
(256 × 8)
FE00H
Data Memory FDFFH
FE2BH
FE06H
Peripheral RAM
(768 × 8)
Data Area
(1024 × 8)
7FFFH
External MemoryNote
(31488 × 8)
Program Area
1000H
0FFFH
0800H
07FFH
8000H
7FFFH
Program Memory
Data Memory
Macro Service Control
(36 × 8)
FB00H
FB00H
FAFFH
Memory Space
(64K × 8)
Program Memory
Data Memory
General Register
(128 × 8)
External Memory
(64256 × 8)
CALLF Instruction Entry Area
(2048 × 8)
Program Area
0080H
007FH
Internal ROM
(32768 × 8)
CALLF Instruction Table Area
(64 × 8)
0FFFH
0040H
003FH
0000H
0000H
0000H
Note Accessed in external memory expansion mode.
Caution For word access (including stack operations) to the main RAM area (FE00H-FEFFH), the address that
specifies the operand must be an even value.
µPD78323, 78324
Vector Table Area
(64 × 8)
µPD78323, 78324
2.2 PROCESSOR REGISTERS
The processor registers consist mainly of three groups. They are general registers consisting of 8 banks of sixteen 8bit registers, control registers consisting of one 8-bit register and three 16-bit registers, and special function registers such
as peripheral hardware I/O mode registers.
Figure 2-2. Register Configuration
Control Registers
15
0
P C
PSW
S P
7
0
CCW
General Registers
7
0
7
0
R 1
R 0
R 3
R 2
R 5
R 4
R 7
R 6
R 9
R 8
R 11
R 10
R 13
R 12
R 15
R 14
Special Function Registers
0 7
7
0
SFR 255
SFR 254
SFR 253
SFR 252
SFR 251
SFR 250
SFR 249
SFR 248
SFR 1
SFR 0
Remark The CCWs of the control registers are mapped in the special function register (SFR) area.
19
µPD78323, 78324
2.2.1 Control Register
The control registers carry out dedicated functions such as control of the program sequence, status and stack memory,
and modification of operand addressing. They consist of three 16-bit registers and one 8-bit register.
(1) Program counter (PC)
This is a 16-bit register which holds the address information of the next program to be executed. It is normally incremented
according to the number of bytes of the instruction to be fetched. If an instruction with data branch is executed, immediate
data and the register content are set. RESET input sets and branches the data of 0000H and 0001H reset vector tables
in the PC.
(2) Program status word (PSW)
This is a 16-bit register consisting of various flags which are set or reset by the result of instruction execution. Read/
write access is carried out in units of the higher 8 bits (PSWH) or lower 8 bits (PSWL). Each flag can be operated using
the bit operation instruction. If an interrupt request is made or BRK instruction is executed, data is automatically saved in
the stack and is recovered by RETI or RETB instruction.
All bits are reset to 0 by RESET input.
Figure 2-3. PSW Format
(a) Interrupt priority level transition flag (LT)
7
PSWH
PSWL
UF
6
5
4
RBS2 RBS1 RBS0
3
2
1
0
0
0
0
0
7
6
5
4
3
2
1
0
S
Z
RSS
AC
IE
P/V
LT
CY
This flag is used to control the interrupt priority. For normal operation of the interrupt control circuit, this bit must
not be operated by a program.
(b) Carry flag (CY)
If a carry is generated out of bit 7 or 15 as a result of the execution of an operation instruction or a borrow is generated
into bit 7 or 15, this flag is set to 1. In all other cases, this flag is reset to 0. This flag can be tested by the conditional
branch instruction.
When a bit control instruction is executed, this flag functions as a bit accumulator.
(c) Zero flag (Z)
When the operation result is zero, this flag is set to 1. In all other cases, this flag is reset to 0. This flag can be tested
by the conditional branch instruction.
(d) Sign flag (S)
When MSB of the operation result is “1”, this flag is set to 1. When the MSB is “0”, this flag is reset to 0. This flag
can be tested by the conditional branch instruction.
(e) Parity/overflow flag (P/V)
Only when an overflow or underflow occurs as two’s complement during execution of an arithmetic operation
instruction, this flag is set to 1. In all other cases, it is reset to 0 (overflow flag operation).
If the bit number of the operation result set to 1 is even during execution of an logic operation instruction, this flag
is set to 1. If the bit number is odd, this flag is reset to 0 (parity flag operation).
This flag can be tested by the conditional branch instruction.
20
µPD78323, 78324
(f)
Auxiliary carry flag (AC)
If a carry is generated out of bit 3 as a result of operation or a borrow is generated into bit 3, this flag is set to 1.
In all other cases, this flag is reset to 0. This flag can be tested by the conditional branch instruction.
(g) Register set select flag (RSS)
This flag is used to specify general registers X, A, C and B. As shown in Table 2-1, the RSS value determines the
relationship between the functional register and the absolute register.
Thus, another register set (X, A, C, B) can be used by switching the RSS flag.
(h) Interrupt request enable flag (IE)
This flag is used to indicate interrupt request enable/disable. This flag is set to 1 by execution of EI instruction and
is reset to 0 byexecution of DI instruction or acceptance of an interrupt.
(i)
Register bank select flag (RBS0 to RBS2)
This is a 3-bit flag to select one of eight register banks (RBANK0 to RBANK7).
(j)
User flag (UF)
This flag is set or reset in the user program and can be used for program control.
(3) Stack pointer (SP)
This is a 16-bit register which holds the first address of the stack area (LIFO format) of the memory.
It is operated by a dedicated instruction.
SP is decremented before write (save) operation into the stack memory and is incremented after read (return) operation
from the stack memory.
Since SP becomes indeterminate by RESET input, it must be set before subroutine call.
21
µPD78323, 78324
(4) CPU control word (CCW)
This is an 8-bit register consisting of CPU control related flags. It is mapped in the special function register area and can
be controlled by the software.
All bits are reset to 0 by RESET input.
Figure 2-4. CCW Format
7
6
5
4
3
2
1
0
0
0
0
0
0
0
TPF
0
CCW
• Table position flag (TPF)
This flag is used to specify the interrupt vector table area and the memory area used as CALLT instruction table area.
As TPF has been reset to 0 after application of RESET input, the 0000H to 007FH address is used as each table area.
The 8002H to 807FH address of the external memory area in place of 0002H to 007FH address can be used as each table
area by setting TPF to 1 using the software. The vector tables of the BRK instruction, operation code trap interrupt and reset
input are fixed to 003EH, 003CH and 0000H, respectively, and they are not affected by TPF.
2.2.2 General Registers
These are 128-byte registers mapped in the special area (FE80H to FEFFH) of the internal RAM space. They consist
of eight register banks. The general register in the bank consists of sixteen 8-bit registers.
Figure 2-5. General Register Memory Location
16-Bit Processing
8-Bit Processing
FEFFH
FE80H
RBNK0
R15
R14
(FH)
RP7
(EH)
RBNK1
R13
R12
(DH)
RP6
(CH)
RBNK2
R11
R10
(BH)
RP5
(AH)
RBNK3
R9
R8
(9H)
RP4
(8H)
RBNK4
R7
R6
(7H)
RP3
(6H)
RBNK5
R5
R4
(5H)
RP2
(4H)
RBNK6
R3
R2
(3H)
RP1
(2H)
RBNK7
R1
R0
(1H)
RP0
(0H)
7
22
0 7
0
15
0
µPD78323, 78324
The sixteen 8-bit registers can function as eight 16-bit register pairs (RP0 to RP7) as well.
As shown in Table 2-1, the sixteen 8-bit registers are characterized by functional names. The X register functions as
the lower half of the 16-bit accumulator, the A register functions as the upper half of the 8-bit or 16-bit accumulator, the B
and C registers function as a counter, and DE, HL, VP and UP function as address register pairs. In particular the VP register
is function as a base register and the UP register is as a user stack pointer.
The unique function register charges as shown in Table 2-1 according to the value of the register set select flag (RSS)
in the PSW. Thus, if the program is described by the functional name, another register set of X, A, C and B can be used
by means of the RSS flag.
The µPD78324 can carry out processed data addressing operations, implied addressing by functional names with
importance attached to the unique function of each register and register addressing by absolute names with a view to fast
processing with a small number of data transfers or creating highly descriptive programs.
Table 2-1. General Register Configuration
Absolute
Name
R0
Functional Name
RSS = 0
RSS = 1
Absolute
Name
Functional Name
RSS = 0
RSS = 1
X
RP0
AX
R1
A
RP1
BC
R2
C
RP2
AX
R3
B
RP3
BC
R4
X
RP4
VP
VP
R5
A
RP5
UP
UP
R6
C
RP6
DE
DE
R7
B
RP7
HL
HL
R8
VPL
VPL
R9
VPH
VPH
R10
UPL
UPL
R11
UPH
UPH
R12
E
E
R13
D
D
R14
L
L
R15
H
H
23
µPD78323, 78324
2.2.3 Special Function Registers (SFR)
These registers are provided with special functions. They include various peripheral hardware mode registers and control
registers (CCW).
The special function registers are assigned in the FF00H to FFFFH 256-byte space. Short direct memory addressing
is applied to the FF00H to FF1FH 32-byte area for processing with a short word length.
The bit manipulation, arithmetic and transfer instructions can be executed in all areas. The FFD0H to FFDFH 16-byte
area is externally accessible by SFR addressing. Thus, the external memory can be accessed and the external device bit
manipulation can be carried out by an instruction having a short word length.
Table 2-2 lists the special function registers (SFR). The items in the table have the following meanings.
• Symbol................. Indicates the address of the built-in special function register.
Can be described in the instruction operand column.
• R/W.......................Indicates if the corresponding special function register can read or write.
R/W : Read/write enable
R : Read only enable (register bit test enable)
W
• Manipulable bit unit
: Write only enable
....................... Indicates the applicable operation bit unit for the corresponding special function
register.
16-bit manipulable SFR can be described in operand sfrp. When specified by an
address, an even address is described.
1-bit manipulable SFR can be described by the bit operation instruction.
• On reset ............... Indicates the state of each register when RESET is input.
Cautions 1. Addresses for which no special function registers have been assigned cannot be accessed in the
FF00H to FFFFH area.
2. Do not write to the read only register. If data is written, the internal circuit may malfunction.
24
µPD78323, 78324
Table 2-2. List of Special Function Registers (1/4)
Manipulable Bit Unit
Address
Special Function Register (SFR) Name
Symbol
R/W
On Reset
1 bit
8 bits
16 bits
––
FF00H
Port 0
P0
R/W
●
●
FF02H
Port 2
P2
R
––
●
FF03H
Port 3
P3
●
●
FF04H
Port 4
P4
●
●
FF05H
Port 5
P5
●
●
FF07H
Port 7
P7
––
●
FF08H
Port 8
P8
●
●
P9
●
●
TM0LW
––
––
––
––
––
––
––
––
––
––
––
––
––
––
––
––
––
––
––
––
––
––
––
––
––
––
R/W
R
R/W
FF09H
Port 9
FF0AH
Free running counter
FF0BH
(lower 16 bits) Note
FF10H
Capture register X0
Note
FF11H
(lower 16 bits)
FF12H
Capture register 01
FF13H
(lower 16 bits)
Note
FF14H
Capture register 02
FF15H
(lower 16 bits)
Note
FF16H
Capture register 03
FF17H
(lower 16 bits) Note
FF18H
Capture/compoare register X0
Note
FF19H
(lower 16 bits)
FF1AH
Capture/compoare register 01
CTX0LW
CT01LW
R
CT02LW
CT03LW
CCX0LW
––
––
Undefined
––
––
●
0000H
●
●
●
Undefined
●
●
R/W
CC01LW
Note
●
FF1BH
(lower 16 bits)
FF20H
Port 0 mode register
PM0
––
●
––
FFH
FF23H
Port 3 mode register
PM3
––
●
––
× × ×1 1111B
FF25H
Port 5 mode register
PM5
––
●
––
FFH
FF28H
Port 8 mode register
PM8
––
●
––
× × 11 1111B
FF29H
Port 9 mode register
PM9
––
●
––
× × × × 1111B
FF2AH
Free runnting counter
––
––
●
––
––
––
––
––
––
––
––
––
––
––
––
––
––
––
––
––
––
FF2BH
(higher 16 bits)
Note
W
TM0UW
FF2CH
Timer register 1
FF2DH
FF30H
Capture register X0
FF31H
(higher 16 bits)
Note
FF32H
Capture register 01
FF33H
(higher 16 bits)
Note
FF34H
Capture register 02
FF35H
Note
(higher 16 bits)
TM1
CTX0UW
R
CT01UW
CT02UW
0000H
●
●
●
Undefined
●
Note Upper or lower half of 18-bit register.
25
µPD78323, 78324
Table 2-2. List of Special Function Registers (2/4)
Manipulable Bit Unit
Address
Special Function Register (SFR) Name
FF36H
Capture register 03
FF37H
(higher 16 bits)
Note
FF38H
Capture/compoare register X0
Note
FF39H
(higher 16 bits)
FF3AH
Capture/compoare register 01
Symbol
CT03UW
R/W
R
8 bits
––
––
––
––
––
––
––
––
––
––
––
––
CCX0UW
R/W
Note
On Reset
1 bit
CC01UW
16 bits
●
●
Undefined
●
FF3BH
(higher 16 bits)
FF40H
Port 0 mode control register
PMC0
W
––
●
––
FF41H
Realtime output port reset register
RTPS
R/W
●
●
––
FF43H
Port 3 mode control register
PMC3
––
●
––
× × ×0 0000B
––
●
––
× × 00 0000B
––
––
––
––
●
●
––
FF48H
Port 8 mode control register
W
PMC8
FF4CH
Baud rate generator
FF4DH
BRG
●
Undefined
FF60H
Realtime output port register
FF61H
Realtime output port reset register
RTPR
●
●
––
FF62H
Port read control register
PRDC
●
●
––
FF68H
A/D converter mode register
ADM
●
●
––
ADCR
––
––
●
––
●
––
––
––
––
––
––
––
FF73H
––
––
FF74H
––
––
––
––
––
––
––
––
––
––
––
––
––
––
––
––
CSIM
●
●
SBIC
●
●
––
SIO
●
●
––
RTP
R/W
A/D conversion result register
FF6AH
FF70H
R
ADCRH
(for upper 8-bit access)
Compare register 00
CM00
R/W
FF71H
FF72H
00H
(for 16-bit access)
A/D conversion result register
FF6BH
00H
Compare register 01
CM01
●
●
Undefined
Compare register 02
CM02
FF75H
FF76H
Compare register 03
CM03
FF77H
FF7CH
Compare register 10
CM10
FF7DH
FF7EH
Compare register 11
CM11
FF7FH
Clock synchronous serial
FF80H
interface mode register
FF82H
Serial bus interface control register
FF86H
Serial I/O shift register
Note Upper or lower half of 18-bit register.
26
R/W
●
●
●
●
––
00H
Undefined
µPD78323, 78324
Table 2-2. List of Special Function Registers (3/4)
Manipulable Bit Unit
Address
Special Function Register (SFR) Name
Symbol
R/W
8 bits
16 bits
●
●
––
80H
●
●
––
00H
––
●
––
––
●
––
TMC
●
●
––
BRGM
●
●
––
●
●
––
Asynchronous serial interface
FF88H
On Reset
1 bit
ASIM
R/W
mode register
Asynchronous serial interface
ASIS
FF8AH
status register
R
FF8CH
Serial receive buffer
:UART
RXB
FF8EH
Serial send shift register
:UART
TXS
FFB0H
Timer control register
FFB1H
Baud rate generator mode register
FFB2H
Prescalar mode register
W
PRM
R/W
Undefined
FFB8H
Timer output control register 0
TOC0
●
●
––
FFB9H
Timer output control register 1
TOC1
●
●
––
FFBFH
RPU mode register
RPUM
●
●
––
●
●
––
00H
0000 × 000B
FFC0H
Standby control register
STBC
R/WNote
FFC1H
CPU control word
CCW
R/W
●
●
––
FFC2H
Watchdog timer mode register
WDM
R/WNote
●
●
––
FFC4H
Memory expansion mode register
MM
●
●
––
FFC6H
Programmable weight control register
PWC
●
●
––
22H
FFC9H
Fetch cycle control register
FCC
●
●
––
00H
●
●
––
Undefined
●
●
●
●
●
●
––
––
●
●
●
●
●
●
––
––
●
●
●
●
●
●
––
––
●
●
●
●
FFD0H to
External acces area
00H
FFDFH
FFE0H
Interrupt request flag rgister 0L
IF0L
FFE1H
Interrupt request flag rgister 0H
IF0H
FFE2H
Interrupt request flag rgister 1L
IF1L
FFE3H
––
Interrupt mask flag rgister 0L
FFE5H
Interrupt mask flag rgister 0H
MK0H
FFE6H
Interrupt mask flag rgister 1L
MK1L
MK0L
MK0
MK1
––
––
FFE8H
Priority specify bufer register 0L
FFE9H
Priority specify bufer register 0H
PB0H
FFEAH
Priority specify bufer register 1L
PB1L
FFEBH
FFECH
PB0L
PB0
R/W
PB1
––
Interrupt processing mode specify register 0L
––
ISM0L
ISM0
FFEDH
Interrupt processing mode specify register 0H
ISM0H
FFEEH
Interrupt processing mode specify register 1L
ISM1L
FFEFH
IF1
––
FFE4H
FFE7H
IF0
●
●
––
––
ISM1
––
––
●
00H
●
––
●
●
FFH
× × × × × 111B
––
●
00H
●
––
●
00H
●
––
Note Write enable in case of special instructions.
27
µPD78323, 78324
Table 2-2. List of Special Function Registers (4/4)
Manipulable Bit Unit
Address
FFF0H
Symbol
Special Function Register (SFR) Name
Context switching enable register 0L
CSE0L
CSE0
FFF1H
Context switching enable register 0H
CSE0H
FFF2H
Context switching enable register 1L
CSE1L
FFF3H
CSE1
––
R/W
R/W
––
On Reset
1 bit
8 bits
●
●
●
●
●
●
––
––
16 bits
●
00H
●
––
FFF4H
External interupt mode register 0
INTM0
●
●
––
FFF5H
External interupt mode register 1
INTM1
●
●
––
FFF8H
In-service priority register
ISPR
R
––
●
––
FFF9H
Priority specify register
PRSL
R/W
●
●
––
2.3
00H
DATA MEMORY ADDRESSING
In the µPD78324, the internal RAM space (FB00H to FEFFH) and the special function register area (FF00H to FFFFH)
are mapped in the FB00H to FFFFH area. In the FE20H to FF1FH space of the data memory, short direct addressing enables
direct addressing by 1-byte data in an instruction word.
Figure 2-6. Data Memory Addressing Space
FFFFH
FF1FH
FF00H
FEFFH
Special Function Register
(SFR)
General Register
SFR Addressing
Register Addressing
Short Direct Addressing
FE80H
FE20H
Main RAM
FE00H
FDFFH
Peripheral RAM
FB00H
External Memory
Direct Addressing
Register Indirect Addressing
Based Addressing
Paste Indexed Addressing
Paste Indexed Addressing
(Provided with Displacement)
7FFFH
Internal ROMNote
0000H
Note When EA = L, and with the µPD78323, this is external memory.
Caution For word access (including stack operations) to the main RAM area (FE00H-FEFFH), the address that
specifies the operand must be an even value.
28
µPD78323, 78324
2.3.1 General Register Addressing
The general registers consist of eight register banks, each consisting of sixteen 8-bit registers or eight 16-bit registers.
General register addressing is carried out using the register specify field of 3 or 4 bits supplied from an instruction word,
the register bank select flag (RBS0 to RBS2) and the register set select flag (RSS) in the PSW.
2.3.2
Short Direct Addressing
Short direct addressing which enables direct address specification by 1-byte data in an instruction work is applied to the
FE20H to FF1FH space. The short direct memory is accessed as 8-bit or 16-bit data. When accessing the memory as 16bit data, specification of even data for 1-byte address specify data will cause 2-byte data specified by continuous addresses
of even and odd addresses to be accessed. (Do not specify odd number for address specify data.)
2.3.3
Special Function Register (SFR) Addressing
This addressing is applied to operations for the special function register (SFR) mapped in the SFR area of FF00H to
FFFFH. Addressing is performed by 1-byte data in the instruction word corresponding to the lower 8 bits of the special
function register address. For 16-bit access of 16-bit operational SFR, 2-byte data specified by continuous even and odd
addresses is accessed as is the case with short direct addressing.
29
µPD78323, 78324
3. BLOCK FUNCTIONS
3.1 BUS CONTROL UNIT (BCU)
In the BCU, the necessary bus cycle is started according to the physical address obtained by the execution unit (EXU).
If no bus cycle startup request is made from the EXU, a prefetch address is generated and instruction prefetch is carried
out. The prefetched instruction code is fetched into the instruction queue.
3.2
EXECUTION UNIT (EXU)
In the EXU, address calculation, arithmetic logical operation and data transfer are controlled by microprograms. A 256byte RAM is built in the EXU.
The 256-byte RAM in the EXU is accessible by the relevant instruction faster than peripheral RAM (768 bytes).
3.3 ROM/RAM
This block consists of a 32K-byte ROM and a 768-byte RAM. However, the µPD78323 does not incorporate ROM.
ROM access can be disabled by EA pin.
3.4 INTERRUPT CONTROLLER
Various interrupt requests (NMI, INTP0 to INTP6) generated either externally or from the peripheral hardware are
processed by the context switch, vectored interrupt or macro service function.
The 3-level interrupt priority is also specified.
30
µPD78323, 78324
3.5
PORT FUNCTIONS
Table 3-1 lists the digital input/output ports.
Each port can carry out many control operations including 8 and other bit data input/output operations.
Table 3-1. Port Functions and Features
Port Name
Function
Feature
Remarks
Port 0
8-bit input/outpput
Specifiable bit-wise for input/output.
Also specifiable for realtime output port.
Serves as RTP0 to RTP7
and pins.
Port 2
8-bit input
Input port pin. Functions as an external interrupt input.
Serves as NMI, INTP0 to
INTP5, INTP6/TI and pins.
Port 3
5-bit input/output
Specifiable bit-wise for port pins or control pins.
Serves as TXD, RXD,
SO/SB0, SI/SB1, SCK and
pins.
Port 4
8-bit input/output
Specifiable in 8-bit units for input or output.
Functions as the multiplexed address/data bus (AD0 to
AD7) in the external memory expansion mode.
––––––––
Port 5
8-bit input/output
Specifiable bit-wise for input or output.
Functions as the address bus (A8 to A15) in the external
memory expansion mode.
Pins which are not used as the address bus can be used
as a port.
––––––––
Port 7
8-bit input
Input port pin. Also functions as analog input to the
A/D converter.
Serves as AN0 to AN7
and pins.
Port 8
6-bit input/output
Specifiable bit-wise for the port pin or control pin.
Functions as TO00 to
TO03, TO10 to TO11 and
pins.
4-bit input/output
Specifiable bit-wise for input/output.
P90 and P91 function as RD output and WR output,
respectively, in the external memory expansion mode.
P92 and P93 function as TAS output and TMD output,
respectively, in the high-speed fetch mode.
Port 9
––––––––
31
µPD78323, 78324
3.6 CLOCK GENERATOR
The clock generator generates and controls internal system clocks (CLK) supplied to the CPU. It is configured as shown
in Figure 3-1.
Figure 3-1. Block Diagram of Clock Generator
X1
Divider
System
Clock
Generator
fXX or fX
1/2
fCLK
Internal System
Clock (CLK)
X2
STOP Mode
Remarks
1.
2.
fXX : Crystal oscillator frequency
fX : External clock frequency
3.
fCLK : Internal system clock frequency
The system clock oscillator oscillates by a crystal resonator connected to X1 and X2 pins. It stops oscillating when set
to the standby mode (STOP).
External clocks can be input to the system clock oscillator. In such cases, input a clock signal to the X1 pin and input
the reverse phase of the clock signal to the X2 pin. The X2 pin can also be left open.
Caution When using external clocks, do not set the STBC STP bit.
The divider generates internal system clocks (fCLK) by dividing a system clock oscillator output (fxx for crystal oscillation
and fx for external clocks) into two parts.
32
µPD78323, 78324
Figure 3-2. Externally-Mounted System Clock Generator
(a) Crystal oscillator
µ PD78324
X2
X1
VSS
(b) External clock
(ii) When X2 pin is left open
(i) When the inverted phase of an
external clock to be input to the
X1 pin is input to the X2 pin
µ PD78324
µ PD78324
External
Clock
X1
External
Clock
X2
X1
Open X2
Cautions 1. When the system clock oscillator is used, the following points should be noted concerning wiring
within broken lines shown in Figure 3-2, in order to prevent the effects of wiring capacitance, etc.
• Keep the wiring as short as possible.
• Do not cross any other signal lines, and keep clear of lines in which a high fluctuating current
flows.
• Ensure that oscillator capacitor connection points are always at the same potential as VSS. Do not
ground in a ground pattern in which a high current flows.
• Do not take a signal from the oscillator.
2. When an external clock is input to the X1 pin and the X2 pin is left open, ensure that no loads such
as wiring capacitance are connected to the X2 pin.
33
µPD78323, 78324
3.7 REALTIME PULSE UNIT (RPU)
This unit can measure pulse intervals and frequencies, and generate programmable pulse outputs.
It consists mainly of two timers. To flexibly cope with many applications, the configuration of registers connected to the
timers can be changed using programs. To meet various applications, toggle output (6 max.) or set/ reset output (4 max.)
can be selected as timer output.
3.7.1 Configuration
The realtime pulse unit is configured mainly of timer 0 (TM0) which functions as a 16-bit or 18-bit free running timer and
timer 1 (TM1) which functions as a 16-bit timer/event counter shown in Figure 3-3.
34
Figure 3-3. Realtime Pulse Unit Configuration
TM1
TM0
INTOV
2
(CLEAR CONTROL)
10 11
fCLK/4
fCLK/8
0
15
16/18-BIT FREE RUNNING TIMER
17
INTP6/TI
OVF
fCLK/16
INTP0
(OPPOSITE EDGE)
OVF
16-BIT TIMER/EVENT COUNTER
INTCM00
T
COMPARE REG. CM00
COMPARE REG. CM01
COMPARE REG. CM02
COMPARE REG. CM03
INTCM01
INTCM02
INTCM03
TO00
R
S
T
TO01
R
S
T
TO02
R
S
Match
TO03
T
INTP0
INTP1
INTP2
INTP3
INTCCX0
INTP5
INTCM10
COMPARE REG. CM10
INTCM11
COMPARE REG. CM11
Match
CAPTURE REG. CT01
T
TO11
CAPTURE REG. CT02
R
S
TO10
CAPTURE REG. CT03
CAPTURE/COMPARE REG. CC01
T
INTCC01
Match
MODE0
MODE1
CAPTURE REG. CTX0
INTP4
CAPTURE/COMPARE REG. CCX0
INTP0
INTCCX0
Match
35
µPD78323, 78324
INTP0
µPD78323, 78324
3.7.2 Realtime Output Function
The realtime output port can set/reset port outputs bit-wise in synchronization with the trigger signal transmitted from
the RPU (Realtime Pulse Unit). It enables to generate multi-channel synchronous pulses easily.
Figure 3-4. Realtime Output Port
WRPORT
PMC0n = 0
P0n
Output Latch
INTCM03
WRRTPR
RTPn
R
RTPRn
WRPTP
Internal Bus
PMC0n = 1
D
Q
P0n
WRRTPS
S
RTPSn
PM0n = 0
INTCCX0
RD
36
PM0n = 1
µPD78323, 78324
3.8 A/D CONVERTER
The µPD78324 incorporates a high-speed, high-resolution 10-bit analog/digital (A/D) converter. This A/D converter is
equipped with eight analog inputs (AN0 to AN7) and A/D conversion result register (ADCR) which holds the conversion
results. Upon termination of conversion, the interrupt which can start the macro service is generated.
Figure 3-5. A/D Converter Block Diagram
Sample & Hold Circuit
AVREF
Input Circuit
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
D/A Converter
AVSS
Comparator
ADM (8)
SAR (10)
8
10
Internal Bus
ADCR (10)
10
10
Internal Bus
3.9 SERIAL INTERFACE
The µPD78324 is equipped with the following two independent channels for the serial interface function.
Asynchronous serial interface
Clock synchronous serial interface
• 3-wire serial I/O mode
• Serial bus interface mode (SBI mode)
Since the µPD78324 incorporates a baud rate generator, it can set any serial transfer rate irrespective of the operating
frequency. The baud rate generator functions for the 2-channel serial interface.
The serial transfer rate can be selected from 75 bps to 19.2 Kbps by setting the mode register.
37
38
Figure 3-6. Asynchronous Serial Interface Block Diagram
Internal Bus
ASIM
RXB
Receive Buffer
REX PS1 PS0 CL
SL SCK
BRG
BRGM
ASIS
RXD
Shift Register
PE
FE OVE
TXS
1
2
Shift Register
Match
Clear
TXD
1
16
INTSER
Send Control
Parity
Addition
fCLK/8
INTST
INTSR
1
16
Send/Receive Baud Rate Generator Output
fCLK/4
Baud Rate Generator
µPD78323, 78324
Selector
Receive
Control
Parity
Check
Figure 3-7. Block Diagram of Clock Synchronous Serial Interface
Internal Bus
8
8
CSIM
SBIC
RELT CMDT RELD CMDD ACKT ACKE ACKD BSYE
SET
CLEAR
MOD2 CTXE CRXE WUP MOD1 CLS1 CLS0 MOD0
SI/SB1
Shift Register SIO
D
Q
SO Latch
SO/SB0
Busy/
Acknowledge
Detector
N-ch Open Drain
Output Enable
Bus Release/
Command/Acknowledge
Detector
SCK
Serial Clock
Counter
INTCSI
MPX
CLS1 CLS0
Baud Rate Generator
Output
fCLK/8
fCLK/32
39
µPD78323, 78324
Serial Clock
Controller
Interrupt
Signal
Generation
Controller
µPD78323, 78324
3.10 WATCHDOG TIMER
The watchdog timer is used to prevent program overrun and deadlock. Normal operation of the program or system can
be confirmed by checking that no watchdog timer interrupt has been generated. Thus, an instruction to clear the watchdog
timer (timer start) is set into each program module.
If the watchdog timer clear instruction is not cleared within the time period set into the watchdog timer and the watchdog
timer overflows, a watchdog timer interrupt is generated, and a low level is generated to WDTO pin, thereby notifying of
an error in the program.
The watchdog timer can also be used to maintain the oscillation stabilizing time of the oscillator after the stop mode has
been released.
Figure 3-8 shows the watchdog timer configuration.
Figure 3-8. Watchdog Timer Configuration
fCLK/28
fCLK/210
Watchdog Timer (8 Bits)
Overflow
fCLK/212
Timer (5 Bits)
Clear
WDT CLR
WDT STOP
INTWDT
Oscillation Stabilizing
Time Controller
40
WDTO
µPD78323, 78324
4. INTERRUPT FUNCTIONS
4.1 OVERVIEW
In the µPD78324, various interrupt requests generated externally or from the on-chip peripheral hardware are handled
in the following three processing modes.
Interrupt Request
Handled by Vectored Interrupt Processing
Handled by Context Switching
Handled by Macro Service
Interrupt requests are classified into the following three groups.
• Nonmaskable interrupt requests
• Maskable interrupt requests
• Interrupt requests by software
Figure 4-1 shows the maskable interrupt request processing modes. Table 4-1 gives a listing of interrupt factors which
can be processed.
Figure 4-1. Interrupt Request Processing Modes
× × MK = 1 (Interrupt Masked)
Vectored Interrupt and Macro Service Reserved
× × MK = 0 (Interrupt Unmasked)
× × ISM = 0 (Vectored Interrupt Processing Mode)
DI
Vectored Interrupt Processing Reserved
EI
× × CSE = 0 Vectored Interrupt Processing Executed
× × CSE = 1 Context Switching Executed
× × ISM = 1 (Macro Service Processing Mode)
Macro Service Processing Executed
41
µPD78323, 78324
Table 4-1. List of Interrupt Factors
Interrupt
Default
Request Type
Priority
Request Signal
Interrupt Factor
–––
–––
BRK instruction
–––
–––
003EH
–––
–––
Operation code trap
–––
–––
003CH
Function
Generator
Unit
Macro
Service
Vector Table
Address
Software
Nonmaskable
–––
NMI
NMI pin input
(External
interrupt)
–––
0002H
–––
INTWDT
Watchdog timer
(WDT)
–––
0004H
0
INTOV
Timer 0 overflow
(RPU)
0006H
1
INTP0
INTP0 pin input
(External)
0008H
2
INTP1
INTP1 pin input
(External)
000AH
3
INTP2
INTP2 pin input
(External)
000CH
4
INTP3
INTP3 pin input
(RPU/exteranl)
000EH
5
INTP4/INTCCX0
INTP4 pin input/CCX0 match signal
(RPU/exteranl)
0010H
6
INTP5/INTCC01
INTP5 pin input/CC01 match signal
(RPU/exteranl)
0012H
7
INTP6/TI
INTP6 pin input/TI input
(Exteranl)
0014H
8
INTCM00
CM00 match signal
(RPU)
Maskable
0016H
Available
9
INTCM01
CM01 match signal
(RPU)
0018H
10
INTCM02
CM02 match signal
(RPU)
001AH
11
INTCM03
CM03 match signal
(RPU)
001CH
12
INTCM10
CM10 match signal
(RPU)
001EH
13
INTCM11
CM11 match signal
(RPU)
0020H
14
INTSR
Serial receive terminate interrupt
(UART)
0024H
15
INTST
Serial send terminate interrupt
(UART)
0026H
16
INTCSI
Serial send/receive interrupt
(CSI)
0028H
17
INTAD
A/D conversion terminate interrupt
(A/D)
002AH
–––
–––
INTSERNote
Serial receive error signal
(UART)
Reset
–––
RESET
Reset input
Note This is a test factor. A vectored interrupt is not generated.
42
–––
–––
–––Note
–––
0000H
µPD78323, 78324
4.2 MACRO SERVICE
The macro service function is executed at the interrupt request to carry out data operation and data transfer in hardware
terms between the special function register area and the memory space.
Upon startup of the macro service, the CPU stops program execution temporarily. 1-byte/2-byte data operation and
transfer are automatically carried out between the special function register (SFR) and the memory. Upon termination of the
macro service, the interrupt request flag is reset to 0 and the CPU restarts program execution. When the CPU carries out
the macro service operations as many as set into the macro service counter (MSC), a vectored interrupt request is generated.
Figure 4-2. Macro Service Processing Sequence Example
Macro Service Processing
Interrupt Request Generated
Macro service execution
MSC ← MSC–1
Yes
MSC = 0?
; Data Transfer, and Realtime
Output Port Control
; Macro Service Counter (MSC)
Decrement (by 1)
No
ISM×× ← 0
Interrupt request flag ← 0
Vectored Interrupt Request Occurred
Next Instruction Executed
43
µPD78323, 78324
4.3 CONTEXT SWITCHING FUNCTION
This is the function to first select the specified register bank in hardware terms by generating an interrupt request or
executing BRKCS instruction, to branch the selected register bank to the vector address prestored in the register bank, and
also to stack the current PC and PSW contents into the register bank.
4.3.1
Context Switching Function at Interrupt Request
The context switching function start is enabled by setting the × ×CSE bit preset at each interrupt request to 1.
If an unmasked interrupt request for which the context switching function has been enabled is generated in the EI state,
the register bank which is specified by the lower 3 bits of the lower address (even address) of the corresponding interrupt
vector table address is selected. The vector address prestored in the selected register bank is transferred to the PC, the
PC and PSW contents are saved into the register bank, and the operation is branched to the interrupt processing routine.
Return is by means of executing the RETCS instruction.
Figure 4-3. Context Switching at Interrupt Request
Register
Banks
(0 to 7)
RBANK n
PC
Exchange
Save
A
X
B
C
R5
R4
R7
R6
VP
PSW
UP
44
D
E
H
L
µPD78323, 78324
4.3.2 Context Switching Function by BRKCS Instruction
The context switching function can be started by executing BRKCS instruction.
The context switched register bank is specified by the lower 3-bit immediate data of the 2nd operation code of BRKCS
instruction. When BRKCS instruction is executed, the register bank specified by the 3-bit immediate data is selected, the
vector address prestored in the register bank is set and branched to the PC, and the PC and PSW contents are saved into
the register bank.
Return is by means of executing the RETCSB instruction.
Figure 4-4. Context Switching by Execution of BRKCS Instruction
OP CODE
(BRKCS)
OP CODE
N2
N1
N0
Register Bank Specification
RBANK n
PC
Exchange
Save
000
RBANK0
111
RBANK7
Register
Banks
(0 to 7)
(n = 0 – 7)
A
X
B
C
R5
R4
R7
R6
VP
PSW
UP
D
E
H
L
45
µPD78323, 78324
5. STANDBY FUNCTIONS
The µPD78324 has the standby function to decrease the power consumption of the system. The following two modes
are available for execution of the standby function.
• HALT mode........ Mode for halting the CPU operation clock. The total power consumption of the
system can be decreased by intermittent operation in combination with the normal
operating mode.
• STOP mode....... Mode for stopping the whole system by stopping the oscillator. Considerably low
power consumption with leak current only can be set.
Each mode is set by the software. Figure 5-1 shows standby mode (STOP/HALT mode) transition.
Figure 5-1. Standby Status Transition
t
Se
RE
OP
I
NM
ST
se
t
se
lea
Re
LT
46
d
ke
as
m pt d
Un erru rate
t
In ene
G
STOP
T
HA
SE
T
SE
Re
RE
lea
se
Normal
Status
HALT
µPD78323, 78324
6. EXTERNAL DEVICE EXPANSION FUNCTION
The µPD78324 can expand external devices (data memory, program memory peripheral device) for areas (8000H to
FAFFH) except the internal ROM and RAM areas. Table 6-1 and 6-2 show the pin used for external device access and the
pin function setting procedure.
Table 6-1. Pin Function Setting (µPD78324)
EA Pin
Memory Expansion
Mode Register
MM0 to MM2
MM7
Fetch Cycle
Control
Register
0
00H
Port mode
Pin Function
Remarks
P40 to P47
P50 to P57
P92
P93
Setting prohibited
0
Expansion
mode
P91
General port
1
1
P90
00H
AD0 to AD7
Except 00H
1
Set to A8 to
A15 in steps
RD
General port
External device
connection mode
TAS
µPD71P301
connection mode
WR
TMD
P50 to P57 pins according to the externally expanded memory size. The memory can be expanded in steps from 256
bytes to about 32K bytes. The pins which are not used as the address bus can be used as the general-purpose input/output
port.
Table 6-2. Port and Address Setting for Port 5 (µPD78324)
P57
P56
P55
P54
P53
P52
P51
P50
External Address Space
Port
Port
Port
Port
Port
Port
Port
Port
256 bytes or less
Port
Port
Port
Port
A11
A10
A9
A8
4K bytes or less
Port
Port
A13
A12
A11
A10
A9
A8
16K bytes or less
A15
A14
A13
A12
A11
A10
A9
A8
About 32K bytes or less
Table 6-3. Pin Function Setting (µPD78323)
EA Pin
Memory Expansion
Mode Register
MM7
ASTB
Fetch Cycle
Control
Register
Pin Function
Remarks
AD0 to AD7
A8 to A15
RD
WR
––
0
00H
1
Except 00H
AD0 to AD7
A8 to A15
RD
WR
P92
P93
TAS
TMD
µPD78324
emulation mode
General port
External device
connection mode
TAS
µPD71P301
connection mode
1
TMD
47
µPD78323, 78324
7. OPERATION AFTER RESET
If the RESET input pin is set to the low level, the system reset is applied and each hardware becomes as initialized status
(reset status). If RESET input becomes high level, program execution is started. Initialize the contents of various registers
in the program as required.
Change the number of cycles for the programmable wait register and the fetch cycle control register in particular.
The RESET input pin is equipped with an analog delay noise suppressor to prevent malfunctioning due to noise.
Cautions 1. While RESET is active(low level), all pins remain high impedance (except WDTO, AVREF, AVDD, AVSS,
VDD, VSS, X1 and X2).
2. If RAM has been expanded externally, mount a pull-up resistor to the P90/RD and P91/WR pins. It is
possible that the P90/RD and P91/WR pins become high impedance resulting in an external RAM
contents corruption or input unit damage. In addition, signals may collide on the address/data bus,
resulting in the destruction of the input/output circuit.
Figure 7-1. Reset Signal Acknowledge
RESET Input
Analog
Delay
Analog
Delay
∇
∇
Analog
Delay
Removed
as Noise
Reset
Acknowledged
Reset
Release
For reset operation upon power-up, secure the oscillation stabilizing time of about 40 msec from power-up to reset
acknowledge as shown in Figure 7-2.
Figure 7-2. Reset Upon Power-Up
VDD
RESET
Analog
Delay
∇
Oscillation
Stabilizing
Time
Reset
Release
48
µPD78323, 78324
8. INSTRUCTION SET
This chapter covers instruction operations.
For the operation codes and the number of instruction execution clock cycles, see µPD78322 User’s Manual (IEU-1248).
(1) Operand representation format and description method
In each instruction operand column, enter the operand using the description method for the instruction operand
representation format (refer to the assembler specification for details). If two or more factors are included in the description
method column, select one factor. The capital alphabetic letters and +, -, #, $, ! and [ ] symbols are keywords and should
be described as they are.
In case of immediate data, describe appropriate numeric values or labels. When describing labels, make sure to describe
#, $, ! and [ ] symbols.
Table 8-1. Operand Representation and Description Method
Representation
Format
Description Method
r
r1
r2
R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15
R0, R1, R2, R3, R4, R5, R6, R7
C, B
rp
rp1
rp2
RP0, RP1, RP2, RP3, RP4, RP5, RP6, RP7
RP0, RP1, RP2, RP3, RP4, RP5, RP6, RP7
DE, HL, VP, UP
sfr
sfrp
Special function register code (see Table 2-2)
Special function register code (16-bit operation enable register; see Table 2-2)
post
RP0, RP1, RP2, RP3, RP4, RP5/PSW, RP6, RP7
(Two or more instructions can be described. Only PUSH and POP instructions can be
described for RP5 and only PUSHU and POPU instructions can be described for PSW.)
mem
[DE], [HL], [DE+], [HL+], [DE-], [HL-], [VP], [UP]
[DE+A], [HL+A], [DE+B], [HL+B], [VP+DE], [VP+HL]
[DE+byte], [HL+byte], [VP+byte], [UP+byte], [SP+byte]
word[A], word[B], word[DE], word[HL]
saddr
saddrp
FE20H to FF1FH Immediate data or label
FE20H to FF1EH Immediate data (bit0 = 0) or label (for 16-bit operation)
$addr16
!addr16
addr11
addr5
0000H to FDFFH Immediate data or label; relative addressing
0000H to FDFFH Immediate data or label; immediate addressing
(Up to FFFFH describable by MOV instruction)
800H to FFFH Immediate data or label
40H to 7EH Immediate data (bit0 = 0)Note or label
word
byte
bit
n
16-bit immediate data or label
8-bit immediate data or label
3-bit immediate data or label
3-bit immediate data (0 to 7)
;
;
;
;
Register indirect mode
Based indexed mode
Based mode
Index mode
Note Do not make work access to bit0 = 1 (odd address).
Remarks
1.
Although rp and rp1 have the same describable register names, they generate different codes.
2.
r, r1, rp, rp1 and post can be described with absolute names (R0 to R15, RP0 to RP7) as well as functional
names (X, A, C, B, E, D, L, H, AX, BC, DE, HL, VP, UP (refer to Table 2-1 for details of the relationships
3.
between the absolute and functional names).
Immediate addressing is enabled for all spaces. Relative addressing is only enabled from the first address
of the subsequent instruction to the range of –128 to +127.
49
Operand
Mnemonic
8-bit data transfer
MOV
Note
Operation
r1, #byte
2
r1 ← byte
saddr, #byte
3
(saddr) ← byte
sfrNote,
3
sfr ← byte
r, r1
2
r ← r1
A, r1
1
A ← r1
A, saddr
2
A ← (saddr)
saddr, A
2
(saddr) ← A
saddr, saddr
3
(saddr) ← (saddr)
A, sfr
2
A ← sfr
sfr, A
2
sfr ← A
#byte
A, mem
1-4 A ← (mem)
mem, A
1-4 (mem) ← A
A, [saddrp]
2
A ← ((saddrp))
[saddrp], A
2
((saddrp)) ← A
A, !addr16
4
A ← (addr16)
!addr16, A
4
(addr16) ← A
PSWL, #byte
3
PSWL ← byte
PSWH, #byte
3
PSWH ← byte
PSWL, A
2
PSWL ← A
PSWH, A
2
PSWH ← A
A, PSWL
2
A ← PSWL
A, PSWH
2
A ← PSWH
A, r1
1
A ↔ r1
r, r1
2
r ↔ r1
A, saddr
2
A ↔ (saddr)
A, sfr
3
A ↔ sfr
A, [saddrp]
2
A ↔ ((saddrp))
saddr, saddr
3
(saddr) ↔ (saddr)
Z
AC P/V CY
×
×
×
×
×
×
×
×
×
×
If STBC and WDM are described for sft, a different dedicated instruction having a different number of bytes
is used.
Remark For the symbols in the Flags column, refer to the table below.
Symbol
(Blank)
0
1
×
P
V
R
50
S
2-4 A ↔ (mem)
A, mem
XCH
Flags
Bytes
Instruction
Group
µPD78323, 78324
Description
No change
Clear to 0.
Set to 1.
Set/clear according to the result.
P/V flag operates as a parity flag
P/V flag operates as an overflow flag.
The previously stored value is restored.
16-bit data transfer
Operand
Mnemonic
MOVW
XCHW
8-bit opration
ADDC
Operation
rp1, #word
3
rp1 ← word
saddrp, #word
4
(saddrp) ← word
sfrp, #word
4
sfrp ← word
rp, rp1
2
rp ← rp1
AX, saddrp
2
AX ← (saddrp)
saddrp, AX
2
(saddrp) ← AX
saddrp, saddrp
3
(saddrp) ← (saddrp)
AX, sfrp
2
AX ← sfrp
sfrp, AX
2
sfrp ← AX
rp1, !addr16
4
rp1 ← (addr16)
!addr16, rp1
4
(addr16) ← rp1
AX, mem
2-4 AX ← (mem)
mem, AX
2-4 (mem) ← AX
AX, saddrp
2
AX ↔ (saddrp)
AX, sfrp
3
AX ↔ sfrp
saddrp, saddrp
3
(saddrp) ↔ (saddrp)
rp,rp1
2
rp ↔ rp1
AX, mem
ADD
Flags
Bytes
Instruction
Group
µPD78323, 78324
S
Z
AC P/V CY
2-4 AX ↔ (mem)
A, #byte
2
A, CY ← A + byte
×
×
×
V
×
saddr, #byte
3
(saddr), CY ← (saddr) + byte
×
×
×
V
×
sfr, #byte
4
sfr, CY ← sfr + byte
×
×
×
V
×
r, r1
2
r, CY ← r + r1
×
×
×
V
×
A, saddr
2
A, CY ← A + (saddr)
×
×
×
V
×
A, sfr
3
A, CY ← A + sfr
×
×
×
V
×
saddr, saddr
3
(saddr), CY ← (saddr) + (saddr)
×
×
×
V
×
A, mem
2-4 A, CY ← A + (mem)
×
×
×
V
×
mem, A
2-4 (mem), CY ← (mem) + A
×
×
×
V
×
A, #byte
2
A, CY ← A + byte + CY
×
×
×
V
×
saddr, #byte
3
(saddr), CY ← (saddr) + byte + CY
×
×
×
V
×
sfr, #byte
4
sfr, CY ← sfr + byte + CY
×
×
×
V
×
r, r1
2
r, CY ← r + r1 + CY
×
×
×
V
×
A, saddr
2
A, CY ← A + (saddr) + CY
×
×
×
V
×
A, sfr
3
A, CY ← A + sfr + CY
×
×
×
V
×
saddr, saddr
3
(saddr), CY ← (saddr) + (saddr) + CY
×
×
×
V
×
A, mem
2-4 A, CY ← A + (mem) + CY
×
×
×
V
×
mem, A
2-4 (mem), CY ← (mem) + A + CY
×
×
×
V
×
51
8-bit opration
SUB
SUBC
AND
52
Operand
Mnemonic
Flags
Bytes
Instruction
Group
µPD78323, 78324
Operation
S
Z
AC P/V CY
A, #byte
2
A, CY ← A – byte
×
×
×
V
×
saddr, #byte
3
(saddr), CY ← (saddr) – byte
×
×
×
V
×
sfr, #byte
4
sfr, CY ← sfr – byte
×
×
×
V
×
r, r1
2
r, CY ← r – r1
×
×
×
V
×
A, saddr
2
A, CY ← A – (saddr)
×
×
×
V
×
A, sfr
3
A, CY ← A – sfr
×
×
×
V
×
saddr, saddr
3
(saddr), CY ← (saddr) – (saddr)
×
×
×
V
×
A, mem
2-4 A, CY ← A – (mem)
×
×
×
V
×
mem, A
2-4 (mem), CY ← (mem) – A
×
×
×
V
×
A, #byte
2
A, CY ← A – byte – CY
×
×
×
V
×
saddr, #byte
3
(saddr), CY ← (saddr) – byte – CY
×
×
×
V
×
sfr, #byte
4
sfr, CY ← sfr – byte – CY
×
×
×
V
×
r, r1
2
r, CY ← r – r1 – CY
×
×
×
V
×
A, saddr
2
A, CY ← A – (saddr) – CY
×
×
×
V
×
A, sfr
3
A, CY ← A – sfr – CY
×
×
×
V
×
saddr, saddr
3
(saddr), CY ← (saddr) – (saddr) – CY
×
×
×
V
×
A, mem
2-4 A, CY ← A – (mem) – CY
×
×
×
V
×
mem, A
2-4 (mem), CY ← (mem) – A – CY
×
×
×
V
×
A, #byte
2
A ← A ∧ byte
×
×
P
saddr, #byte
3
(saddr) ← (saddr) ∧ byte
×
×
P
sfr, #byte
4
sfr ← sfr ∧ byte
×
×
P
r, r1
2
r ← r ∧ r1
×
×
P
A, saddr
2
A ← A ∧ (saddr)
×
×
P
A, sfr
3
A ← A ∧ sfr
×
×
P
saddr, saddr
3
(saddr) ← (saddr) ∧ (saddr)
×
×
P
A, mem
2-4 A ← A ∧ (mem)
×
×
P
mem, A
2-4 (mem) ← (mem) ∧ A
×
×
P
OR
8-bit opration
Operand
Mnemonic
XOR
CMP
Flags
Bytes
Instruction
Group
µPD78323, 78324
Operation
S
Z
AC P/V CY
A, #byte
2
A ← A ∨ byte
×
×
P
saddr, #byte
3
(saddr) ← (saddr) ∨ byte
×
×
P
sfr, #byte
4
sfr ← sfr ∨ byte
×
×
P
r, r1
2
r ← r ∨ r1
×
×
P
A, saddr
2
A ← A ∨ (saddr)
×
×
P
A, sfr
3
A ← A ∨ sfr
×
×
P
saddr, saddr
3
(saddr) ← (saddr) ∨ (saddr)
×
×
P
A, mem
2-4 A ← A ∨ (mem)
×
×
P
mem, A
2-4 (mem) ← (mem) ∨ A
×
×
P
A, #byte
2
A ← A ∨ byte
×
×
P
saddr, #byte
3
(saddr) ← (saddr) ∨ byte
×
×
P
sfr, #byte
4
sfr ← sfr ∨ byte
×
×
P
r, r1
2
r ← r ∨ r1
×
×
P
A, saddr
2
A ← A ∨ (saddr)
×
×
P
A, sfr
3
A ← A ∨ sfr
×
×
P
saddr, saddr
3
(saddr) ← (saddr) ∨ (saddr)
×
×
P
A, mem
2-4 A ← A ∨ (mem)
×
×
P
mem, A
2-4 (mem) ← (mem) ∨ A
×
×
P
A, #byte
2
A – byte
×
×
×
V
×
saddr, #byte
3
(saddr) – byte
×
×
×
V
×
sfr, #byte
4
sfr – byte
×
×
×
V
×
r, r1
2
r – r1
×
×
×
V
×
A, saddr
2
A – (saddr)
×
×
×
V
×
A, sfr
3
A – sfr
×
×
×
V
×
saddr, saddr
3
(saddr) – (saddr)
×
×
×
V
×
A, mem
2-4 A – (mem)
×
×
×
V
×
mem, A
2-4 (mem) – A
×
×
×
V
×
53
16-bit opration
ADDW
SUBW
Signed
multiplication
Multiplication/division
CMPW
54
Operand
Mnemonic
Flags
Bytes
Instruction
Group
µPD78323, 78324
Operation
S
Z
AC P/V CY
AX, #word
3
AX, CY ← AX + word
×
×
×
V
×
saddrp, #word
4
(saddrp), CY ← (saddrp) + word
×
×
×
V
×
sfrp, #word
5
sfrp, CY ← sfrp + word
×
×
×
V
×
rp, rp1
2
rp, CY ← rp + rp1
×
×
×
V
×
AX, saddrp
2
AX, CY ← AX + (saddrp)
×
×
×
V
×
AX, sfrp
3
AX, CY ← AX + sfrp
×
×
×
V
×
saddrp, saddrp
3
(saddrp), CY ← (saddrp) + (saddrp)
×
×
×
V
×
AX, #word
3
AX, CY ← AX – word
×
×
×
V
×
saddrp, #word
4
(saddrp), CY ← (saddrp) – word
×
×
×
V
×
sfrp, #word
5
sfrp, CY ← sfrp – word
×
×
×
V
×
rp, rp1
2
rp, CY ← rp – rp1
×
×
×
V
×
AX, saddrp
2
AX, CY ← AX – (saddrp)
×
×
×
V
×
AX, sfrp
3
AX, CY ← AX – sfrp
×
×
×
V
×
saddrp, saddrp
3
(saddrp), CY ← (saddrp) – (saddrp)
×
×
×
V
×
AX, #word
3
AX – word
×
×
×
V
×
saddrp, #word
4
(saddrp) – word
×
×
×
V
×
sfrp, #word
5
sfrp – word
×
×
×
V
×
rp, rp1
2
rp – rp1
×
×
×
V
×
AX, saddrp
2
AX – (saddrp)
×
×
×
V
×
AX, sfrp
3
AX – sfrp
×
×
×
V
×
saddrp, saddrp
3
(saddrp) – (saddrp)
×
×
×
V
×
MULU
r1
2
AX ← A × r1
DIVUM
r1
2
AX(quotient), r1(remainder) ← AX ÷ r1
MULUW
rp1
2
DIVUX
rp1
2
MULW
rp1
2
AX(higher 16 bits), rp1(lower 16 bits)
← AX × rp1
AXDE(quotient), rp1(remainder) ← AXDE
÷ rp1
AX(higher 16 bits), rp1(lower 16 bits)
← AX × rp1
Increase/decrease
Flags
Operation
S
Z
AC P/V CY
r1
1
r1 ← r1 + 1
×
×
×
V
saddr
2
(saddr) ← (saddr) + 1
×
×
×
V
r1
1
r1 ← r1 – 1
×
×
×
V
saddr
2
(saddr) ← (saddr) – 1
×
×
×
V
rp2
1
rp2 ← rp2 + 1
saddrp
3
(saddrp) ← (saddrp) + 1
rp2
1
rp2 ← rp2 – 1
saddrp
3
(saddrp) ← (saddrp) – 1
ROR
r1, n
2
(CY, r17 ← r10, r1m–1 ← r1m) × n times
P
×
ROL
r1, n
2
(CY, r10 ← r17, r1m+1 ← r1m) × n times
P
×
RORC
r1, n
2
(CY ← r10, r17 ← CY, r1m–1 ← r1m) × n times
P
×
ROLC
r1, n
2
(CY ← r17, r10 ← CY, r1m+1 ← r1m) × n times
P
×
SHR
r1, n
2
(CY ← r10, r17 ← 0, r1m–1 ← r1m) × n times
×
×
0
P
×
SHL
r1, n
2
(CY ← r17, r10 ← 0, r1m+1 ← r1m) × n times
×
×
0
P
×
SHRW
rp1, n
2
(CY← rp10, rp115← 0, rp1m–1← rp1m) × n times
×
×
0
P
×
SHLW
rp1, n
2
(CY← rp115, rp10← 0, rp1m+1← rp1m) × n times
×
×
0
P
×
×
×
×
P
×
INC
DEC
INCW
DECW
Shift-rotate
Operand
Mnemonic
Bytes
Instruction
Group
µPD78323, 78324
A3–0 ← (rp1)3–0,
ROR4
[rp1]
2
(rp1)7–4 ← A3–0,
(rp1)3–0 ← (rp1)7–4
A3–0 ← (rp1)7–4,
ROL4
[rp1]
2
(rp1)3–0 ← A3–0,
Data
conversion
BCD
calibration
(rp1)7–4 ← (rp1)3–0
ADJBA
2
Decimal Adjust Accumulator
ADJBS
CVTBW
1
When A7 = 0, X ← A, A ← 00H
When A7 = 1, X ← A, A ← FFH
55
Mnemonic
Operand
Bit manipulation
S
Z
AC P/V CY
3
CY ← (saddr.bit)
×
CY, sfr. bit
3
CY ← sfr.bit
×
CY, A. bit
2
CY ← A.bit
×
CY, X. bit
2
CY ← X.bit
×
CY, PSWH. bit
2
CY ← PSWH.bit
×
CY, PSWL. bit
2
CY ← PSWL.bit
×
saddr. bit, CY
3
(saddr.bit) ← CY
sfr. bit, CY
3
sfr.bit ← CY
A. bit, CY
2
A.bit ← CY
X. bit, CY
2
X.bit ← CY
PSWH. bit, CY
2
PSWH.bit ← CY
PSWL. bit, CY
2
PSWL.bit ← CY
CY, saddr. bit
3
CY ← CY ∧ (saddr.bit)
×
CY, /saddr. bit
3
CY ← CY ∧ (saddr.bit)
×
CY, sfr. bit
3
CY ← CY ∧ sfr.bit
×
CY, /sfr. bit
3
CY ← CY ∧ sfr.bit
×
CY, A. bit
2
CY ← CY ∧ A.bit
×
CY, /A. bit
2
CY ← CY ∧ A.bit
×
CY, X. bit
2
CY ← CY ∧ X.bit
×
CY, /X. bit
2
CY ← CY ∧ X.bit
×
CY, PSWH. bit
2
CY ← CY ∧ PSWH.bit
×
CY, /PSWH. bit
2
CY ← CY ∧ PSWH.bit
×
CY, PSWL. bit
2
CY ← CY ∧ PSWL.bit
×
CY, /PSWL. bit
2
CY ← CY ∧ PSWL.bit
×
CY, saddr. bit
3
CY ← CY ∨ (saddr.bit)
×
CY, /saddr. bit
3
CY ← CY ∨ (saddr.bit)
×
CY, sfr. bit
3
CY ← CY ∨ sfr.bit
×
CY, /sfr. bit
3
CY ← CY ∨ sfr.bit
×
CY, A. bit
2
CY ← CY ∨ A.bit
×
CY, /A. bit
2
CY ← CY ∨ A.bit
×
CY, X. bit
2
CY ← CY ∨ X.bit
×
CY, /X. bit
2
CY ← CY ∨ X.bit
×
CY, PSWH. bit
2
CY ← CY ∨ PSWH.bit
×
CY, /PSWH. bit
2
CY ← CY ∨ PSWH.bit
×
CY, PSWL. bit
2
CY ← CY ∨ PSWL.bit
×
CY, /PSWL. bit
2
CY ← CY ∨ PSWL.bit
×
OR1
56
Operation
CY, saddr. bit
MOV1
AND1
Flags
Bytes
Instruction
Group
µPD78323, 78324
Flags
Operation
S
Z
AC P/V CY
CY, saddr. bit
3
CY ← CY ∨ (saddr.bit)
×
CY, sfr. bit
3
CY ← CY ∨ sfr.bit
×
CY, A. bit
2
CY ← CY ∨ A.bit
×
CY, X. bit
2
CY ← CY ∨ X.bit
×
CY, PSWH. bit
2
CY ← CY ∨ PSWH.bit
×
CY, PSWL. bit
2
CY ← CY ∨ PSWL.bit
×
saddr. bit
2
(saddr.bit) ← 1
sfr. bit
3
sfr.bit ← 1
A. bit
2
A.bit ← 1
X. bit
2
X.bit ← 1
PSWH. bit
2
PSWH.bit ← 1
PSWL. bit
2
PSWL.bit ← 1
saddr. bit
2
(saddr.bit) ← 0
sfr. bit
3
sfr.bit ← 0
A. bit
2
A.bit ← 0
X. bit
2
X.bit ← 0
PSWH. bit
2
PSWH.bit ← 0
PSWL. bit
2
PSWL.bit ← 0
saddr. bit
3
(saddr.bit) ← (saddr.bit)
sfr. bit
3
sfr.bit ← sfr.bit
A. bit
2
A.bit ← A.bit
X. bit
2
X.bit ← X.bit
PSWH. bit
2
PSWH.bit ← PSWH.bit
PSWL. bit
2
PSWL.bit ← PSWL.bit
SET1
CY
1
CY ← 1
1
CLR1
CY
1
CY ← 0
0
NOT1
CY
1
CY ← CY
×
XOR1
SET1
Bit manipulation
Operand
Mnemonic
Bytes
Instruction
Group
µPD78323, 78324
CLR1
NOT1
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
57
Call-return
Operand
Mnemonic
Z
AC P/V CY
3
(SP–1) ← (PC+3)H, (SP–2) ← (PC+3)L,
PC ← addr16, SP ← SP–2
CALLF
!addr11
2
(SP–1) ← (PC+2)H, (SP–2) ← (PC+2)L,
PC15–11←00001, PC10–0←addr11,SP←SP–2
CALLT
[addr5]
1
(SP–1) ← (PC+1)H, (SP–2) ← (PC+1)L,
PCH←(TPF, 00000000, addr5+1),
PCL←(TPF, 00000000, addr5), SP←SP–2
rp1
2
(SP–1) ← (PC+2)H, (SP–2) ← (PC+2)L,
PCH ← rp1H, PCL← rp1L, SP ← SP–2
[rp1]
2
(SP–1) ← (PC+2)H, (SP–2) ← (PC+2)L,
PCH ← (rp1+1), PCL← (rp1), SP ← SP–2
BRK
1
(SP–1) ← PSWH, (SP–2) ← PSWL
(SP–3) ← (PC+1)H, (SP–4) ← (PC+1)L,
PCL ← (003EH), PCH← (003FH), SP← SP–4
IE ← 0
RET
1
PCL ← (SP), PCH← (SP+1), SP← SP+2
RETB
1
PCL ← (SP), PCH← (SP+1)
PSWL ← (SP+2), PSWH ← (SP+3)
SP ← SP+4
R
R
R
R
R
RETI
1
PCL ← (SP), PCH← (SP+1)
PSWL ← (SP+2), PSWH ← (SP+3)
SP ← SP+4
R
R
R
R
R
sfrp
3
(SP–1) ← sfrH
(SP–2) ← sfrL
SP ← SP–2
post
2
{(SP–1)←postH, (SP–2) ← postL,SP←SP–2}
× n timesNote
PSW
1
(SP–1)←PSWH, (SP–2)←PSWL, SP←SP–2
post
2
{(UP–1)←postH, (UP–2)←postL, UP←UP–2}
× n timesNote
sfrp
3
sfrL ← (SP)
sfrH ← (SP+1)
SP ← SP+2
post
2
{postL← (SP), postH ← (SP+1), SP←SP+2}
× n timesNote
PSW
1
PSWL←(SP), PSWH←(SP+1), SP←SP+2
R
R
R
R
R
post
2
{postL← (UP), postH ← (UP+1), UP←UP+2}
× n timesNote
SP, #word
4
SP← word
SP, AX
2
SP← AX
AX, SP
2
AX ←SP
INCW
SP
2
SP ← SP+1
DECW
SP
2
SP ← SP–1
CHKL
sfr
3
(pin level) ∨ (signal level before output
buffer)
×
×
P
CHKLA
sfr
3
A ← (pin level) ∨ (signal level before output
buffer)
×
×
P
CALL
POP
POPU
MOVW
Note n indicates the number of registers described as post.
58
S
!addr16
PUSHU
Stack manipulation
Operation
CALL
PUSH
Special
Flags
Bytes
Instruction
Group
µPD78323, 78324
Unconditional
branch
Operand
Mnemonic
Flags
Bytes
Instruction
Group
µPD78323, 78324
Operation
S
!addr16
3
PC ← addr16
rp1
2
PCH ← rp1H, PCL ← rp1L
[rp1]
2
PCH ← (rp1+1), PCL ← (rp1)
$ addr16
2
PC ← PC+2+jdisp8
$ addr16
2
PC ← PC+2+jdisp8 if CY=1
$ addr16
2
PC ← PC+2+jdisp8 if CY=0
$ addr16
2
PC ← PC+2+jdisp8 if Z=1
$ addr16
2
PC ← PC+2+jdisp8 if Z=0
$ addr16
2
PC ← PC+2+jdisp8 if P/V=1
$ addr16
2
PC ← PC+2+jdisp8 if P/V=0
BN
$ addr16
2
PC ← PC+2+jdisp8 if S=1
BP
$ addr16
2
PC ← PC+2+jdisp8 if S=0
BGT
$ addr16
3
PC ← PC+3+jdisp8 if (P/V ∨ S) ∨ Z=0
BGE
$ addr16
3
PC ← PC+3+jdisp8 if P/V ∨ S=0
BLT
$ addr16
3
PC ← PC+3+jdisp8 if P/V ∨ S=1
BLE
$ addr16
3
PC ← PC+3+jdisp8 if (P/V ∨ S) ∨ Z=1
BH
$ addr16
3
PC ← PC+3+jdisp8 if Z ∨ CY=0
BNH
$ addr16
3
PC ← PC+3+jdisp8 if Z ∨ CY=1
saddr. bit, $ addr16
3
PC ← PC+3+jdisp8 if (saddr.bit)=1
sfr. bit, $ addr16
4
PC ← PC+4+jdisp8 if sfr.bit=1
A. bit, $ addr16
3
PC ← PC+3+jdisp8 if A.bit=1
X. bit, $ addr16
3
PC ← PC+3+jdisp8 if X.bit=1
PSWH. bit, $ addr16
3
PC ← PC+3+jdisp8 if PSWH.bit=1
PSWL. bit, $ addr16
3
PC ← PC+3+jdisp8 if PSWL.bit=1
saddr. bit, $ addr16
4
PC ← PC+4+jdisp8 if (saddr.bit)=0
sfr. bit, $ addr16
4
PC ← PC+4+jdisp8 if sfr.bit=0
A. bit, $ addr16
3
PC ← PC+3+jdisp8 if A.bit=0
X. bit, $ addr16
3
PC ← PC+3+jdisp8 if X.bit=0
PSWH. bit, $ addr16
3
PC ← PC+3+jdisp8 if PSWH.bit=0
PSWL. bit, $ addr16
3
PC ← PC+3+jdisp8 if PSWL.bit=0
BR
BC
Z
AC P/V CY
BL
BNC
BNL
BZ
BE
BNZ
BNE
BV
BPE
BNV
Conditional branch
BPO
BT
BF
59
Operand
Mnemonic
saddr.bit, $ addr16
sfr.bit, $ addr16
Flags
Bytes
Instruction
Group
µPD78323, 78324
Operation
S
Z
AC P/V CY
×
×
×
×
×
×
×
×
×
×
R
R
R
R
R
R
R
R
R
R
PC ← PC+4+jdisp8 if (saddr.bit)=1
4
then reset (saddr.bit)
PC ← PC+4+jdisp8 if sfr.bit=1
4
then reset sfr.bit
A.bit, $ addr16
PC ← PC+3+jdisp8 if A.bit=1
3
then reset A.bit
BTCLR
PC ← PC+3+jdisp8 if X.bit=1
X.bit, $ addr16
3
then reset X.bit
PC ← PC+3+jdisp8 if PSWH.bit=1
PSWH.bit, $ addr16
3
then reset PSWH.bit
PC ← PC+3+jdisp8 if PSWL.bit=1
PSWL.bit, $ addr16
3
Conditional branch
then reset PSWL.bit
PC ← PC+4+jdisp8 if (saddr.bit)=0
saddr.bit, $ addr16
4
then set (saddr.bit)
PC ← PC+4+jdisp8 if sfr.bit=0
sfr.bit, $ addr16
4
then set sfr.bit
PC ← PC+3+jdisp8 if A.bit=0
A.bit, $ addr16
3
then set A.bit
BFSET
X.bit, $ addr16
PC ← PC+3+jdisp8 if X.bit=0
3
then set X.bit
PC ← PC+3+jdisp8 if PSWH.bit=0
PSWH.bit, $ addr16
3
then set PSWH.bit
PC ← PC+3+jdisp8 if PSWL.bit=0
PSWL.bit, $ addr16
3
then set PSWL.bit
r2 ← r2–1,
r2, $ addr16
2
saddr, $ addr16
3
RBn
2
Context switching
DBNZ
60
BRKCS
then PC ← PC+2+jdisp8 if r2≠0
(saddr) ← (saddr)–1,
then PC ← PC+3+jdisp8 if (saddr) ≠0
PCH ↔ R5, PCL ↔ R4, R7 ← PSWH,
R6←PSWL, RBS2–0← n, RSS←0, IE←0
PCH ← R5, PCL ← R4, R5, R4 ← addr16,
RETCS
!addr16
3
RETCSB
!addr16
4
PSWH ← R7, PSWL ← R6
PCH ← R5, PCL ← R4, R5, R4 ← addr16,
PSWH ← R7, PSWL ← R6
Mnemonic
Operand
[DE + ], A
Operation
S
Z
AC P/V CY
×
×
×
V
×
×
×
×
V
×
×
×
×
V
×
×
×
×
V
×
×
×
×
V
×
×
×
×
V
×
×
×
×
V
×
×
×
×
V
×
×
×
×
V
×
×
×
×
V
×
(DE + ) ← A, C ← C–1
2
MOVM
[DE – ], A
Flags
Bytes
Instruction
Group
µPD78323, 78324
End if C=0
(DE – ) ← A, C ← C–1
2
End if C=0
[DE + ], [HL + ]
(DE + ) ← (HL + ), C ← C–1
2
End if C=0
MOVBK
(DE – ) ← (HL – ), C ← C–1
[DE – ], [HL – ]
2
End if C=0
(DE + ) ↔ A, C ← C–1
[DE + ], A
2
End if C=0
XCHM
(DE – ) ↔ A, C ← C–1
[DE – ], A
2
End if C=0
(DE + ) ↔ (HL + ), C ← C–1
[DE + ], [HL + ]
2
End if C=0
XCHBK
(DE – ) ↔ (HL – ), C ← C–1
[DE – ], [HL – ]
2
End if C=0
(DE + ) – A, C ← C–1
String
[DE + ], A
2
End if C=0 or Z=0
CMPME
[DE – ], A
(DE – ) – A, C ← C–1
2
End if C=0 or Z=0
(DE + ) – (HL + ), C ← C–1
[DE + ], [HL + ]
2
End if C=0 or Z=0
CMPBKE
(DE – ) – (HL – ), C ← C–1
[DE – ], [HL – ]
2
End if C=0 or Z=0
(DE + ) – A, C ← C–1
[DE + ], A
2
End if C=0 or Z=1
CMPMNE
(DE – ) – A, C ← C–1
[DE – ], A
2
End if C=0 or Z=1
(DE + ) – (HL + ), C ← C–1
[DE + ], [HL + ]
2
End if C=0 or Z=1
CMPBKNE
[DE – ], [HL – ]
(DE – ) – (HL – ), C ← C–1
2
End if C=0 or Z=1
(DE + ) – A, C ← C–1
[DE + ], A
2
End if C=0 or CY=0
CMPMC
(DE – ) – A, C ← C–1
[DE – ], A
2
End if C=0 or CY=0
61
Operand
Mnemonic
[DE + ], [HL + ]
Operation
(DE + ) – (HL + ), C ← C–1
2
CMPBKC
[DE – ], [HL – ]
Flags
Bytes
Instruction
Group
µPD78323, 78324
S
Z
AC P/V CY
×
×
×
V
×
×
×
×
V
×
×
×
×
V
×
×
×
×
V
×
×
×
×
V
×
×
×
×
V
×
End if C=0 or CY=0
(DE – ) – (HL – ), C ← C–1
2
End if C=0 or CY=0
String
[DE + ], A
(DE + ) – A, C ← C–1
2
End if C=0 or CY=1
CMPMNC
(DE – ) – A, C ← C–1
[DE – ], A
2
End if C=0 or CY=1
(DE + ) – (HL + ), C ← C–1
[DE + ], [HL + ]
2
End if C=0 or CY=1
CMPBKNC
(DE – ) – (HL – ), C ← C–1
[DE – ], [HL – ]
2
End if C=0 or CY=1
STBC, #byte
4
STBC ← byteNote
WDM, #byte
4
WDM ← byteNote
1
RSS ← RSS
RBn
2
RBS2 – 0 ← n, RSS ← 0
RBn, ALT
2
RBS2 – 0 ← n, RSS ← 1
NOP
1
No Operation
EI
1
IE ← 1 (Enable Interrupt)
DI
1
IE ← 0 (Disable Interrupt)
CPU control
MOV
Note
SWRS
SEL
If the operation code of STBC register and WDM register operation instructions is abnormal, an operation code
trap interrupt is generated.
Operation in the eent of trap:
(SP–1)← PSWH, (SP–2) ← PSWL,
(SP–3)← (PC–4)H, (SP–4) ← (PC–4)L,
PCL ← (003CH), PCH ← (003DH),
SP ← SP–4, IE ← 0
62
µPD78323, 78324
9. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C)
Parameter
Symbol
Test Conditions
Rating
Unit
–0.5 to + 7.0
V
–0.5 to VDD + 0.5
V
–0.5 to + 0.5
V
–0.5 to VDD + 0.5
V
–0.5 to VDD + 0.5
V
All output pins
4.0
mA
All output pins total
90
mA
All output pins
–1.0
mA
All output pins total
–20
mA
VDD
Supply voltage voltage
AVDD
AVSS
Input voltage
VI
Output voltage
VO
Output current low
Note 1
IOL
Output current high
IOH
Analog input voltage
V IAN
Note 2
AVDD > VDD
–0.5 to VDD + 0.5
VDD ≥ AVDD
–0.5 to AVDD + 0.5
AVDD > VDD
–0.5 to VDD + 0.3
VDD ≥ AVDD
–0.5 to AVDD + 0.3
V
A/D converter reference
input voltage
AV REF
Operating ambient temperature
TA
–10 to + 70
°C
Storage temperature
Tstg
–65 to + 150
°C
V
Notes 1. Except the pin described in Note 2.
2. P70/ANI0 to P77/ANI7 pins
Caution If the absoute maximum rating of any one of the parameters is exceeded even momentarily, the quality
of the product may be degraded. In other words, the product may be physically damaged if any of the
absolute maximum raings is exceeded. Be sure to use the product without exceeding these rarings.
RECOMMENDED OPERATING CONDITION
Oscillation frequency
TA
8 MHz ≤ fXX ≤ 16 MHz
–10 to +70 °C
VDD
+5.0 V ±10 %
CAPACITANCE (TA = 25 °C, VSS = VDD = 0 V)
Parameter
Symbol
Input capacitance
CI
Output capacitance
CO
I/O capacitance
CIO
Test Conditions
f=1 MHz
Unmeasured pins returned to 0 V.
MIN.
TYP.
MAX.
Unit
10
pF
20
pF
20
pF
63
µPD78323, 78324
OSCILLATOR CHARACTERISTICS (TA = –10 to +70 °C, VDD = +5 V ±10 %, VSS = 0 V)
Resonator
MIN.
MAX.
Unit
Oscillation frequency (fXX)
8
16
MHz
X1 input frequency (fX)
8
16
MHz
X1 input rise/fall time (tXR, tXF)
0
20
ns
25
80
ns
Parameter
Recommended Circuit
X2
VSS
X1
Ceramic resonator
or
crystal resonator
C1
C2
X1
X2
HCMOS
Invertor
External clock
or
X1
X2
Open
X1 input high/low level width
HCMOS
Invertor
Caution
(tWXH , tWXL)
When using the system clock oscillation circuit, wire the part encircled in the dotted line in the following
manner to avoid the influence of the wiring capacity, etc.
• Make the wiring as short as possible.
• Avoid intersecting other signal conductors. Avoid approaching lines in which very high fluctuating
currents run.
• Make sure that the grounding point of the oscillation circuit capacitor always has the same electrical
potential as VSS. Avoid grounding with a grand pattern in which very high currents run.
• Do not fetch signals from the oscillation circuit.
64
µPD78323, 78324
RECOMMENDED OSCILLATOR CONSTANT
CERAMIC RESONATOR
Manufacturer
Product Name
Frequency
[MHz]
CSA8.00MT
8.0
CSA12.0MT
12.0
Murata Mfg.
CSA14.74MXZ040
14.74
Co., Ltd.
CSA16.00MXZ040
16.0
CST8.00MTW
8.0
CST12.0MTW
12.0
CST14.74MXW0C3
17.74
CST16.00MXW0C3
16.0
Recommended Constant
C1 [pF]
C2 [pF]
30
30
15
15
On-chip
On-chip
CRYSTAL RESONATOR
Manufacturer
Product Name
HC49/U-S
Kinseki Co., Ltd.
Frequency
[MHz]
8 to 16
Recommended Constant
C1 [pF]
10
C2 [pF]
10
HC49/U
65
µPD78323, 78324
DC CHARACTERISTICS (TA = –10 to +70 °C, VDD = +5 V ±10 %, VSS = 0 V)
Parameter
Input voltage low
Symbol
Test Conditions
VIL
MIN.
TYP.
0
MAX.
Unit
0.8
V
VIH1
Note 1
2.2
VIH2
Note 2
0.8VDD
Output voltage low
VOL
IOL = 2.0 mA
Output voltage high
VOH
IOH = –400 µA
Input leakage current
ILI
0 V ≤ VI ≤ VDD
±10
µA
Output leakage current
ILO
0 V ≤ VO ≤ VDD
±10
µA
IDD1
Operating mode
40
75
mA
IDD2
HALT mode
20
45
mA
Data retention voltage
VDDDR
STOP mode
Data retention current
IDDDR
Input voltage high
V
0.45
VDD – 1.0
V
V
VDD supply current
STOP mode
2.5
V
VDDDR = 2.5 V
2
10
µA
VDDDR = 5.0 V ±10 %
10
50
µA
Notes 1. Except the pin descried in Note 2.
2. RESET, X1, X2, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2,P24/INTP3, P25/INTP4, P26/INTP5, P27/
INTP6/TI, P32/SO/SB0, P33/SI/SB1, P34/SCK pins.
66
µPD78323, 78324
AC CHARACTERISTICS (TA = –10 to +70 °C, VDD = +5 V ±10 %, VSS = 0 V)
Non-consecutive read/write operation (with general-purpose memory connected)
Parameter
Symbol
Test Conditions
MIN.
MAX.
Unit
250
ns
System clock cycle time
tCYK
125
Address setup time (vs. ASTB↓)
tSAST
32
ns
Address hold time (vs. ASTB↓)
tHSTA
32
ns
RD↓ delay time from address
tDAR
85
ns
Address float time from RD↓
tFRA
10
ns
Data input time from address
tDAID
222
ns
Data input time from RD↓
tDRID
112
ns
RD↓ delay time from ASTB↓
tDSTR
42
ns
Data hold time (vs. RD↑)
tHRID
0
ns
Address active time from RD↑
tDRA
50
ns
RD low-level width
tWRL
147
ns
ASTB high-level width
tWSTH
37
ns
WR↓ delay time from address
tDAW
85
ns
Data output time from ASTB↓
tDSTOD
102
ns
Data output time from WR↓
tDWOD
40
ns
WR↓ delay time from ASTB↓
tDSTW
42
ns
Data setup time (vs. WR↑)
tSODW
147
ns
Data hold time (vs. WR↑)
tHWOD
32
ns
ASTB↑ delay time from WR↑
tDWST
42
ns
WR low-level width
tWWL
147
ns
67
µPD78323, 78324
tCYK Dependent Bus Timing Definition
Parameter
68
MIN./MAX.
Unit
tSAST
0.5T – 30
MIN.
ns
tHSTA
0.5T – 30
MIN.
ns
MIN.
ns
tDAR
Remarks
Expression
T – 40
tDAID
(2.5 + n) T – 90
MAX.
ns
tDRID
(1.5 + n) T – 75
MAX.
ns
tDSTR
0.5T – 20
MIN.
ns
tDRA
0.5T – 12
MIN.
ns
tWRL
(1.5 + n) T – 40
MIN.
ns
tWSTH
0.5T – 25
MIN.
ns
tDAW
T – 40
MIN.
ns
tDSTOD
0.5T + 40
MAX.
ns
tDSTW
0.5T – 20
MIN.
ns
tSODW
1.5T – 40
MIN.
ns
tHWOD
0.5T – 30
MIN.
ns
tDWST
0.5T – 20
MIN.
ns
tWWL
(1.5 + n) T – 40
MIN.
ns
1.
2.
T = tCYK = 1/fCLK (fCLK is internal system clock frequency)
n indicates the number of wait cycles defined by user software.
3.
Depends on tCYK for the bus timing shown in this table only.
µPD78323, 78324
SERIAL OPERATION (TA = –10 to +70 °C, VDD = +5 V ±10 %, VSS = 0 V)
Parameter
Serial clock cycle time
Serial clock low-level width
Serial clock high-level width
Symbol
Test Conditions
MIN.
MAX.
SCK output
Internal division by 8
1
µs
SCK input
External clock
1
µs
SCK output
Internal division by 8
420
ns
SCK input
External clock
420
ns
SCK output
Internal division by 8
420
ns
SCK input
External clock
420
ns
tCYSK
tWSKL
Unit
tWSKH
SI setup time (to SCK↑)
tSRXSK
80
ns
SI hold time (from SCK↑)
tHSKRX
80
ns
SO delay time from SCK↓
tDSKTX
R = 1 kΩ, C = 100 pF
210
ns
MAX.
Unit
OTHER OPERATION (TA = –10 to +70 °C, VDD = +5 V ±10 %, VSS = 0 V)
Parameter
Symbol
Test Conditions
MIN.
NMI high/low-level width
tWNIH, tWNIL
5
µs
INTP0 high/low-level width
tWI0H, tWI0L
8T
tCYK
INTP1 high/low-level width
tWI1H, tWI1L
8T
tCYK
INTP2 high/low-evel width
tWI2H, tWI2L
8T
tCYK
NTP3 high/low-level width
tWI3H, tWI3L
8T
tCYK
NTP4 high/low-level width
tWI4H, tWI4L
8T
tCYK
INTP5 high/low-level width
tWI5H, tWI5L
8T
tCYK
INTP6 high/low-level width
tWI6H, tWI6L
8T
tCYK
RESET high/low-level width
tWRSH, tWRSL
5
µs
TI high/low-level width
tWTIH, tWTIL
8T
tCYK
In TM1 event counter mode
69
µPD78323, 78324
A/D CONVERTER CHARACTERISTICS(TA = –10 to +70 °C, VDD = +5 V ±10 %, VSS = AVSS = 0 V,
VDD – 0.5 V ≤ AVDD ≤ VDD)
Parameter
Symbol
Test Conditions
Resolution
MIN.
TYP.
10
Total error Note 1
Unit
bit
4.5 V ≤ AVREF ≤ AVDD
±0.4 %
%FSR
3.4 V ≤ AVREF ≤ AVDD
±0.7
%FSR
±1/2
LSB
Quantization error
Conversion time
tCONV
144
tCYK
Sampling time
tSAMP
24
tCYK
Zero scale error Note 1
Full scale error Note 1
Non-linear error
Note 1
Analog input voltage
Note 2
4.5 V ≤ AVREF ≤ AVDD
±1.5
±2.5
LSB
3.4 V ≤ AVREF ≤ AVDD
±1.5
±4.5
LSB
4.5 V ≤ AVREF ≤ AVDD
±1.5
±2.5
LSB
3.4 V ≤ AVREF ≤ AVDD
±1.5
±4.5
LSB
4.5 V ≤ AVREF ≤ AVDD
±1.5
±2.5
LSB
3.4 V ≤ AVREF ≤ AVDD
±1.5
±4.5
LSB
VIAN
–0.3
AVDD
V
Reference voltage
AVREF
3.4
AVDD
V
AVREF current
AIREF
1.0
3.0
mA
AVDD supply current
AIDD
2.0
6.0
mA
AVDDR = 2.5 V
2.0
10
µA
AVDDR = 5 V ±10 %
10
50
µA
A/D converter data
retention current
AIDDR
STOP mode
Notes 1. Quantization error excluded.
2. When –0.3 V ≤ VIAN ≤ 0 V, the conversion result becomes 000H.
When 0 V < VIAN < AVREF, the conversion is performed at a resolution of 10 bits.
When AVREF ≤ VIAN ≤ AVDD, the conversion result is 3FFH.
70
MAX.
µPD78323, 78324
Non-Consecutive Read Operation
tCYK
(CLK)
P50-P57
(Output)
Higher Address
Higher Address
tDAID
tSAST
P40-P47
(Input/
Output)
Hi-Z
Hi-Z
Lower Address
(Output)
Data (Input)
tWSTH
Hi-Z
Lower Address
(Output)
Hi-Z
tHRID
ASTB
(Output)
tHSTA
tFRA
RD (Output)
tDSTR
tDRID
tDRA
tDAR
tWRL
Non-Consecutive Write Operation
(CLK)
P50-P57
(Output)
Higher Address
Higher Address
tSAST
P40-P47
(Input/
Output)
Lower Address
(Output)
Lower Address
(Output)
Data (Output)
Undefined
tWSTH
tHWOD
ASTB
(Output)
tDWST
tHSTA
tDSTOD
WR (Output)
tDSTW
tSODW
tDWOD
tDAW
tWWL
71
µPD78323, 78324
Serial Operation
tCYSK
tWSKH
tWSKL
SCK
tDSKTX
SO
SI
tSRXSK
tHSKRX
Interrupt Input Timing
tWNIH
tWNIL
0.8VDD
NMI
0.8V
tWInH
INTPn
Remarks
72
n = 0 to 6
tWInL
µPD78323, 78324
Reset Input Timing
tWRSH
tWRSL
0.8VDD
RESET
0.8V
TI Pin Input Timing
tWTIH
tWTIL
TI
73
µPD78323, 78324
10. PACKAGE DRAWINGS
74 PIN PLASTIC QFP (
20)
A
F2
B
56
57
38
37
F1
Q
R
S
D
C
detail of lead end
74
19
18
1
G1
G2
H
I
M
J
M
P
K
N
L
NOTE
Each lead centerline is located within 0.20 mm (0.008 inch) of
its true position (T.P.) at maximum material condition.
ITEM
MILLIMETERS
INCHES
A
23.2±0.4
0.913 +0.017
–0.016
B
20.0±0.2
0.787 +0.009
–0.008
C
20.0±0.2
0.787 +0.009
–0.008
D
23.2±0.4
0.913 +0.017
–0.016
F1
2.0
0.079
F2
1.0
0.039
G1
2.0
0.079
G2
1.0
0.039
H
0.40±0.10
0.016 +0.004
–0.005
I
0.20
0.008
J
1.0 (T.P.)
0.039 (T.P.)
K
1.6±0.2
0.063±0.008
L
0.8±0.2
0.031 +0.009
–0.008
M
0.15 +0.10
–0.05
0.006 +0.004
–0.003
N
0.10
0.004
P
Q
3.7
0.146
R
0.1±0.1
5°±5°
0.004±0.004
5°±5°
S
4.0 MAX.
0.158 MAX.
S74GJ-100-5BJ-3
74
µPD78323, 78324
68 PIN PLASTIC QFJ (
950 mil)
A
B
C
D
F
E
H
G
U
J
68
1
I
T
Q
K
M
N
M
P
P68L-50A1-2
NOTE
Each lead centerline is located within 0.12
mm (0.005 inch) of its true position (T.P.) at
maximum material condition.
ITEM
MILLIMETERS
INCHES
A
25.2 ± 0.2
0.992 ± 0.008
B
24.20
0.953
C
24.20
0.953
D
25.2 ± 0.2
0.992 ± 0.008
E
1.94 ± 0.15
0.076+0.007
–0.006
F
0.6
0.024
G
4.4 ± 0.2
0.173+0.009
–0.008
H
2.8 ± 0.2
0.110+0.009
–0.008
I
0.9 MIN.
0.035 MIN.
J
3.4
0.134
K
1.27 (T.P.)
0.050 (T.P.)
M
0.40 ± 1.0
0.016+0.004
–0.005
N
0.12
0.005
P
23.12 ± 0.20
0.910+0.009
–0.008
Q
0.15
0.006
T
R 0.8
R 0.031
U
0.20 +0.10
–0.05
0.008+0.004
–0.002
75
µPD78323, 78324
11. RECOMMENDED SOLDERING CONDITIONS
The µPD78323 and 78324 should be soldered and mounted under the conditions recommended in the table below.
For detail of recommended soldering conditions, refer to the information document Semiconductor Device Mounting Technology Manual (IE1-1207).
For soldering methods and conditions other than those recommended below, contact our salesman.
Table 11-1. Soldering Conditions for Surface Mount Type
µPD78323GJ-5BJ
: 74-pin plastic QFP (20 × 20 mm)
µPD78324GJ-×××-5BJ : 74-pin plastic QFP (20 × 20 mm)
Soldering Method
Soldering Conditions
Recommended
Condition Symbol
Infrared reflow
Package peak temperature: 230 °C, Time: 30 sec. max. (at 210 °C or above)
Number of times: Once, Time limit: 7 daysNote (thereafter 10 hours prebaking
required at 125 °C)
IR30-107-1
VPS
Package peak temperature: 215 °C, Time: 40 sec. max. (at 200 °C or above)
Number of times: Once, Time limit: 7 daysNote (thereafter 10 hours prebaking
required at 125 °C)
VP15-107-1
Pin part heating
Pin temperature: 300 °C max, Time: 3 sec. max. (Per side of the device)
µPD78323LP
: 68-pin plastic QFJ (
µPD78324LP-××× : 68-pin plastic QFJ (
Soldering Method
Infrared reflow
VPS
Pin part heating
950 mil)
950 mil)
Soldering Conditions
Recommended
Condition Symbol
Package peak temperature: 235 °C, Time: 30 sec. max. (at 210 °C or above)
Number of times: twice or less, Time limit: 7 daysNote (thereafter 36 hours
prebaking required at 125 ˚C)
<Caution>
(1) The second reflow should be started after the temperature of the device
which would have been changed by the first reflow has returned to normal.
(2) Please avoid flux water washing after the first reflow.
IR30-367-2
Package peak temperature: 215 °C, Time: 40 sec. max. (at 200 °C or above),
Number of times: twice or less, Time limit: 7 daysNote (thereafter 36 hours
prebaking required at 125 ˚C)
<Caution>
(1) The second reflow should be started after the temperature of the device
which would have been changed by the first reflow has returned to normal.
(2) Please avoid flux water washing after the first reflow.
VP15-367-2
Pin temperature: 300 °C max., Time: 3 sec. max. (Per side of the device))
Note For the storage period after dry-pack decompression, storage conditions are max. 25 °C, 65 % RH.
Caution Use more than one soldering method should be avoided (except in the case of pin part heating).
76
APPENDIX A. LIST OF 78K/III SERIES PRODUCTS (1/2)
µPD78324
µPD78323
Basic instruction
Minimum instruction execution time
32768 × 8 bits
ROM
Internal memory
µPD78322
µPD78310A
96
250 ns (at 16 MHz operation)
500 ns (at 12 MHz operation)
16384 × 8 bits
––
––
8192 × 8 bits
640 × 8 bits
Memory space
I/O lines
µPD78312A
111
1024 × 8 bits
RAM
µPD78320
––
256 × 8 bits
64K bytes
Input
16 (including 8 analog inputs)
12 (including 4 analog inputs)
Output
––
1
I/O
Pulse unit
39
21
39
21
Real-time pulse unit
• 18/16-bit free running timer × 1
• 16-bit timer/event counter × 1
Real-time pulse unit
• 16-bit compare register × 6
• 18/16-bit free running timer × 1
• 18-bit capture register × 4
• 16-bit timer/event counter × 1
• 18-bit capture/compare register × 2
• 16-bit compare register × 6
• Real-time output port × 8
• 18-bit capture register × 4
• 18-bit capture/compare register × 2
• Real-time output port × 8
40
24
Multi-function pulse I/O unit
• 16-bit presettable up-/down-counter
×2
• 16-bit free running counter capture
function × 2
• 16-bit interval timer × 2
• High-precision PWM output × 2
• Real-time output port : 4 bits × 2
Count unit mode 4 (4-multiplication
mode) function available
Counter start function by interval timer
external trigger available
Serial communication interface
Dedicated on-chip baud rate generator
UART
...1 channel
SBI
...1 channel
3-wire serial I/O
• 8 bits (full-duplex transmission/
reception)
• Dedicated on-chip baud rate generator
• 2 transfer modes (asynchronous mode,
I/O interface mode)
A/D converter
Eight 10-bit resolution inputs
Four 8-bit resolution inputs
Interrupt
• 8 external, 14 internal (shared with external 2)
• 3-level programmable priority order
• 4 external, 13 internal
• 8-level programmable priority order
• 3 processing methods (vectored interrupt, context switching and macro service functions)
77
µPD78323, 78324
•
•
•
•
78
LIST OF 78K/III SERIES PRODUCTS (2/2)
µPD78324
Test source
Instruction set
µPD78323
µPD78322
µPD78320
µPD78312A
µPD78310A
Internal : 1
Instructions for µPD78312 and 78310 significantly increased.
Following instructions added for
µPD78312 and 78310
• MOVW rp1, !addr16 instruction
• MOVW !addr16, rp1 instruction
• On-chip watchdog timer
• Standby function (STOP/HALT)
Others
• 20-bit time base counter
• Pseudo static RAM refresh function
—
Package
• 68-pin plastic QFJ ( 950 mil)
• 74-pin plastic QFP (20 × 20 mm)
• 68-pin plastic QFJ (
950 mil)
• 74-pin plastic QFP (20 × 20 mm)
• 80-pin plastic QFP (14 × 20 mm)
•
•
•
•
64-pin
64-pin
64-pin
68-pin
plastic
plastic
plastic
plastic
shurink DIP (750 mil)
QFP (14 × 20 mm)
QUIP
QFJ ( 950 mil)
µPD78323, 78324
µPD78323, 78324
APPENDIX B. TOOLS
B.1
DEVELOPMENT TOOLS
The following development tools are available for system development using the µPD78324.
Language Processor
78K/III series relocatable assembler
(RA78K/III)
Refers to the relocatable assembler which can be used commonly for the 78K/III
series. Equipped with the macro function, the relocatable assembler is aimed at
improved development efficiency.
The assembler is also accompanied by the structured assembler which can describe
the program control structure explicitly, thus making it possible to improve the
productivity and the maintainability of the program.
Host machine
Part number
OS
PC-9800 series
78K/III series C compiler (CC78K/III)
Supply medium
3.5-inch 2HD
µS5A13RA78K3
5-inch 2HD
µS5A10RA78K3
3.5-inch 2HC
µS7B13RA78K3
5-inch 2HC
µS7B10RA78K3
µS3P16RA78K3
MS-DOSTM
IBM PC/ATTM and
its compatible
machine
PC DOSTM
HP9000 series
700TM
HP-UXTM
DAT
SPARCstationTM
SunOSTM
NEWSTM
NEWS-OSTM
Cartridge tape
(QIC-24)
µS3R15RA78K3
Refers to the C compiler which can be commonly used in the 78K/III series. This
compiler is a program converting the programs written in the C language to those
object codes which are executable by microcontrollers. When using this compiler, the
78K/III series relocatable assembler (RA78K/III) is required.
Part number
Host machine
OS
PC-9800 series
IBM PC/AT and its
compatible machine
Remark
µS3K15RA78K3
Supply medium
3.5-inch 2HD
µS5A13CC78K3
5-inch 2HD
µS5A10CC78K3
3.5-inch 2HC
µS7B13CC78K3
5-inch 2HC
µS7B10CC78K3
µS3P16CC78K3
MS-DOS
PC DOS
HP9000 series 700
HP-UX
DAT
SPARCstation
SunOS
NEWS
NEWS-OS
Cartridge tape
(QIC-24)
µS3K15CC78K3
µS3R15CC78K3
Relocatable assembler and C compiler operations are assured only on the host machine and the OS
above.
79
µPD78323, 78324
PROM Writing Tools
PG-1500
This PROM programmer allows programming, in standalone mode or via operation from a
host computer, of a singlechip microcontroller with on-chip PROM by connection of the
board provided and a separately available programmer adapter.
It can program typical 256K-bit to 4M-bit PROMs.
UNISITE
2900
PROM programmer made by Data I/O Japan Corporation.
PA-78P324GJ
PA-78P324KC
PA-78P324KD
PA-78P324LP
PROM programmer adapters for writing programs to the µPD78P324 with a general PROM
programmer such as the PG-1500.
PA-78P324GJ ... For µPD78P324GJ
PA-78P324KC ... For µPD78P324KC
PA-78P324KD ... For µPD78P324KD
PA-78P324LP ... For µPD78P324LP
Hardware
Connects PG-1500 and host machine via a serial and parallel interface, and controls the
PG-1500 on the host machine.
Host Machine
OS
Software
Remark
PG-1500 controller
MS-DOS
IBM PC/AT and its
compatible machine
PC DOS
3.5-inch 2HD
µS5A13PG1500
5-inch 2HD
µS5A10PG1500
3.5-inch 2HC
µS7B13PG1500
5-inch 2HC
µS7B10PG1500
Operation of the PG-1500 controller is guaranteed only on the host machines and operating systems
quoted above.
80
PC-9800 series
Supply Medium
Ordering Code
(Product Name)
µPD78323, 78324
Debugging Tools
IE-78327-R
IE-78320-RNote
EP-78320GJ-R
EP-78320L-R
These are the in-circuit emulators which can be used for the development and
debugging of application systems. Debugging is performed by connecting them to a
host machine. The IE-78327-R can be used commonly for both the µPD78322
subseries and the µPD78328 subseries.
The IE-78320-R can be used for the µPD78322 subseries.
These are the emulation probes for connecting the IE-78327-R or IE-78320-R to a
target system.
EP-78320GJ-R: for 74-pin plastic QFP
EP-78320L-R: for 68-pin plastic QFJ
This program is for controlling the IE-78327-R from a host machine. It can execute
commands automatically, thus enabling more efficient debugging.
Hardware
Host machine
Part number
OS
IE-78327-R
control program
(IE controller)
PC-9800 series
IBM PC/AT and its
compatible machine
Supply medium
3.5-inch 2HD
µS5A13IE78327
5-inch 2HD
µS5A10IE78327
3.5-inch 2HC
µS7B13IE78327
5-inch 2HC
µS7B10IE78327
MS-DOS
PC DOS
This program is for controlling the IE-78320-R from a host machine. It can execute
commands automatically, thus enabling more efficient debugging.
Host machine
Software
IE-78320-R
control programNote
(IE controller)
PC-9800 series
IBM PC/AT and its
compatible machine
Remarks
Part number
OS
Supply medium
3.5-inch 2HD
µS5A13IE78320
5-inch 2HD
µS5A10IE78320
5-inch 2HC
µS7B10IE78320
MS-DOS
PC DOS
1. The operation of each software is assured only on the host machine and the OS above.
2. µPD78322 subseries: µPD78320, 78322, 78P322, 78323, 78324, 78P324, 78320(A), 78320(A1),
78320(A2), 78322(A), 78322(A1), 78322(A2), 78323(A), 78323(A1), 78323(A2),
78324(A), 78324(A1), 78324(A2), 78P324(A), 78P324(A1), 78P324(A2)
µPD78328 subseries: µPD78327, 78328, 78P328, 78327(A), 78328(A)
Note
The existing product IE-78320-R is a maintenance product. If you are going to newly purchase an in-circuit
emulator, please use the alternative product IE-78327-R.
81
Development Tool Configurations
82
Host machine
RS-232-C
PC-9800 series
IBM PC/AT or its compatible machine
Emulation probes
IE-78327-R
in-circuit emulator
Software
RS-232-C
PROM
programmer
Relocatable assembler
PG-1500
(With structured assembler) controller
IE controller
PROM-incorporated products
EP-78320GJ-R
EP-78320L-R
Socket for connecting the emulation probe
and the target system Note
PG-1500
EV-9200G-74
µPD78P324GJ
µPD78P324LP
µ PD78P324KC
µ PD78P324KD
+
+
+
Socket for plastic QFJ
Programmer adapters
Target system
PA-78P324GJ
PA-78P324LP
PA-78P324KC
PA-78P324KD
The socket is supplied with the emulation probe.
Remarks 1. It is also possible to use the host machine and the PG-1500
by connecting them directly by the RS-232-C.
2. In the diagram above, representative software supply media
and 3.5-inch FDs.
µPD78323, 78324
Note
µPD78323, 78324
B.2
EVALUATION TOOLS
To evaluate the functions of the µ PD78324, the following tools are made available.
Part Number
Host Machine
EB-78320-98
PC-9800 series
EB-78320-PC
IBM PC/AT or its compatible
machine
Note
Function
By connecting to a host machine, it is possible
to evaluate the functions equipped by the
µPD78324 in a simple manner. The command
system of this product basically conforms to
that of IE-78327-R and IE-78320-R. Therefore,
it is easy to move to the development work of
application systems by IE-78327-R or IE78320-R. In addition a turbo access manager
(µPD71P301)Note can be mounted on the
board.
The turbo access manager (µPD71P301) is a maintenance product.
Cautions 1. This product is not a development tool of µPD78324 application systems.
2. This product is not equipped with the emulation function for executing the ROM incorporated
in the µPD78324.
B.3
EMBEDDED SOFTWARE
The following embedded software programs are available to perform program development and maintenance
more efficiently.
Eeal-time OS
The RX78K/III is designed to provide a multi-task environment in the field of control
application where real-time operation is required. By using this real-time OS, the
performance of the whole system can be improved by allocating CPU’s idle time to
other processings.
The RX78K/III provides the system call based on the µITRON specifications.
The RX78K/III package provides tools (configurators) for creating RX78K/III’s nucleus
and multiple information table.
Real-time OS (RX78K/III)
Host machine
Part number
OS
PC-9800 series
IBM PC/AT and its
compatible machine
Caution
Supply medium
3.5-inch 2HD
µS5A13RX78320
5-inch 2HD
µS5A10RX78320
3.5-inch 2HC
µS7B13RX78320
5-inch 2HC
µS7B10RX78320
MS-DOS
PC DOS
To purchase the operating system above, you need to fill in a purchase application form
beforehand and sign a contract allowing you to use the software.
Remark
When using the real-time OS RX78K/III, you need the assembler package RA78K/III (optional) as well.
83
µPD78323, 78324
Fuzzy Inference Development Support System
This program supports inputting/editing/evaluating (through simulation) of the fuzzy
knowledge data (fuzzy rules and membership functions).
Host machine
Part number
OS
Fuzzy knowledge data creation
tools (FE9000, FE9200)
PC-9800 series
IBM PC/AT and its
compatible machine
Supply medium
3.5-inch 2HD
µS5A13FE9000
5-inch 2HD
µS5A10FE9000
3.5-inch 2HC
µS7B13FE9200
5-inch 2HC
µS7B10FE9200
MS-DOS
PC DOS WinsowsTM
This program converts the fuzzy knowledge data obtained with fuzzy knowledge data
creation tools to an assembler source program for RA78K/III.
Host machine
Part number
OS
Supply medium
Translator (FT78K3)Note
PC-9800 series
IBM PC/AT and its
compatible machine
3.5-inch 2HD
µS5A13FT78K3
5-inch 2HD
µS5A10FT78K3
3.5-inch 2HC
µS7B13FT78K3
5-inch 2HC
µS7B10FT78K3
MS-DOS
PC DOS
This program executes fuzzy inference. Fuzzy inference is executed by being linked to
the fuzzy knowledge data converted by the translator.
Part number
Host machine
OS
Fuzzy inference module
(FI78K/III)Note
PC-9800 series
IBM PC/AT and its
compatible machine
Supply medium
3.5-inch 2HD
µS5A13FI78K3
5-inch 2HD
µS5A10FI78K3
3.5-inch 2HC
µS7B13FI78K3
5-inch 2HC
µS7B10FI78K3
MS-DOS
PC DOS
This is a support software program for evaluating and adjusting the fuzzy knowledge
data at a hardware level by using the in-circuit emulator.
Host machine
Part number
OS
Fuzzy inference debugger
(FD78K/III)
PC-9800 series
IIBM PC/AT and its
compatible machine
Note
84
Under development
Supply medium
3.5-inch 2HD
µS5A13FD78K3
5-inch 2HD
µS5A10FD78K3
3.5-inch 2HC
µS7B13FD78K3
5-inch 2HC
µS7B10FD78K3
MS-DOS
PC DOS
µPD78323, 78324
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material.
All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry.
Each unused pin should be connected to V DD or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production
process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
85
µPD78323, 78324
The export of these products from Japan is regulated by the Japanese government. The export of some or all of
these products may be prohibited without governmental license. To export or re-export some or all of these
products from a country other than Japan may also be prohibited without a license from that country. Please call
an NEC sales representative.
License not needed
:
The customer must judge the need for license :
µPD78323
µPD78324
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
“Standard“, “Special“, and “Specific“. The Specific quality grade applies only to devices developed based on
a customer designated “quality assurance program“ for a specific application. The recommended applications
of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each
device before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices in “Standard“ unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact NEC Sales Representative in advance.
Anti-radioactive design is not implemented in this product.
M4 94.11
MS-DOS and Windows are trademarks of Microsoft Corporation.
PC/AT and PC DOS are trademarks of IBM Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
SunOS is a trademark of Sun Microsystems, Inc.
NEWS and NEWS-OS are trademarks of Sony Corporation.
TRON is an abbreviation of The Realtime Operating system Nucleus.
ITRON is an abbreviation of Industrial TRON.