TI TPIC1504

TPIC1504
QUAD AND HEX POWER DMOS ARRAY
SLIS057 – OCTOBER 1996
D
D
D
D
DW PACKAGE
(TOP VIEW)
Low rDS(on):
0.25 Ω Typ (Full H-Bridge)
0.15 Ω Typ (Triple Half H-Bridge)
Pulsed Current:
6 A Per Channel (Full H-Bridge)
8 A Per Channel (Triple Half H-Bridge)
Matched Sense Transistor for Class A-B
Linear Operation
Fast Commutation Speed
OUTPUT1
GATE2C
GATE1B
GATE3B
GND
OUTPUT3
SOURCE
OUTPUT5
GND
GATE4B
GATE2B
GATE5B
description
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
GATE3A
GATE1A
GATE4A
VDD1
VDD3
OUTPUT4
VDD3
GATE5A
VDD2
GATE2A
SENSE
OUTPUT2
The TPIC1504 is a monolithic power DMOS array
11
14
that consists of ten electrically isolated N-channel
12
13
enhancement-mode power DMOS transistors,
four of which are configured as a full H-bridge and six as a triple half H-bridge. The lower stage of the full H-bridge
is provided with an integrated sense-FET to allow biasing of the bridge in class A-B operation.
The TPIC1504 is offered in a 24-pin wide-body surface-mount (DW) package and is characterized for operation
over the case temperature range of – 40°C to 125°C.
schematic
VDD1
VDD2
21
16
Q2A
Q1A
23
GATE1A
D1
D2
Q1B
3
GATE1B
13
OUTPUT2
Q4A
22
GATE4A
Q3A
24
GATE3A
15
GATE2A
1
OUTPUT1
6
OUTPUT3
Q2B
11
GATE2B
19
OUTPUT4
D3
Q4B
10
GATE4B
Q3B
4
GATE3B
Q5A
17
GATE5A
8
OUTPUT5
Q5B
12
GATE5B
14
SENSE
2
VDD3
18, 20
7
SOURCE
Q2C
GATE2C
6V
5, 9
GND
NOTES: A. Terminals 5 and 9 must be externally connected.
B. Terminals 18 and 20 must bef externally connected.
C. No output may be taken greater than 0.5 V below GND.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
TPIC1504
QUAD AND HEX POWER DMOS ARRAY
SLIS057 – OCTOBER 1996
absolute maximum ratings, TC = 25°C (unless otherwise noted)†
Supply-to-GND voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 V
Source-to-GND voltage (Q3A, Q4A, Q5A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 V
Output-to-GND voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 V
Sense-to-GND voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 V
Gate-to-source voltage range, VGS (Q1A, Q1B, Q2A, Q2B, Q3A, Q3B, Q4A, Q4B, Q5A, Q5B) . . . . . ± 20 V
Gate-to-source voltage, VGS (Q2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.7 V to 6 V
Continuous gate-to-source zener-diode current (Q2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 10 mA
Pulsed gate-to-source zener-diode current (Q2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous drain current, each output (Q1A, Q1B, Q2A, Q2B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 A
Continuous drain current, each output (Q3A, Q3B, Q4A, Q4B, Q5A, Q5B) . . . . . . . . . . . . . . . . . . . . . . . . . . 2 A
Continuous drain current (Q2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA
Continuous source-to-drain diode current (Q1A, Q1B, Q2A, Q2B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 A
Continuous source-to-drain diode current (Q3A, Q3B, Q4A, Q4B, Q5A, Q5B) . . . . . . . . . . . . . . . . . . . . . . . 2 A
Continuous source-to-drain diode current (Q2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA
Pulsed drain current, each output, Imax (Q1A, Q1B, Q2A, Q2B) (see Note 1 and Figure 24) . . . . . . . . . . 6 A
Pulsed drain current, each output, Imax (Q3A, Q3B, Q4A, Q4B, Q5A, Q5B)
(see Note 1 and Figure 25) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 A
Pulsed drain current, each output, Imax (Q2C) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Continuous total power dissipation, TC = 70°C (see Note 2 and Figures 24 and 25) . . . . . . . . . . . . . . 2.86 W
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 150°C
Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Pulse duration = 10 ms, duty cycle = 2%
2. Package mounted in intimate contact with infinite heatsink.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPIC1504
QUAD AND HEX POWER DMOS ARRAY
SLIS057 – OCTOBER 1996
electrical characteristics, Q1A, Q1B, Q2A, Q2B, TC = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ID = 250 µA,
ID = 1 mA,
See Figure 5
V(BR)DSX
Drain-to-source breakdown voltage
VGS = 0
VDS = VGS,
VGS(th)
Gate-to-source threshold voltage
VGS(th)match
Gate-to-source threshold voltage matching
V(BR)
Reverse drain-to-GND breakdown voltage
V(BR)GS
Gate-to-source threshold breakdown voltage,
Q2C
IGS = 100 µA
V(BR)SG
Source-to-gate breakdown voltage, Q2C
V(DS)on
Drain-to-source on-state voltage
ISG = 100 µA
ID = 1.5 A,
See Notes 3 and 4
VF
Forward on-state voltage, GND-to-VDD1,
GND-to-VDD2
ID = 1.5 A (D1, D2)
See Notes 3 and 4
VF(SD)
Forward on-state voltage, source-to-drain
IS = 1.5 A,
VGS = 0,
See Notes 3 and 4 and Figure 19
IDSS
Zero gate voltage drain current
Zero-gate-voltage
VDS = 16 V,,
VGS = 0
TC = 25°C
TC = 125°C
IGSSF
Forward gate current, drain short-circuited
to source
VGS = 16 V,
IGSSR
Reverse gate current, drain short-circuited
to source
Ilk
lkg
rDS(on)
DS( )
ID = 1 mA,
VDS = VGS
Drain-to-GND current = 250 µA
(D1, D2)
MIN
TYP
MAX
20
1.5
UNIT
V
1.9
2.2
V
40
mV
20
V
6
V
0.5
V
VGS = 10 V,
0.375
0.45
1.7
0.85
V
V
1.2
V
0.05
1
0.5
10
VDS = 0
10
100
nA
VSG = 0.5 V,
VDS = 0
10
100
nA
Leakage
g current,, VDD1-to-GND,, VDD2-to-GND,,
gate shorted to source
VDGND = 16 V
TC = 25°C
TC = 125°C
0.05
1
0.5
10
VGS = 10 V,
ID = 1.5 A,,
See Notes 3 and 4
and Figure 9
TC = 25°C
0.25
0.3
Static drain-to-source
drain to source on-state
on state resistance
TC = 125°C
0.4
0.475
VDS = 14 V,
ID = 750 mA,
See Notes 3 and 4 and Figure 13
gfs
Forward transconductance
Ciss
Short-circuit input capacitance, common source
Coss
Short-circuit output capacitance, common source
Crss
Short-circuit reverse transfer capacitance,
common source
αs
Sense-FET drain current ratio
µA
µA
Ω
0.8
1.2
S
99
VDS = 14 V,
f = 1 MHz,
VGS = 0,
See Figure 17
81
pF
F
59
VDS = 6 V,
ID(Q2C) = 40 µA
100
150
200
NOTES: 3. Technique should limit TJ – TC to 10°C maximum.
4. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
source-to-drain diode characteristics, Q1A, Q2A, TC = 25°C
PARAMETER
trr
Reverse-recovery time
QRR
Total diode charge
TEST CONDITIONS
IS = 750 mA,
VDS = 14 V
V,
See Figures 1 and 23
POST OFFICE BOX 655303
VGS = 0,
di/dt = 100 A/µs
A/µs,
• DALLAS, TEXAS 75265
MIN
TYP
MAX
UNIT
18
ns
13
nC
3
TPIC1504
QUAD AND HEX POWER DMOS ARRAY
SLIS057 – OCTOBER 1996
resistive-load switching characteristics, Q1A, Q1B, Q2A, Q2B, TC = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
td(on)
td(off)
Turn-on delay time
tr
tf
Rise time
Qg
Total gate charge
Qgs(th)
Threshold gate-to-source charge
Qgd
Gate-to-drain charge
LD
LS
Internal drain inductance
7
Internal source inductance
7
Rg
Internal gate resistance
MAX
UNIT
11
Turn-off delay time
VDD = 14 V,,
tdis = 10 ns,
RL = 18.7 Ω,,
See Figure 3
16
ten = 10 ns,,
ns
3
Fall time
4
VDS = 14 V, ID = 750 mA,
See Figure 4 and Figure 21
VGS = 10 V,
1.8
2.5
0.3
0.4
0.5
0.6
nC
nH
Ω
10
electrical characteristics, Q3A, Q3B, Q4A, Q4B, Q5A, Q5B, TC = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ID = 250 µA,
ID = 1 mA,
See Figure 6
V(BR)DSX
Drain-to-source breakdown voltage
VGS(th)
Gate-to-source threshold voltage
V(BR)
Reverse drain-to-GND breakdown voltage
Drain-to-GND current = 250 µA (D3)
V(DS)on
Drain-to-source on-state voltage
ID = 2 A,
VGS = 10 V,
See Notes 3 and 4
VF
Forward on-state voltage, GND-to-VDD3
VF(SD)
Forward on-state voltage, source-to-drain
IDSS
Zero gate voltage drain current
Zero-gate-voltage
VDS = 16 V,,
VGS = 0
TC = 25°C
TC = 125°C
IGSSF
Forward gate current, drain short-circuited
to source
VGS = 16 V,
IGSSR
Reverse gate current, drain short-circuited
to source
Ilk
lkg
rDS(
DS(on))
VGS = 0
VDS = VGS,
MIN
TYP
1.5
V
1.9
2.2
20
V
V
0.3
ID = 2 A (D3),
See Notes 3 and 4
IS = 2 A,
VGS = 0
See Notes 3 and 4 and Figure 20
UNIT
0.35
1.5
V
V
0.85
1.2
0.05
1
0.5
10
VDS = 0
10
100
nA
VSG = 16 V,
VDS = 0
10
100
nA
Leakage
g current,, VDD3-to-GND,,
gate shorted to source
VDGND = 16 V
TC = 25°C
TC = 125°C
0.05
1
0.5
10
TC = 25°C
0.15
0.175
Static drain-to-source
drain to source on-state
on state resistance
VGS = 10 V,
ID = 2 A,
See Notes 3
and 4 and
Figure 10
Forward transconductance
Ciss
Short-circuit input capacitance, common source
Coss
Short-circuit output capacitance, common
source
Crss
Short-circuit reverse transfer capacitance,
common source
V
µA
µA
Ω
TC = 125°C
VDS = 14 V,
ID = 1 A,
See Notes 3 and 4 and Figure 14
gfs
0.24
1
1.7
0.275
S
160
VDS = 14 V,
f = 1 MHz
MHz,
VGS = 0,
See Figure 18
220
110
NOTES: 3: Technique should limit TJ – TC to 10°C maximum.
4: These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
4
MAX
20
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• DALLAS, TEXAS 75265
pF
TPIC1504
QUAD AND HEX POWER DMOS ARRAY
SLIS057 – OCTOBER 1996
source-to-drain diode characteristics, Q3A, Q4A, Q5A, TC = 25°C
PARAMETER
trr
Reverse-recovery time
QRR
Total diode charge
TEST CONDITIONS
IS = 1 A,
VDS = 14 V
V,
See Figures 2 and 23
MIN
VGS = 0,
di/dt = 100 A/µs
A/µs,
TYP
MAX
UNIT
34
ns
30
nC
resistive-load switching characteristics, Q3A, Q3B, Q4A, Q4B, Q5A, Q5B, TC = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
td(on)
td(off)
Turn-on delay time
tr
tf
Rise time
Qg
Total gate charge
Qgs(th)
Threshold gate-to-source charge
Qgd
Gate-to-drain charge
LD
LS
Internal drain inductance
7
Internal source inductance
7
Rg
Internal gate resistance
MAX
UNIT
30
Turn-off delay time
VDD = 14 V,,
tdis = 10 ns,
RL = 14 Ω,,
See Figure 3
34
ten = 10 ns,,
ns
15
Fall time
21
VDS = 14 V
V,
ID = 1 A,
A
See Figure 4 and Figure 22
VGS = 10 V,
V
3.2
4.5
0.5
0.6
0.9
1.1
nC
nH
Ω
10
thermal resistance
PARAMETER
TEST CONDITIONS
MIN
TYP
RθJA
Junction-to-ambient thermal resistance
See Notes 5 and 8
90
RθJB
Junction-to-board thermal resistance
See Notes 6 and 8
52
RθJP
Junction-to-pin thermal resistance
See Notes 7 and 8
28
NOTES: 5.
6.
7.
8.
MAX
UNIT
°C/W
Package mounted on a FR4 printed-circuit board with no heatsink.
Package mounted on a 24 in2, 4-layer FR4 printed-circuit board.
Package mounted in intimate contact with infinite heatsink.
All outputs with equal power
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• DALLAS, TEXAS 75265
5
TPIC1504
QUAD AND HEX POWER DMOS ARRAY
SLIS057 – OCTOBER 1996
PARAMETER MEASUREMENT INFORMATION
1
Reverse di/dt = 100 A/µs
I S – Source-to-Drain Diode Current – A
0.5
0
25% of IRM†
– 0.5
Shaded Area = QRR
–1
IRM†
– 1.5
trr(SD)
–2
VDS = 14 V
VGS = 0
TJ = 25°C
Q1A and Q2A
– 2.5
–3
0
10
20
30
40
50
60
Time – ns
70
80
90
100
† IRM = maximum recovery current
Figure 1. Reverse-Recovery-Current Waveform of Source-to-Drain Diodes
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPIC1504
QUAD AND HEX POWER DMOS ARRAY
SLIS057 – OCTOBER 1996
PARAMETER MEASUREMENT INFORMATION
2
VDS = 14 V
VGS = 0
TJ = 25°C
Q3A, Q4A, and Q5A
I S – Source-to-Drain Diode Current – A
1.5
1
Reverse di/dt = 100 A/µs
0.5
0
– 0.5
–1
IRM†
Shaded Area = QRR
– 1.5
trr(SD)
–2
0
10
20
30
40
50
60
Time – ns
70
80
90
100
† IRM = maximum recovery current
Figure 2. Reverse-Recovery-Current Waveform of Source-to-Drain Diodes
VDD = 14 V
RL
Pulse Generator
ten
VDS
10 V
VGS
VGS
0V
DUT
Rgen
tdis
50 Ω
50 Ω
td(off)
td(on)
CL 30 pF
(see Note A)
tr
tf
VDD
VDS
VDS(on)
VOLTAGE WAVEFORMS
TEST CIRCUIT
NOTE A: CL includes probe and jig capacitance.
Figure 3. Resistive-Switching Test Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
TPIC1504
QUAD AND HEX POWER DMOS ARRAY
SLIS057 – OCTOBER 1996
PARAMETER MEASUREMENT INFORMATION
Current
Regulator
12-V
Battery
0.2 µF
Qg
Same Type
as DUT
50 kΩ
10 V
0.3 µF
Qgs(th)
VDD = 14 V
VDS
VGS
DUT
IG = 10 µA
0
Qgd
Gate Voltage
Time
IG CurrentSampling Resistor
ID CurrentSampling Resistor
VOLTAGE WAVEFORM
TEST CIRCUIT
Figure 4. Gate-Charge Test Circuit and Voltage Waveform
TYPICAL CHARACTERISTICS
2.5
VDS = VGS
Q1A, Q1B, Q2A, Q2B
ID = 10 mA
2
ID = 100 µA
1.5
ID = 1 mA
1
0.5
0
– 40 – 20
0
20
40
60
80 100 120 140 160
GATE-TO-SOURCE THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
VGS(th) – Gate-to-Source Threshold Voltage – V
VGS(th) – Gate-to-Source Threshold Voltage – V
GATE-TO-SOURCE THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
2.5
2
ID = 10 mA
1.5
ID = 100 µA
ID = 1 mA
1
0.5
0
– 40 – 20
TJ – Junction Temperature – °C
0
20
40
60
Figure 6
POST OFFICE BOX 655303
80 100 120 140 160
TJ – Junction Temperature – °C
Figure 5
8
VDS = VGS
Q3A, Q3B, Q4A, Q4B, Q5A, Q5B
• DALLAS, TEXAS 75265
TPIC1504
QUAD AND HEX POWER DMOS ARRAY
SLIS057 – OCTOBER 1996
TYPICAL CHARACTERISTICS
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
0.483
ID =1.5 A
Q1A, Q1B, Q2A, Q2B
r DS(on) – Static Drain-to-Source
On-State Resistance – Ω
0.414
VGS = 10 V
0.345
0.276
VGS = 15 V
0.207
VGS = 12 V
0.138
0.069
0
– 40 – 20
0
20
40
60
80
100 120 140 160
TJ – Junction Temperature – °C
Figure 7
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
0.275
On-State Resistance – Ω
r DS(on) – Static Drain-to-Source
0.248
ID = 2 A
Q3A, Q3B, Q4A, Q4B, Q5A, Q5B
0.221
VGS = 10 V
0.193
0.166
VGS = 15 V
0.138
VGS = 12 V
0.110
0.083
0.055
0.028
0
– 40 – 20
0
20
40
60
80 100 120 140 160
TJ – Junction Temperature – °C
Figure 8
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• DALLAS, TEXAS 75265
9
TPIC1504
QUAD AND HEX POWER DMOS ARRAY
SLIS057 – OCTOBER 1996
TYPICAL CHARACTERISTICS
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
DRAIN CURRENT
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
DRAIN CURRENT
1
1
TJ = 25°C
Q3A, Q3B, Q4A
Q4B, Q5A, Q5B
VGS = 10 V
VGS = 15 V
VGS = 12 V
0.1
0.01
0.01
0.1
1
ID – Drain Current – A
On-State Resistance – Ω
r DS(on) – Static Drain-to-Source
On-State Resistance – Ω
r DS(on) – Static Drain-to-Source
TJ = 25°C
Q1A, Q1B, Q2A, Q2B
VGS = 12 V
VGS = 10 V
0.1
VGS = 15 V
0.01
0.01
10
10
0.1
1
ID – Drain Current – A
Figure 10
Figure 9
DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
8
6
∆VGS = 1 V
(unless otherwise noted)
TJ = 25°C
Q1A, Q1B, Q2A, Q2B
4
∆VGS = 1 V
(unless otherwise noted)
TJ = 25°C
Q3A, Q3B, Q4A, Q4B,
Q5A, Q5B
7
I D – Drain Current – A
I D – Drain Current – A
5
100
VGS = 5 V
3
2
6
VGS = 5 V
5
4
VGS = 4 V
3
2
1
VGS = 3 V
VGS = 3 V
1
0
0
0
1
7
8
9
2
3
4
5
6
VDS – Drain-to-Source Voltage – V
10
0
1
Figure 12
Figure 11
10
7
8
9
2
3
4
5
6
VDS – Drain-to-Source Voltage – V
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• DALLAS, TEXAS 75265
10
TPIC1504
QUAD AND HEX POWER DMOS ARRAY
SLIS057 – OCTOBER 1996
TYPICAL CHARACTERISTICS
DISTRIBUTION OF
FORWARD TRANSCONDUCTANCE
DISTRIBUTION OF
FORWARD TRANSCONDUCTANCE
30
50
Total Number of Units = 100
VDS = 14 V
TJ = 25°C
ID = 750 mA
Q1A, Q1B, Q2A, Q2B
40
Percentage of Units – %
Percentage of Units – %
40
20
Total Number of Units = 100
VDS = 14 V
TJ = 25°C
ID = 1 A
Q3A, Q3B, Q4A,
Q4B, Q5A, Q5B
30
20
10
gfs – Forward Transconductance – S
1.76
1.75
1.74
1.73
1.72
1.17
1.7
1.69
1.68
0
1.195
1.19
1.185
1.18
1.175
1.17
1.165
1.16
1.155
1.15
1.145
0
1.14
10
gfs – Forward Transconductance – S
Figure 13
Figure 14
DRAIN CURRENT
vs
GATE-TO-SOURCE VOLTAGE
DRAIN CURRENT
vs
GATE-TO-SOURCE VOLTAGE
6
8
Q1A, Q1B, Q2A, Q2B
5
TJ = – 40°C
Q3A, Q3B, Q4A, Q4B,
Q5A, Q5B
7
TJ = 25°C
TJ = – 40°C
TJ = 25°C
I D – Drain Current – A
I D – Drain Current – A
6
4
TJ = 75°C
3
TJ = 125°C
2
TJ = 75°C
5
TJ = 125°C
4
TJ = 150°C
3
2
1
1
0
0
0
1
2
3
4
5
6
7
8
0
1
VGS – Gate-to-Source Voltage – V
2
3
4
5
6
7
VGS – Gate-to-Source Voltage – V
Figure 16
Figure 15
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TPIC1504
QUAD AND HEX POWER DMOS ARRAY
SLIS057 – OCTOBER 1996
TYPICAL CHARACTERISTICS
CAPACITANCE
vs
DRAIN-TO-SOURCE VOLTAGE
240
CAPACITANCE
vs
DRAIN-TO-SOURCE VOLTAGE
550
VGS = 0
f = 1 MHz
TJ = 25°C
Q1A, Q1B,
Q2A, Q2B
220
200
450
Capacitance – pF
180
Capacitance – pF
VGS = 0
f = 1 MHz
TJ = 25°C
Q3A, Q3B, Q4A,
Q4B, Q5A, Q5B
500
160
140
120
Ciss
100
400
350
300
250
Coss
200
Ciss
Coss
150
80
Crss
60
Crss
100
40
50
0
2
4
6
8
10
12
14
16
18
20
0
2
VDS – Drain-to-Source Voltage – V
SOURCE-TO-DRAIN DIODE CURRENT
vs
SOURCE-TO-DRAIN VOLTAGE
I SD – Source-to-Drain Diode Current – A
I SD – Source-to-Drain Diode Current – A
10
VGS = 0
Q1A, Q1B, Q2A, Q2B
TJ = – 40°C
TJ = 25°C
0.1
0.1
10
12
14
16
18
20
1
VSD – Source-to-Drain Voltage – V
10
VGS = 0
Q3A, Q3B, Q4A, Q4B,
Q5A, Q5B
TJ = 150°C
TJ = 25°C
TJ = – 40°C
1
0.1
0.1
Figure 19
12
8
SOURCE-TO-DRAIN DIODE CURRENT
vs
SOURCE-TO-DRAIN VOLTAGE
10
1
6
Figure 18
Figure 17
TJ = 150°C
4
VDS – Drain-to-Source Voltage – V
1
VSD – Source-to-Drain Voltage – V
Figure 20
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TPIC1504
QUAD AND HEX POWER DMOS ARRAY
SLIS057 – OCTOBER 1996
TYPICAL CHARACTERISTICS
16
14
14
12
12
10
10
VDD = 10 V
8
8
VDD = 12 V
6
6
4
4
VDD = 14 V
2
2
VDD = 12 V
0
0.25 0.5 0.75
16
ID = 1 A
TJ = 25°C
See Figure 4
Q3A, Q3B,
Q4A, Q4B,
Q5A, Q5B
12
10
14
12
10
VDD = 10 V
VDD = 14 V
8
8
VDD = 12 V
6
4
6
4
VDD = 10 V
VDD = 12 V
2
2
VDD = 14 V
0
1 1.25 1.5 1.75 2
0
0
0
2.25 2.5
0
0.5
1
1.5
2
2.5
3
3.5
Qg – Gate Charge – nC
Qg – Gate Charge – nC
Figure 21
Figure 22
4
4.5
5
REVERSE RECOVERY TIME
vs
REVERSE di/dt
60
TJ = 25°C
See Figures 1 and 2
trr – Reverse Recovery Time – ns
VDS – Drain-to-Source Voltage – V
14
16
VDS – Drain-to-Source Voltage – V
ID = 0.75 A
TJ = 25°C
Q1A, Q1B, Q2A, Q2B
See Figure 4
VGS – Gate-to-Source Voltage – V
16
DRAIN-TO-SOURCE VOLTAGE AND
GATE-TO-SOURCE VOLTAGE
vs
GATE CHARGE
VGS – Gate-to-Source Voltage – V
DRAIN-TO-SOURCE VOLTAGE AND
GATE-TO-SOURCE VOLTAGE
vs
GATE CHARGE
50
IS = 1 A
Q3A, Q4A, Q5A
40
30
20
IS = 750 mA
Q1A, Q2A
10
0
0
50
100
150
200
250
Reverse di/dt – A/µs
Figure 23
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TPIC1504
QUAD AND HEX POWER DMOS ARRAY
SLIS057 – OCTOBER 1996
THERMAL INFORMATION
MAXIMUM DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
I D – Maximum Drain Current – A
10
TC = 25°C
Q1A, Q1B,
Q2A, Q2B
500 µs†
1 ms†
10 ms¶
1
θJC§
ÁÁ
ÁÁ
θJA‡
DC Conditions
0.1
0.1
1
10
100
VDS – Drain-to-Source Voltage – V
Figure 24
MAXIMUM DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
I D – Maximum Drain Current – A
10
TC = 25°C
Q3A, Q3B,
Q4A, Q4B,
Q5A, Q5B
500 µs†
1 ms†
10 ms¶
1
ÁÁ
ÁÁ
0.1
0.1
θJC§
θJA‡
DC Conditions
1
10
VDS – Drain-to-Source Voltage – V
Figure 25
† Less than 10% duty cycle
‡ Device mounted on a 24-in2, 4-layer FR4 printed-circuit board.
§ Device mounted in intimate contact with infinite heat sink.
¶ Less than 2% duty cycle
14
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100
TPIC1504
QUAD AND HEX POWER DMOS ARRAY
SLIS057 – OCTOBER 1996
THERMAL INFORMATION
DW PACKAGE†
JUNCTION-TO-BOARD THERMAL RESISTANCE
vs
PULSE DURATION
100
DC Conditions
RθJB – Junction-to-Board Thermal Resistance – °C/W
d = 0.5
d = 0.2
10
d = 0.1
d = 0.05
d = 0.02
d = 0.01
1
Single Pulse
tc
tw
ID
0
0.1
0.0001
0.001
0.01
0.1
1
10
100
tw – Pulse Duration – s
† Device is mounted on 24-in2, 4-layer FR4 printed circuit board with no heat sink.
NOTE A: ZθB(t) = r(t) RθJB
tw = pulse duration
tc = cycle time
d = duty cycle = tw/tc
Figure 26
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