NPC SM5849BF

SM5849BF
Asynchronous Sample Rate Converter
OVERVIEW
The SM5849BF is a digital audio signal, asynchronous sample rate converter LSI. It supports 16/20/24-bit
word length input data, 16/20/24-bit word length output data, 2kHz to 100kHz input sample rate range, and
4kHz to 200kHz output sample rate range. It also features a built-in digital deemphasis filter and digital attenuator.
PINOUT
■
■
■
■
ORDERING INFORMATION
Device
Package
SM5849BF
80-pin QFP
41
45
44
43
42
46
47
48
50
49
53
52
51
56
55
54
VSS
NC
NC
NC
NC
NC
NC
NC
NC
NC
SLAVE
THRUN
RSTN
DITHN
TST2N
STATE
IISN
OWL1
OWL2
VDD
20
16
17
18
19
15
14
13
11
12
8
VSS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
MLEN/DEEM
MCK/FSI2
MDT/FSI1
MCOM
DMUTE
VDD
PACKAGE DIMENSIONS
(Unit: mm)
80-pin QFP
14 ± 0.4
12 ± 0.1
0.5
0.1
0.18 0.05
1.7max
■
0.05
0.125 0.025
1.4 ± 0.1
■
■
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
9
10
■
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
0 to 10
0.1
■
VDD
OCKSL
OCLK
VSS
LRCO
BCKO
DOUT
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VSS
4
5
6
7
■
58
57
■
60
59
■
(Top view)
2
3
■
Left/right-channel processing (stereo)
2 to 100kHz input sample rate range (fsi)
4 to 200kHz output sample rate range (fso)
0.45 to 2.2-times variable sample rate conversion
ratio (fso/fsi)
Asynchronous input and output timing (clock
inputs)
System clock inputs (input and output clocks independent)
• 256fsi or 384fsi input system clock select
• 256fso or 384fso output system clock select
Deemphasis filter
• IIR-type filter
• 44.1, 48 or 32kHz
Digital attenuator
• 11-bit data, 1025 levels
• Smooth attenuation change
• +12dB gain shift function
Direct mute function
Through mode operation
• Direct connection from input to output
Output data clocks (LRCO, BCKO)
• Slave mode: external input
• Master mode: output system clock generated
internally
Dither round-off processing
• Dither round-off ON/OFF selectable
3.3V single supply
80-pin QFP
Silicon-gate CMOS process
1
■
VDD
DI
BCKI
LRCI
VSS
ICLK
ICKSL
IFM1
IFM2
IWL1
IWL2
NC
NC
NC
NC
NC
NC
NC
NC
VSS
■
14 ± 0.4
12 ± 0.1
Functions
0.5 ± 0.2
SEIKO NPC CORPORATION —1
SM5849BF
FEATURES
Filter Characteristics and Converter Efficiency
■
■
■
■
■
24-bit internal data word length
Deemphasis filter characteristics (IIR filter)
• ±0.03dB gain deviation from ideal filter characteristics
Anti-aliasing LPF characteristics
• Output/input sample rate conversion ratio automatic filter select (6 FIR filters)
- Up converter LPF
1.0 to 2.2 times
- Down converter LPF I
0.92 times: 48.0 to 44.1kHz
- Down converter LPF II
0.73 times: 44.1 to 32.0kHz
- Down converter LPF III
0.67 times: 48.0 to 32.0kHz
- Down converter LPF IV
0.5 times: 48.0 to 24.0kHz
- Down converter LPF V
0.45 times: 48.0 to 22.1kHz
• ±0.00005dB passband ripple
• > 110dB stopband attenuation
Converter noise levels
• ≤ −110dB internal calculation (quantization)
noise
• −98dB (16-bit output), −122dB (20-bit output),
and −146dB (24-bit output) word rounding
noise
Output S/N ratio (theoretical values)
Interfaces
■
Mode
Word length
Data position
Data sequence
Right justified
MSB first
Right justified
LSB first
3
Left justified
MSB first
4
IIS
MSB first
5
Right justified
MSB first
Right justified
LSB first
7
Left justified
MSB first
8
IIS
MSB first
9
Right justified
MSB first
Right justified
LSB first
11
Left justified
MSB first
12
IIS
MSB first
1
2
16 bits
6
20 bits
10
24 bits
■
S/N ratio
Output signal
word length
Input data format
• 2s-complement, L/R alternating, serial
• IIS/non-IIS format
Output data format
• 2s-complement, MSB first, L/R alternating,
serial
• Continuous bit clock
Mode
Word length
1
16 bits
2
20 bits
16-bit input
word length
20-bit input
word length
24-bit input
word length
3
24 bits
16 bits
94.8dB
97.7dB
97.7dB
4
24 bits
20 bits
97.7dB
109.5dB
109.7dB
5
16 bits
24 bits
97.7dB
109.7dB
110dB
6
20 bits
7
24 bits
IIS selection
Data position
Normal
(non IIS)
Right justified
Left justified
IIS
APPLICATIONS
■
■
Digital audio equipment-interface sample rate
conversion (AV amplifiers, CD-R, DAT, MD and
8mm VTRs)
Commercial recording/editing equipment sample
rate conversion
SEIKO NPC CORPORATION —2
SM5849BF
BLOCK DIAGRAM
IWL1 IWL2
IFM1 IFM2
MCOM
MDT/FSI1
MCK/FSI2
BCKI
DI
Input data
interface
Deemphasis and
attenuator setup
MLEN/DEEM
Arithmetic
operations
ICLK
ICKSL
LRCI
RSTN
Input-stage
divider
Deemphasis
operation
Input timing
controller
Attenuator
Filter characteristic
select
Interpolation
filter operation
Dither
operation
DITHN
TST2N
Output operation
timing controller
Output
operation
OWL1
OWL2
Output format
controller
Output data
interface
IISN
SLAVE
OCLK
OCKSL
Output-stage
clock select
LRCI BCKI
DI
Output-stage
divider
Through mode
switching
Mute
generator
Direct mute
THRUN
DMUTE
STATE
LRCO
BCKO
DOUT
SEIKO NPC CORPORATION —3
SM5849BF
PIN DESCRIPTION
I/O1
Number
Name
Description
1
VDD
–
2
DI
Ip
Digital input signal
3
BCKI
Ip
Bit clock input
4
LRCI
Ip
Word clock input
5
VSS
–
Ground
6
ICLK
I
System clock input
7
ICKSL
Ip
System clock select. 384fs clock when HIGH, and 256fs clock when LOW.
Supply voltage
Input format select
8
9
IFM1
IFM2
Ip
Ip
IFM1
IFM2
Data position
LOW
LOW
Right justified
LOW
HIGH
Right justified1
HIGH
LOW
Left justified
HIGH
HIGH
IIS
1. Data is in LSB first sequence
Input word length select
10
11
IWL1
IWL2
Ip
Ip
IWL1
IWL2
Data length
LOW
LOW
16 bits
LOW
HIGH
24 bits
HIGH
LOW
20 bits
HIGH
HIGH
24 bits
12
NC
–
No connection (must be open)
13
NC
–
No connection (must be open)
14
NC
–
No connection
15
NC
–
No connection (must be open)
16
NC
–
No connection (must be open)
17
NC
–
No connection (must be open)
18
NC
–
No connection (must be open)
19
NC
–
No connection (must be open)
20
VSS
–
Ground
21
VDD
–
Supply voltage
22
DMUTE
Ip
Direct mute pin. Muting ON when HIGH.
23
MCOM
Ip
Microcontroller control select. Microcontroller control when HIGH.
24
MDT/FSI1
Ip
When MCON = HIGH: Microcontroller interface data input (MDT)
When MCON = LOW: Deemphasis filter fs select 1 (FSI1)
25
MCK/FSI2
Ip
When MCON = HIGH: Microcontroller interface clock (MCK)
When MCON = LOW: Deemphasis filter fs select 2 (FSI2)
26
MLEN/DEEM
Ip
When MCOM is HIGH: Microcontroller interface latch enable (MLEN)
When MCOM is LOW: Deemphasis function select (DEEM)
27
NC
–
No connection (must be open)
28
NC
–
No connection (must be open)
29
NC
–
No connection (must be open)
30
NC
–
No connection (must be open)
31
NC
–
No connection (must be open)
32
NC
–
No connection (must be open)
33
NC
–
No connection (must be open)
34
NC
–
No connection (must be open)
35
NC
–
No connection (must be open)
36
NC
–
No connection (must be open)
37
NC
–
No connection (must be open)
SEIKO NPC CORPORATION —4
SM5849BF
Number
Name
I/O1
38
NC
–
Description
No connection (must be open)
39
NC
–
No connection (must be open)
40
VSS
–
Ground
41
VDD
–
Supply voltage
Output word length select
42
43
OWL2
OWL1
Ip
Ip
OWL1
OWL2
Data length
LOW
LOW
16 bits
LOW
HIGH
24 bits
HIGH
LOW
20 bits
HIGH
HIGH
24 bits1
1. Data is in left justified sequence.
44
IISN
Ip
IIS output mode select. Normal mode when HIGH, and IIS mode when LOW.
45
STATE
O
Status output
46
TST2N
Ip
IC test mode pin 2. Test mode when LOW. Leave HIGH or open circuit for normal operation.
47
DITHN
Ip
Output dither control pin. Dither when LOW, and normal mode when HIGH.
48
RSTN
Ip
Reset input. Reset when LOW.
49
THRUN
Ip
Through mode set. Normal mode when HIGH, and through mode when LOW.
50
SLAVE
Ip
Slave mode set. Slave mode when HIGH, and master mode when LOW.
51
NC
–
No connection (must be open)
52
NC
–
No connection (must be open)
53
NC
–
No connection (must be open)
54
NC
–
No connection (must be open)
55
NC
–
No connection (must be open)
56
NC
–
No connection (must be open)
57
NC
–
No connection (must be open)
58
NC
–
No connection (must be open)
59
NC
–
No connection (must be open)
60
VSS
–
Ground
61
VDD
–
Supply voltage
62
OCKSL
Ip
Output system clock select. 384fs when HIGH, and 256fs when LOW.
63
OCLK
I
Output system clock input
64
VSS
–
Ground
65
LRCO
O
Word clock output
66
BCKO
O
Bit clock output
67
DOUT
O
Data output
68
NC
–
No connection (must be open)
69
NC
–
No connection (must be open)
70
NC
–
No connection (must be open)
71
NC
–
No connection (must be open)
72
NC
–
No connection (must be open)
73
NC
–
No connection (must be open)
74
NC
–
No connection (must be open)
75
NC
–
No connection (must be open)
76
NC
–
No connection (must be open)
77
NC
–
No connection (must be open)
78
NC
–
No connection (must be open)
79
NC
–
No connection (must be open)
80
VSS
–
Ground
1. Ip = input pin with internal pull-up resistor
SEIKO NPC CORPORATION —5
SM5849BF
SPECIFICATIONS
Absolute Maximum Ratings
VSS = 0V
Symbol
Rating1
Unit
Supply voltage range
VDD
−0.3 to 4.0
V
Input voltage range
VIN
VSS − 0.3 to VDD + 0.3
V
Storage temperature range
Tstg
−55 to 125
°C
Power dissipation
PD
400
mW
Symbol
Rating
Unit
Supply voltage range
VDD
3.0 to 3.6
V
Operating temperature range
Topr
−40 to 85
°C
Parameter
1. Ratings also apply at supply switch ON and OFF.
Recommended Operating Conditions
VSS = 0V
Parameter
DC Electrical Characteristics
VDD = 3.0 to 3.6V, VSS = 0V, Ta = −40 to 85°C
Rating
Parameter
Symbol
Condition
typ
max
–
70
100
mA
Current consumption
IDD
HIGH-level input voltage1
VIH1
2.0
–
–
V
LOW-level input voltage1
VIL1
–
–
0.8
V
HIGH-level input voltage2
VIH2
2.0
–
–
V
LOW-level input voltage2
VIL2
–
–
0.8
V
HIGH-level output voltage3
VOH
IOH = −1.0mA
VDD–0.4
–
–
V
LOW-level output voltage3
VOL
IOL = 1.0mA
–
–
0.4
V
HIGH-level input current2
IIH
VIN = VDD
–
–
1.0
µA
LOW-level input current2
IIL
VIN = 0V
–
–
90
µA
ILH
VIN = VDD
–
–
1.0
µA
ILL
VIN = 0V
–
–
1.0
µA
Input leakage current1
No output load
Unit
min
1. Pins ICLK and OCLK.
2. Pins DI, BCKI, LRCI, ICKSL, IFM1, IFM2, IWL1, IWL2, DMUTE, MCOM, MDT/FSI1, MCK/FSI2, MLEN/DEEM, OWL1, OWL2, IISN, DITHN, TST2N,
RSTN, THRUN, SLAVE, OCKSL.
3. Pins STATE, LRCO, BCKO, DOUT.
SEIKO NPC CORPORATION —6
SM5849BF
AC Electrical Characteristics
Input clock (ICLK)
Condition
Parameter
HIGH-level clock pulsewidth
LOW-level clock pulsewidth
Clock pulse cycle
Rating
Symbol
Unit
tCWH1
System clock
min
typ
max
256fsi
17.5
–
–
384fsi
11.7
–
–
256fsi
17.5
–
–
384fsi
11.7
–
–
256fsi
39.0
–
2000
384fsi
26.0
–
1300
ns
tCWL1
ns
tCY1
ns
Output clock (OCLK)
Condition
Parameter
HIGH-level clock pulsewidth
LOW-level clock pulsewidth
Clock pulse cycle
Rating
Symbol
Unit
tCWH2
System clock
min
typ
max
256fso
8.7
–
–
384fso
5.8
–
–
256fso
8.7
–
–
384fso
5.8
–
–
256fso
19.5
–
1000
384fso
13.0
–
650
ns
tCWL2
ns
tCY2
ns
ICLK and OCLK timing
ICLK
OCLK
0.5VDD
t CWH1, t CWH2
t CWL1, t CWL2
t CY1, t CY2
SEIKO NPC CORPORATION —7
SM5849BF
Serial inputs (DI, LRCI, BCKI)
Rating
Parameter
Symbol
Unit
min
typ
max
50
–
–
BCKI HIGH-level pulsewidth
tBCWH1
ns
BCKI LOW-level pulsewidth
tBCWL1
50
–
–
ns
BCKI pulse cycle
tBCY1
100
–
–
ns
DI setup time
tDS
50
–
–
ns
DI hold time
tDH
50
–
–
ns
Last BCKI rising edge to LRCI edge
tBL1
50
–
–
ns
LRCI edge to first BCKI rising edge
tLB1
50
–
–
ns
t BCY1
t BCWH1
t BCWL1
BCKI
0.5VDD
t DS
t DH
0.5VDD
DI
t BL1
t LB1
LRCI
0.5VDD
Serial inputs (LRCO, BCKO: SLAVE = HIGH)
Rating
Parameter
Symbol
Unit
min
typ
max
BCKO HIGH-level pulsewidth
tBCWH2
39
–
–
ns
BCKO LOW-level pulsewidth
tBCWL2
39
–
–
ns
BCKO pulse cycle
tBCY2
78
–
–
ns
Last BCKO rising edge to LRCO edge
tBL2
39
–
–
ns
LRCO edge to first BCKO rising edge
tLB2
39
–
–
ns
Note: BCKO clock inputs exceeding 64 fso cannot be detected, and will cause incorrect operation.
t BCY2
t BCWH2
t BCWL2
BCKO
0.5VDD
t BL2
LRCO
t LB2
0.5VDD
SEIKO NPC CORPORATION —8
SM5849BF
Microcontroller interface (MCK, MDT, MLEN)
Rating
Parameter
Symbol
Unit
min
typ
max
MCK LOW-level pulsewidth
tMCWL
50
–
–
ns
MCK HIGH-level pulsewidth
tMCWH
50
–
–
ns
MDT setup time
tMDS
50
–
–
ns
MDT hold time
tMDH
50
–
–
ns
MLEN LOW-level pulsewidth
tMLWL
50
–
–
ns
MLEN HIGH-level pulsewidth
tMLWH
50
–
–
ns
MLEN setup time
tMLS
50
–
–
ns
MLEN hold time
tMLH
50
–
–
ns
MDT
0.5VDD
t MDS
t MDH
0.5VDD
MCK
t MCWL
t MCWH
t MLS
t MLH
MLEN
0.5VDD
t MLWL
t MLWH
Reset input (RSTN)
Rating
Parameter
Symbol
Unit
min
typ
max
First HIGH-level pulsewidth after supply ON
tHRST
–
640
–
tCY
RSTN pulsewidth
tRST
64
–
–
tCY
Note: tCY is the system clock input cycle time.
tRST = approximately 3.8µs when tCY = 59ns.
VDD
RSTN
t HRST
t RST
SEIKO NPC CORPORATION —9
SM5849BF
Serial outputs (DOUT, BCKO, LRCO)
SLAVE = LOW, CL = 15pF
Rating
Parameter
Symbol
Condition
Unit
min
typ
max
LRCO pulse cycle
tLOCY
–
1/fso
–
ns
LRCO LOW-level pulsewidth
tLOWL
–
1/2fso
–
ns
LRCO HIGH-level pulsewidth
tLOWH
–
1/2fso
–
ns
OCKSL = LOW
–
1/64fso
–
BCKO pulse cycle
tBOCY
OCKSL = HIGH
–
1/48fso
–
OCKSL = LOW
–
1/128fso
–
OCKSL = HIGH
–
1/96fso
–
OCKSL = LOW
–
1/128fso
–
OCKSL = HIGH
–
1/96fso
–
tBDH1
BCKO fall to DOUT, LRCO rise
–5
–
20
ns
tBDL1
BCKO fall to DOUT, LRCO fall
–5
–
20
ns
Symbol
Condition
BCKO LOW-level pulsewidth
tBOWL
BCKO HIGH-level pulsewidth
tBOWH
BCKO to DOUT and LRCO delay time
ns
ns
ns
SLAVE = HIGH, CL = 15pF
Rating
Parameter
BCKO to DOUT delay time
Unit
min
typ
max
tBDH2
BCKO fall to DOUT rise
0
–
50
ns
tBDL2
BCKO fall to DOUT fall
0
–
50
ns
t BOCY
t BOWL
t BOWH
0.5VDD
BCKO
t BDH1, t BDL1
t BDH2, t BDL2
DOUT
0.5VDD
t BDH
t BDL
LRCO
0.5VDD
t LOWH
t LOWL
t LOCY
SEIKO NPC CORPORATION —10
SM5849BF
Filter Characteristics
Anti-aliasing filter frequency characteristic
Filter5
48 to 24kHz
Filter3
44.1 to 32kHz
Filter1
Up converter
0
Filter4
48 to 32kHz
Filter6
48 to 22.05kHz
Filter2
48 to 44.1kHz
-20
Attenuation [dB]
-40
-60
-80
-100
-120
-140
0.15 0.17 0.19 0.22 0.24 0.26 0.28
0.3 0.33 0.35
0.37 0.39 0.41 0.43 0.46
0.48
0.5
0.52
0.54 0.57 0.59
0.61 0.63
Frequency [× fsi]
Deemphasis filter frequency characteristic
0.00
-4.00
-6.00
-8.00
44.1KHz
48KHz
32KHz
-10.00
-12.00
10
20.23
40.93
82.79
167.5
338.8
685.5
1387
2805
5675
11482
23227
Frequency [Hz]
0
Phase Characteristics θ [°]
Attenuation [dB]
-2.00
32KHz
44.1KHz
48KHz
-20
-40
-60
-80
-100
-120
10
17.3
29.92
51.76
89.54
154.9
267.9
463.4
801.7
1387
2399
4150
7178
12417
21478
Frequency [Hz]
SEIKO NPC CORPORATION —11
SM5849BF
FUNCTIONAL DESCRIPTION
Input Data Interface (DI, LRCI, BCKI, IFM1, IFM2, IWL1, IWL2)
Table 1. Input data format (IFM1, IFM2, IWL1, IWL2)
Mode
IFM1
IFM2
1
LOW
LOW
2
LOW
HIGH
IWL1
IWL2
LOW
LOW
Word length
Data position
Data
sequence
Right justified
MSB first
Right justified
LSB first
16 bits
3
HIGH
LOW
Left justified
MSB first
4
HIGH
HIGH
IIS
MSB first
5
LOW
LOW
Right justified
MSB first
6
LOW
HIGH
Right justified
LSB first
HIGH
LOW
20 bits
7
HIGH
LOW
Left justified
MSB first
8
HIGH
HIGH
IIS
MSB first
9
LOW
LOW
Right justified
MSB first
10
LOW
HIGH
Right justified
LSB first
LOW or HIGH
HIGH
24 bits
11
HIGH
LOW
Left justified
MSB first
12
HIGH
HIGH
IIS
MSB first
Attenuator and Deemphasis Selection
The attenuator is set using the microcontroller interface. When the attenuator is used, deemphasis settings also
need to be set using the microcontroller interface. The microcontroller interface comprises MDT, MCK and
MLEN, and is used to transfer all input serial data.
Table 2. Attenuator and deemphasis function select
Function set method
Function
Deemphasis ON/OFF
Deemphasis frequency (fsi) select
Attenuator data set
Test mode select
External pins
(MCOM = LOW)
Microcontroller interface
(MCOM = HIGH)
DEEM
FDEEM
FSI1, FSI2
FFSI1, FFSI2
N/A (no attenuation)
11 bits (B0 to B10)
N/A (test mode 1)
FTST1, FTST2
MCON should not be switched after a power-ON reset.
When MCOM is HIGH, serial data received on MDT, MCK and MLEN sets the attenuation data and control
flag data.
When MCOM is LOW, the logic levels on FSI1, FSI2 and DEEM select the device function.
SEIKO NPC CORPORATION —12
SM5849BF
Microcontroller Interface (MCOM, MDT, MCK, MLEN)
When MCOM is HIGH, the microcontroller interface is active, comprising MDT (data), MCK (clock) and
MLEN (latch enable clock) interface pins.
Input data on MDT is synchronized to the MCK clock. Data is read into the input stage shift register on the rising edge of MCK. Accordingly, the input data should change on the falling edge of MCK. Input data enters an
internal SIPO (serial-to-parallel converter register), and then the parallel data is latched into the mode register
on the rising edge of the latch enable clock MLEN.
The mode register addressed is determined by bit D1 of the 12 data bits before MLEN goes HIGH. If this bit is
LOW, then the data is read into the attenuation data register as shown in figure 1. If this bit is HIGH, then the
data is read into the mode flag register as shown in figure 2. The function of each bit in the mode flag register is
described in table 3.
MLEN
;;;;;;;;;
;;;;;;;;;
;;;;;;;;;
;;;;;
;;;;;
;;;;;
;;;;;
;;;;;
;;;;;
1
MDT
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
MSB
"L"
;;;;;
;;;;;
;;;;;
;;;;;
;;;;;
;;;;;
12
MCK
B0
D12
LSB
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
Figure 1. Attenuation data format (D1 = LOW)
MLEN
;;;;;;;;
;;;;;;;;
;;;;;;;;
;;;;;
;;;;
;;;;;
;;;;
;;;;;
;;;;
1
12
MCK
MDT
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
"H"
"L"
"L"
"L"
"L"
FTST1
FTST2
FRATE
F12DB
FFSI1
FFSI2
FDEEM
;;;;
;;;;
;;;;
;;;;
;;;;
;;;;
Figure 2. Mode flag data format (D1 = HIGH)
SEIKO NPC CORPORATION —13
SM5849BF
Table 3. Mode flag description
Mode function select
D1
Bit
Parameter
D2 to D7
Reset
mode
Mode flag
(Not used)
D8
FRATE
D9
F12DB
LOW/HIGH
Select
IC test mode flags.
Not used for normal operation.
D2 to D7 should be set LOW.
Test mode select
LOW
HIGH
Set the input/output sample rate ratio for each
output sample
LOW
Set the input/output sample rate ratio with high
accuracy every 2048 output samples
HIGH
+12dB gain shift
LOW
No gain shift (normal operation)
Input/output rate
LOW
Attenuator
LOW
HIGH
fsi select
D10
FFSI1
Deemphasis filter fs
select 1
FFSI2
FFSI1
fsi
LOW
LOW
LOW
HIGH
HIGH
LOW
48.0kHz
HIGH
HIGH
32.0kHz
LOW
44.1kHz
D11
FFSI2
D12
FDEEM
Deemphasis filter fs
select 2
Deemphasis control
ON/OFF
HIGH
Deemphasis filter ON
LOW
Deemphasis filter OFF
LOW
LOW
Deemphasis (DEEM, FSI1, FSI2 pins or FDEEM, FFSI1, FFSI2 flags)
The digital deemphasis filter is an IIR filter with variable coefficients to faithfully reproduce the gain and phase
characteristics of analog deemphasis filters.
The filter coefficients are selected by FSI1 (or FFSI1 flag) and FSI2 (or FFSI2 flag) to correspond to the sampling frequencies fs = 44.1, 48.0 and 32.0kHz.
Table 4. Deemphasis ON/OFF
DEEM
(MCOM = LOW)
FDEEM
(MCOM = HIGH)
Table 5. Deemphasis fs select (FSI1, FSI2 pins or
FFSI1, FFSI2 flags)
Deemphasis
MCOM = LOW (MCOM = HIGH)
fs
HIGH
ON
FSI1 (FFSI1)
FSI2 (FFSI2)
LOW
OFF
LOW
LOW
HIGH
LOW
LOW
HIGH
48.0kHz
HIGH
HIGH
32.0kHz
44.1kHz
SEIKO NPC CORPORATION —14
SM5849BF
Attenuation (MDT, MCK, MLEN)
The digital attenuator coefficients are read in as serial data on the microcontroller interface. Data on MDT is
read into the internal shift register on the rising edge of MCK, and then 12 bits are latched internally on the rising edge of MLEN.
When the leading bit is 0 (D1 = LOW), the following 11 bits are read into the attenuation register and used as
an unsigned integer in MSB first format. See figure 3.
MLEN
;;;;;;;;;
;;;;;;;;;
;;;;;;;;;
;;;;;
;;;;;
;;;;;
;;;;;
;;;;;
;;;;;
1
MDT
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
MSB
"L"
;;;;;
;;;;;
;;;;;
;;;;;
;;;;;
;;;;;
12
MCK
B0
D12
LSB
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
Figure 3. Attenuation data format (microcontroller interface)
Although the attenuation data comprises 11 bits, only 1025 levels are valid as given by the following.
10
DATT =
Σ ai × 2 (10 − i)
i=0
The gain of the attenuator for values of DATT from 001H to 400H are given by the following equations. Note
that when the F12DB flag is HIGH, the gain is shifted by a fixed +12.0412dB.
Gain = 20 × log
DATT
[dB]
1024
when F12DB = LOW
= 20 × log
DATT
[dB]
256
when F12DB = HIGH
After a system reset initialization, DATT is set to 400H and the F12DB flag is LOW, corresponding to 0dB
gain. (The F12DB flag is described in table 3.)
Table 6. Attenuator settings
D1
LOW
F12DB = LOW (default)
F12DB = HIGH
Attenuation data
DATT
Gain [dB]
Linear expression
Gain [dB]
Linear expression
000H
−∞
0.0
−∞
0.0
001H
−60.206
1/1024
−48.165
1/256
↓
↓
↓
↓
↓
100H
−12.041
256/1024
0.0
256/256
↓
↓
↓
↓
↓
3FFH
−0.0085
1023/1024
12.032
1023/256
400H (to 7FFH)
0
1.0
12.041
4.0
SEIKO NPC CORPORATION —15
SM5849BF
Attenuator operation
A change in the attenuation data DATT causes the gain to change smoothly from its previous value towards the
new setting. The new attenuation data is stored in the attenuation data register and the current attenuation level is
stored in a temporary register. Consequently, if a new attenuation level is read in before the previously set level is
reached, the gain changes smoothly from the current value towards the latest setting as shown in figure 4.
The attenuation counter output changes, and hence the gain changes, by 1 step every output sample. The time
taken to reduce the gain from 0dB (or 12dB) to −∞dB is (1024/fso), which corresponds to approximately
23.2ms when fso = 44.1kHz.
Level 1
Level 5
0 dB
Level 3
Gain
Level 2
—∞
∆t
Level 4
Time
Figure 4. Attenuator operation example
Mute (DMUTE)
Direct mute
Table 7. DMUTE operation ON/OFF
DMUTE
Function
LOW
Normal data is output from the next output word (mute OFF)
HIGH
0 data is output from the next output word (mute ON)
Other mute operations
The direct mute function is also invoked at the following times.
■
■
■
■
When the reset input (RSTN) changes.
When the fs setting changes, for deemphasis, using either FSI1, FSI2 inputs or FFSI1, FFSI2 flags.1
When the ICKSL, IFM1, or IFM2 setting changes.
When the ICLK input system clock stops.
Table 8. Other mute operations
Input
Function
RSTN = LOW
0 data is output from the next output word (mute ON)
RSTN = HIGH
Normal data is output from the 3073rd output word (mute OFF)
FSI1, FSI2 input settings changed (MCOM = LOW).1
FFSI1, FFSI2 input settings changed (MCOM = HIGH).1
0 data is output from the next output word (mute ON).
Normal data is output from the 3073rd output word (mute OFF)
ICKSL, IFM1, IFM2 input settings change.
ICLK input system clock stops.
0 data is output from the next output word (mute ON)
ICLK input system clock restarts.
Normal data is output from the 3073rd output word (mute OFF)
1. Mute function does not operate when the deemphasis filter ON/OFF is switched (DEEM (MCOM = LOW), FDEEM (MCOM = HIGH)).
SEIKO NPC CORPORATION —16
SM5849BF
Internal Operating Status (STATE)
Internally, all functions are performed on 24-bit serial data, and the conversion rate and filter type are selected
accordingly. The output format is 24-bit left-justified.
Table 9. Status data description
Output bit position
1 to 20
21
Content
(Output data cycle/input data cycle) − 129
Ex.
1st
20th
00.111111111101111111 ⇒ 1.0 times
01.111111111101111111 ⇒ 2.0 times (1/2 conversion rate ratio)
00.011111111101111111 ⇒ 0.5 times (2.0 conversion rate ratio)
Not used.
Selected filter type
22
DA2
23
DA1
24
DA0
DA2
DA1
DA0
Filter type
Conversion frequency (example)
0
0
0
1
Up converter
0
0
1
2
48 to 44.1kHz
0
1
0
3
44.1 to 32kHz
0
1
1
4
48 to 32kHz
1
0
0
5
96 to 48kHz, 48 to 24kHz
1
0
1
6
96 to 44.1kHz, 48 to 22.05kHz
Note that when THRUN is LOW, LRCO and BCKO are not guaranteed to be synchronized to the STATE output.
Input System Clock (ICLK, ICKSL)
The input system clock can be set to run at either 256fsi or 384fsi, where fsi is the input frequency on LRCI.
Note that ICLK and LRCI should be divided from a common clock source or PLL to maintain synchronism.
Table 10. ICKSL and input system clock
ICKSL
ICLK system clock rate
HIGH
384fsi
LOW
256fsi
Output System Clock (OCLK, OCKSL)
The output system clock can be set to run at either 256fso or 384fso, where fso is the output frequency on
LRCO. In through mode, OCLK and OCKSL have no function and are not used.
Note that even in slave mode, a suitable clock must be input on OCLK. A malfunction prevention circuit uses
this clock so that operation continues when the ICLK stops.
Table 11. SLAVE, OCKSL and output system clock
SLAVE
OCKSL
OCLK system clock rate
HIGH
384fso
LOW
256fso
×
Not used
LOW
HIGH
SEIKO NPC CORPORATION —17
SM5849BF
Output Data Interface and Output Clock Selection (LRCO, BCKO, DOUT, SLAVE)
Table 12. Output mode description
Function
THRUN
SLAVE
Mode
Description
LRCO, BCKO state
LOW
Master mode
Output word clock (LRCO) and output bit clock
(BCKO) are divided from OCLK.
Outputs
HIGH
Slave mode
Output word clock (LRCO) and output bit clock
(BCKO) are supplied externally.
Inputs1
Through mode
Output word clock (LRCO), output bit clock (BCKO)
and output data (DOUT) are the same as LRCI,
BCKI and DI, respectively. DMUTE is valid.
Outputs
HIGH
×
LOW
1. The number of BCKO input clock cycles should not exceed 64 per word. Correct operation is not guaranteed beyond these limits.
Output Format Control (OWL1, OWL2, IISN)
The output is in MSB-first, 2s-complement, L/R alternating, bit serial format with a continuous bit clock.
Inputs
Output format
Mode
IISN
OWL2
OWL1
Word length
LOW
LOW
16 bits
LOW
HIGH
20 bits
3
HIGH
LOW
24 bits
4
HIGH
HIGH
24 bits
5
LOW
LOW
16 bits
LOW
HIGH
20 bits
HIGH
×
24 bits
1
2
HIGH
IIS selection
Data position
Normal
(non IIS)
Right justified
Left justified
6
LOW
7
IIS
Output Timing Calculation
The output timing is controlled to maintain the desired ratio between the output data cycle and the input data
cycle.
Output round-off processing
The internal processor data length and output data length are different, making output data round-off processing necessary. The SM5849BF supports selectable normal round-off processing and trigonometric function
dither round-off processing*.
*TPDF: Triangular
Probability Density Function
DITHN
Output round-off processing
HIGH
Normal round-off
LOW
Dither round-off
SEIKO NPC CORPORATION —18
SM5849BF
Filter Characteristic Selection
Conversion rates from 0.45 to 2.2 times are supported using the following 6 filter types.
The ratio between the output sample rate and input sample rate is measured automatically and the most suitable
filter type for this ratio is selected automatically.
Table 13. fs ratio and filter selection
Filter mode
fs ratio (fso/fsi)
Selects range
Conversion frequency (example)
1
1.0 to 2.2
≥ 0.969697
Up converter
2
0.91875
0.864865 to 0.969697
48.0 to 44.1kHz
3
0.72562
0.711111 to 0.864865
44.1 to 32.0kHz
4
0.66667
0.627451 to 0.711111
48 to 32kHz
5
0.50000
0.492308 to 0.627451
48 to 24kHz, 96 to 48kHz
6
0.459375
≤ 0.492308
48 to 22.05kHz, 96 to 44.1kHz
When the selected fs conversion ratio and the actual sample rate conversion ratio do not coincide, the following
phenomenon occur.
Table 14. Mismatch condition and response
Condition1
Response
Actual sample rate conversion ratio is lower than the selected filter conversion ratio
The audio band high-pass develops aliasing noise.
Actual sample rate conversion ratio is higher than the selected filter conversion ratio
The audio band high-pass is cut off.
1. An output noise may be generated if the fs conversion ratio changes at a rate greater 0.119%/sec.
System Reset (RSTN)
At power-ON, all device functions must be reset. The device is reset by applying a LOW-level pulse on RSTN.
At system reset, the internal arithmetic operation, output timing counter and internal flag register operation are
synchronized on the next LRCI rising edge. Note that all flags are set to their defaults (all LOW).
A power-ON reset signal can be applied from an external microcontroller. For systems where ICLK, BCKI,
and LRCI are stable at power ON, initialization can be performed by connecting a 0.001µF capacitor between
RSTN and VSS. Otherwise, a capacitor value should be chosen such that RSTN does not go HIGH until after
LRCI, BCKI, and ICLK have stabilized.
Through Mode (THRUN)
Table 15. Through mode function description
THRUN
Mode
Description
LOW
Through mode
Direct connections are made: LRCI to LRCO, BCKI to BCKO, and DI to DOUT. DMUTE is valid.
HIGH
Normal mode
Sample rate converter operation
Synchronizing Internal Arithmetic Timing
The clock on LRCI should pass through 1 cycle for every 384 (ICKSL = HIGH) or 256 (ICKSL = LOW) ICLK
clock cycles to maintain correct internal arithmetic sequence. If the number of ICLK cycles is different,
increases or decreases, or any jitter is present, device operation could be affected.
There is a fixed-value tolerance within which the internal sequence and LRCI clock timing are not adversely
affected.
Table 16. ICLK and clock tolerance
ICKSL
Allowable clock variation
HIGH (384fs mode)
+8 to −6 cycles
LOW (256fs mode)
+4 to −3 cycles
Whenever the allowable tolerance is exceeded, the internal sequence start-up may be delayed or fail. When this
occurs, there is a possibility that a click noise will be generated.
SEIKO NPC CORPORATION —19
SM5849BF
TIMING DIAGRAMS
Input Timing Examples (DI, BCKI, LRCI)
Audio data input timing (right-justified 16-bit word, IFM1 = L, IFM2 = L, IWL1 = L, IWL2 = L)
LRCI(fsi)
1
24 25
48
BCKI(48fsi)
MSB
DI
LSB
MSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
LSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Audio data input timing (right-justified 24-bit word, IFM1 = L, IFM2 = L, IWL1 = H, IWL2 = H)
LRCI(fsi)
1
24 25
MSB
LSBMSB
48
BCKI(48fsi)
DI
LSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Audio data input timing (left-justified 20-bit word, IFM1 = H, IFM2 = L, IWL1 = H, IWL2 = L)
LRCI(fsi)
1
24 25
48
BCKI(48fsi)
MSB
DI
LSB
MSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
LSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
All data bits after the LSB (20th bit) are ignored. Note that more than 20 BCKI cycles are required.
Audio data input timing (IIS-format 24-bit word, IFM1 = H, IFM2 = H, IWL1 = L, IWL2 = H)
LRCI(fsi)
1
32 33
64
BCKI(64fsi)
MSB
DI
LSB
MSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
LSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Audio data input timing (right-justified 24-bit word, LSB first,
IFM1 = H, IFM2 = H, IWL1 = L, IWL2 = H)
LRCI(fsi)
1
32 33
64
BCKI(64fsi)
LSB
DI
MSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
LSB
MSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SEIKO NPC CORPORATION —20
SM5849BF
Output Timing Examples (DOUT, BCKO, LRCO)
Audio data output timing (right-justified 16-bit word, IISN = H, OWL1 = L, OWL2 = L)
LRCO(fso)
1
24 25
48
BCKO(48fso)
MSB
DOUT
LSB
MSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
LSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Audio data output timing (right-justified 24-bit word, IISN = H, OWL1 = L, OWL2 = H)
LRCO(fso)
1
24 25
MSB
LSBMSB
48
BCKO(48fso)
DOUT
LSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Audio data output timing (left-justified 24-bit word, IISN = H, OWL1 = H, OWL2 = H)
LRCO(fso)
1
32 33
64
BCKO(64fso)
MSB
DOUT
LSB
MSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
LSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Audio data output timing (IIS-format 24-bit word, IISN = L, OWL1 = L, OWL2 = H)
LRCO(fso)
1
32 33
64
BCKO(64fso)
MSB
DOUT
LSB
MSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
LSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Audio data output timing (right-justified 24-bit word, IISN = H, OWL1 = L, OWL2 = H)
LRCO(fso)
1
32 33
64
BCKO(64fso)
MSB
DOUT
LSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
MSB
LSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SEIKO NPC CORPORATION —21
SM5849BF
State Data Output Timing
State data output timing
IISN = H
LRCO(fso)
1
32 33
64
BCKO(64fso)
MSB
STATE
LSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
IISN = L
LRCO(fso)
1
32 33
64
BCKO(64fso)
MSB
STATE
LSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Delay Time
tINPUT is the time when the serial input data read in is completed (on the rising edge of LRCI). tOUTPUT is the
time when the serial output data read out is completed (on the rising edge of LRCO). The delay between input
and output is given by tOUTPUT − tINPUT = (55 ± 5)/fsi.
1/fs
55 ± 5
Serial data input
t input
Serial data output
1/fso
t output
t INPUT
t OUTPUT — t INPUT
t OUTPUT
SEIKO NPC CORPORATION —22
SM5849BF
TYPICAL APPLICATIONS
Input Interface Circuit
Digital audio interface receiver (CS8414)
(256fsi)
MCK
ICLK
FSYNC
LRCI
Level Shifter
(5V to 3.3V)
SCK
BCKI
SDATA
DI
Co/F0
MLEN/DEEM
5V
DIR
CS8414
SEL
SM5849BF
ICKSL
CS12/FCK
MCOM
3.3V
M3
IFM1
M2
IFM2
M1
IWL1
M0
IWL2
Output Interface Circuit
Digital audio interface receiver (CS8404)
External Clock
24.576MHz (256fso) 3.3V
12.288MHz (128fso) 5V
OCLK
MCK
LRCO
FSYNC
Level Shifter
(3.3V to 5V)
BCKO
SCK
DOUT
SDATA
5V
PRO
SM5849BF
OCKSL
3.3V
OWL1
TRNPT/FC1
DIT
CS8404
M2
OWL2
M1
IISN
THRUN
3.3V
M0
SLAVE
SEIKO NPC CORPORATION —23
SM5849BF
APPLICATION NOTE
Delay in the slave mode
In the slave mode , the delay (tBDH2, tBDL2) of DUOT from BCKO is MIN = 0ns, MAX = 50ns which is
rather wide width.
As specified in AC Electrical Characteristics, and BCKO is prohibited from inputting longer than 64fso.
When tBDH2, tBDL2 is maximum 50ns, ideal timing may not be attained for the following devise, depending
on the OCLK cycle (example 1).
Please use considering the timing in the following examples in the slave mode.
(example 1) OCLK = 20.3ns (fs = 192kHz), OCKSL = L (256fs), BCKO (64fso) = 81.4ns, IISN = H, OWL1 = L, OWL2 = H
LRCO
BCKO
(LSB)
L2
DOUT
50ns
L1
50ns
81.4ns
(example 2) OCLK = 27.1ns (fs = 96kHz), OCKSL = H (384fs), BCKO (64fso) = 162.8ns, IISN = H, OWL1 = L, OWL2 = H
LRCO
BCKO
(LSB)
DOUT
L2
50ns
L1
50ns
162.8ns
SEIKO NPC CORPORATION —24
SM5849BF
Please pay your attention to the following points at time of using the products shown in this document.
The products shown in this document (hereinafter “Products”) are not intended to be used for the apparatus that exerts harmful influence on
human lives due to the defects, failure or malfunction of the Products. Customers are requested to obtain prior written agreement for such
use from SEIKO NPC CORPORATION (hereinafter “NPC”). Customers shall be solely responsible for, and indemnify and hold NPC free and
harmless from, any and all claims, damages, losses, expenses or lawsuits, due to such use without such agreement. NPC reserves the right
to change the specifications of the Products in order to improve the characteristic or reliability thereof. NPC makes no claim or warranty that
the contents described in this document dose not infringe any intellectual property right or other similar right owned by third parties.
Therefore, NPC shall not be responsible for such problems, even if the use is in accordance with the descriptions provided in this document.
Any descriptions including applications, circuits, and the parameters of the Products in this document are for reference to use the Products,
and shall not be guaranteed free from defect, inapplicability to the design for the mass-production products without further testing or
modification. Customers are requested not to export or re-export, directly or indirectly, the Products to any country or any entity not in
compliance with or in violation of the national export administration laws, treaties, orders and regulations. Customers are requested
appropriately take steps to obtain required permissions or approvals from appropriate government agencies.
SEIKO NPC CORPORATION
15-6, Nihombashi-kabutocho, Chuo-ku,
Tokyo 103-0026, Japan
Telephone: +81-3-6667-6601
Facsimile: +81-3-6667-6611
http://www.npc.co.jp/
Email: [email protected]
NC0030CE
2006.04
SEIKO NPC CORPORATION —25