TI TPS84620

TPS84620
9 mm × 15 mm × 2.8 mm
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SLVSA43A – OCTOBER 2010 – REVISED JANUARY 2011
4.5-V to 14.5-V Input, 6-A Synchronous Buck, Integrated Power Solution
Check for Samples: TPS84620
FEATURES
1
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Complete Integrated Power Solution Allows
Small Footprint, Low-Profile Design
Efficiencies Up To 96%
Wide-Output Voltage Adjust
1.2 V to 5.5 V, with 1% Reference Accuracy
Optional Split Power Rail allows
input voltage down to 1.7 V
Adjustable Switching Frequency
(480 kHz to 780 kHz)
Synchronizes to an External Clock
Adjustable Slow-Start
Output Voltage Sequencing / Tracking
Power Good Output
Programmable Undervoltage Lockout (UVLO)
Output Overcurrent Protection
Over Temperature Protection
Pre-bias Output Start-up
Operating Temperature Range: –40°C to 85°C
Enhanced Thermal Performance: 13°C/W
Meets EN55022 Class B Emissions
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DESCRIPTION
The TPS84620RUQ is an easy-to-use integrated
power solution that combines a 6-A DC/DC converter
with power MOSFETs, an inductor, and passives into
a low profile, BQFN package. This total power
solution allows as few as 3 external components and
eliminates the loop compensation and magnetics part
selection process.
The 9×15×2.8 mm BQFN package is easy to solder
onto a printed circuit board and allows a compact
point-of-load design with greater than 90% efficiency
and excellent power dissipation with a thermal
impedance of 13°C/W junction to ambient. The
device delivers the full 6-A rated output current at
85°C ambient temperature without airflow.
The TPS84620 offers the flexibility and the
feature-set of a discrete point-of-load design and is
ideal for powering performance DSPs and FPGAs.
Advanced packaging technology afford a robust and
reliable power solution compatible with standard QFN
mounting and testing techniques.
SIMPLIFIED APPLICATION
PVIN
PWRGD
VIN
VIN
APPLICATIONS
•
•
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Broadband & Communications Infrastructure
Automated Test and Medical Equipment
Compact PCI / PCI Express / PXI Express
DSP and FPGA Point of Load Applications
High Density Distributed Power Systems
CIN
TPS84620
RT/CLK
SENSE+
INH/UVLO
SS/TR
100
RSET
STSEL
AGND
85
Efficiency (%)
COUT
VADJ
95
90
VOUT
VOUT
PGND
80
75
70
UDG-10021
VOUT = 3.3 V
fSW = 630 kHz
65
60
PVIN = VIN = 5 V
PVIN = VIN = 12 V
55
50
0
1
2
3
4
Output Current (A)
5
6
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SwitcherPro is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2011, Texas Instruments Incorporated
TPS84620
SLVSA43A – OCTOBER 2010 – REVISED JANUARY 2011
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum at the end of this datasheet, or see
the TI website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
over operating temperature range (unless otherwise noted)
Input Voltage
VALUE
UNIT
VIN
–0.3 to 16
V
PVIN
–0.3 to 16
V
INH/UVLO
–0.3 to 6
V
BOOT
–0.3 to 27
V
VADJ
–0.3 to 3
V
COMP
–0.3 to 3
V
PWRGD
–0.3 to 6
V
SS/TR
–0.3 to 3
V
STSEL
–0.3 to 3
V
RT/CLK
–0.3 to 6
V
BOOT-PH
Output Voltage
0 to 7
V
PH
–1 to 20
V
PH 10ns Transient
–3 to 20
V
VDIFF (GND to exposed thermal pad)
–0.2 to 0.2
V
±100
µA
PH
Current Limit
A
PH
Current Limit
A
PVIN
Current Limit
A
±200
µA
RT/CLK
Source Current
Sink Current
COMP
PWRGD
–0.1 to 5
Operating Junction Temperature
–40 to 125
Storage Temperature
Mechanical Shock
Mil-STD-883D, Methed 2002.3, 1 msec, 1/2 sine, mounted
Mechanical Vibration
Mil-STD-883D, Methed 2007.2, 20-2000Hz
(1)
(2)
2
mA
(2)
°C
–65 to 150
°C
1500
G
20
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
See the temperature derating curves in the Typical Characteristics section for thermal information.
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THERMAL INFORMATION
TPS84620
THERMAL METRIC (1)
RUQ47
UNITS
47 PINS
Junction-to-ambient thermal resistance (2)
qJA
(3)
13
qJCtop
Junction-to-case (top) thermal resistance
qJB
Junction-to-board thermal resistance (4)
yJT
Junction-to-top characterization parameter (5)
yJB
Junction-to-board characterization parameter (6)
5
qJCbot
Junction-to-case (bottom) thermal resistance (7)
n/a
(1)
(2)
(3)
(4)
(5)
(6)
(7)
9
6
°C/W
2.5
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, yJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining qJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, yJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining qJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
PACKAGE SPECIFICATIONS
TPS84620
Weight
Flammability
MTBF Calculated reliability
UNIT
1.26 grams
Meets UL 94 V-O
Per Bellcore TR-332, 50% stress, TA = 40°C, ground benign
33.9 MHrs
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ELECTRICAL CHARACTERISTICS
over -40°C to 85°C free-air temperature, PVIN = VIN = 12 V, VOUT = 1.8 V, IOUT = 6A,
CIN1 = 2x 22 µF ceramic, CIN2 = 68 µF poly-tantalum, COUT1 = 4x 47 µF ceramic (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOUT
Output current
TA = 85°C, natural convection
VIN
Input bias voltage range
PVIN
Input switching voltage range
UVLO
VIN Undervoltage lockout
VOUT(adj)
VOUT
A
4.5
14.5
V
Over IOUT range
1.7 (1)
14.5
V
VIN = increasing
4.0
3.5
Output voltage adjust range
Over IOUT range
1.2
Set-point voltage tolerance
TA = 25°C, IOUT = 0A
Temperature variation
-40°C ≤ TA ≤ +85°C, IOUT = 0A
±0.3%
Line regulation
Over PVIN range, TA = 25°C, IOUT = 0A
±0.1%
Load regulation
Over IOUT range, TA = 25°C
±0.1%
Total output voltage variation
Includes set-point, line, load, and temperature variation
PVIN = VIN = 5 V
IO = 3 A
VINH-H
VINH-L
II(stby)
Inhibit Control
VOUT = 3.3V, fSW = 630kHz
90 %
VOUT = 2.5V, fSW = 530kHz
89 %
VOUT = 1.8V, fSW = 480kHz
87 %
VOUT = 1.5V, fSW = 480kHz
85 %
VOUT = 1.2V, fSW = 480kHz
83 %
VOUT = 3.3V, fSW = 630kHz
94 %
VOUT = 2.5V, fSW = 530kHz
92 %
VOUT = 1.8V, fSW = 480kHz
90 %
VOUT = 1.5V, fSW = 480kHz
88 %
VOUT = 1.2V, fSW = 480kHz
86 %
1.0 A/µs load step from 50 to 100% IOUT(max)
A
VOUT
over/undershoot
60
INH < 1.1 V
-1.15
INH > 1.26 V
-3.4
Input standby current
INH pin to AGND
VOUT falling
fCLK
Synchronization frequency
VCLK-H
CLK High-Level Threshold
VCLK-L
CLK Low-Level Threshold
DCLK
CLK Duty cycle
Thermal Shutdown
(1)
(2)
(3)
4
CLK Control
2
Good
94%
Fault
109%
Fault
91%
Good
106%
Thermal shutdown hysteresis
V
mA
mA
4
µA
0.3
V
560
kHz
480
780
kHz
2.0
5.5
V
0.8
V
400
480
20%
Thermal shutdown
(3)
1.05
INH Hysteresis current
PWRGD Thresholds
mV
Open
INH Input current
Over VIN and IOUT ranges, RT/CLK pin OPEN
mVPP
µs
–0.3
I(PWRGD) = 2 mA
(2)
80
1.30
Switching frequency
±1.5%
V
Recovery time
Inhibit Low Voltage
PWRGD Low Voltage
(2)
V
11
Inhibit High Voltage
fSW
±1.0%
30
VOUT rising
Power
Good
5.5
93 %
20 MHz bandwith
4.5
3.85
VOUT = 5V, fSW = 780kHz
Overcurrent threshold
Transient response
UNIT
Over IOUT range
VIN = decreasing
Output voltage ripple
MAX
6
Efficiency
ILIM
TYP
0
PVIN = VIN = 12 V
IO = 3 A
h
MIN
160
80%
175
°C
10
°C
The minimum PVIN voltage is 1.7V or (VOUT+ 0.5V) , whichever is greater. VIN must be greater than 4.5V.
The stated limit of the set-point voltage tolerance includes the tolerance of both the internal voltage reference and the internal
adjustment resistor. The overall output voltage tolerance will be affected by the tolerance of the external RSET resistor.
This control pin has an internal pullup to the input voltage VIN. If it is left open circuit, the module operates when input power is applied.
A small low-leakage (<100 nA) MOSFET is recommended for control. Do not tie the inhibit pin to VIN or to another module's inhibit pin.
See the application section for further guidance.
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ELECTRICAL CHARACTERISTICS (continued)
over -40°C to 85°C free-air temperature, PVIN = VIN = 12 V, VOUT = 1.8 V, IOUT = 6A,
CIN1 = 2x 22 µF ceramic, CIN2 = 68 µF poly-tantalum, COUT1 = 4x 47 µF ceramic (unless otherwise noted)
PARAMETER
CIN
TEST CONDITIONS
MIN
Ceramic
External input capacitance
Non-ceramic
Ceramic
COUT
External output capacitance
44
(5)
UNIT
µF
(5)
200
1500
220 (5)
5000
Equivalent series resistance (ESR)
(4)
MAX
68 (4)
47
Non-ceramic
TYP
(4)
35
µF
mΩ
A minimum of 100µF of polymer tantalum and/or ceramic external capacitance is required across the input (VIN and PGND connected)
for proper operation. Locate the capacitor close to the device. See Table 5 for more details. When operating with split VIN and PVIN
rails, place 4.7µF of ceramic capacitance directly at the VIN pin.
The amount of required output capacitance varies depending on the output voltage (see Table 3 ). The amount of required capacitance
must include at least 1x 47µF ceramic capacitor. Locate the capacitance close to the device. Adding additional capacitance close to the
load improves the response of the regulator to load transients. See Table 3 and Table 5 more details.
DEVICE INFORMATION
FUNCTIONAL BLOCK DIAGRAM
Thermal Shutdown
INH/UVLO
PWRGD
Shutdown
Logic
PWRGD
Logic
VIN
PVIN
VSENSE+
OCP
VIN
UVLO
VADJ
BOOT
+
+
SS/TR
STSEL
VREF
PH
Power
Stage
and
Control
Logic
VOUT
COMP
PGND
RC
Compensation
RT/CLK
OSC w/PLL
AGND
TPS84620
UDG-10030
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PIN DESCRIPTIONS
TERMINAL
NAME
DESCRIPTION
NO.
1
2
AGND
34
Zero VDC reference for the analog control circuitry. Connect AGND to PGND at a single point. Connect near
the output capacitors.
45
BOOT
32
Boot pin. Do not place any external component on this pin or tie it to a pin of another function. This pin must
be soldered to an isolated pad.
COMP
5
Error amplifier output. Do not place any external component on this pin or tie it to a pin of another function.
This pin must be soldered to an isolated pad.
8
INH/UVLO
9
Inhibit and UVLO adjust pin. Use an open drain or open collector output logic to control the INH function. A
resistor divider between this pin, AGND and VIN adjusts the UVLO voltage. Tie both pins together when
using this control.
15
16
18
19
DNC
20
Do not connect. These pins must remain isolated from one another. Do not connect these pins to AGND or
to any voltage. These pins must be soldered to isolated pads.
22
23
30
31
36
PGND
37
Common ground connection for the PVIN, VIN, and VOUT power connections.
38
10
11
12
PH
13
Phase switch node. Do not place any external component on this pin or tie it to a pin of another function.
14
17
46
PWRGD
33
Power good fault pin. Asserts low if the output voltage is low. A pull-up resistor is required.
39
PVIN
40
Input switching voltage. this pin supplies voltage the power switches of the converter.
41
3
RC
4
Internal compensation pin. Do not place any external component on this pin or tie it to a pin of another
function. These pins must be soldered to isolated pads.
RT/CLK
35
This pin automatically selects between RT mode and CLK mode. An external timing resistor adjusts the
switching frequency of the device. In CLK mode, the device synchronizes to an external clock.
SENSE+
44
Remote sense connection. Connect this pin to VOUT at the load for improved regulation. This pin must be
connected to VOUT at the load, or at the module pins.
SS/TR
6
Slow-start and tracking pin. Connecting an external capacitor to this pin adjusts the output voltage rise time.
A voltage applied to this pin allows for tracking and sequencing control.
STSEL
7
Slow-start or track feature select. Connect this pin to AGND to enable the internal SS capacitor with a SS
interval of approximately 1.1 ms. Leave this pin open to enable the TR feature.
VADJ
43
Connecting a resistor between this pin and AGND sets the output voltage.
VIN
42
Input bias voltage pin. Supplies the control circuitry of the power converter.
6
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PIN DESCRIPTIONS (continued)
TERMINAL
NAME
DESCRIPTION
NO.
21
24
25
VOUT
26
27
Output voltage. Connect output capacitors between these pins and PGND.
28
29
47
PVIN
PVIN
PVIN
PGND
41
40
39
38
3
VIN
RC
42
2
VADJ
AGND
43
1
SENSE+
AGND
44
BOTTOM VIEW
45
AGND
37 PGND
36
PGND
35
RT/CLK
34
AGND
RC
4
COMP
5
33
PWRGD
SS/TR
6
32
BOOT
STSEL
7
31
DNC
INH/UVLO
8
30
DNC
INH/UVLO
9
29
VOUT
PH
10
28
VOUT
PH
11
27
VOUT
26
VOUT
46
PH
47
VOUT
21
22
DNC
15
VOUT
DNC
20
VOUT
DNC
24
DNC
14
19
PH
18
VOUT
DNC
25
17
13
PH
PH
16
12
DNC
PH
23 DNC
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TYPICAL CHARACTERISTICS (PVIN = VIN = 12 V) (1)
100
100
Voltage Output Ripple, Vpp (mV)
95
90
80
75
70
VOUT = 5.0 V, fSW = 780 kHz
VOUT = 3.3 V, fSW = 630 kHz
VOUT = 2.5 V, fSW = 530 kHz
VOUT = 1.8 V, fSW = 480 kHz
VOUT = 1.2 V, fSW = 480 kHz
65
60
PVIN = 12 V
VIN = 12 V
55
0
1
2
3
4
Output Current (A)
5
80
60
40
20
PVIN = 12 V
VIN = 12 V
0
6
VOUT = 5.0 V, fSW = 780 kHz
VOUT = 3.3 V, fSW = 630 kHz
VOUT = 2.5 V, fSW = 530 kHz
VOUT = 1.8 V, fSW = 480 kHz
VOUT = 1.2 V, fSW = 480 kHz
0
Figure 1. Efficiency vs. Output Current
3
4
Output Current (A)
5
6
90
VOUT = 5.0 V, fSW = 780 kHz
VOUT = 3.3 V, fSW = 630 kHz
VOUT = 2.5 V, fSW = 530 kHz
VOUT = 1.8 V, fSW = 480 kHz
VOUT = 1.2 V, fSW = 480 kHz
3
80
Ambient Temperature (°C)
3.5
Power Dissipation (W)
2
Figure 2. Voltage Ripple vs. Output Current
4
2.5
2
1.5
1
0.5
0
1
2
3
4
Output Current (A)
5
60
50
40
30
PVIN = 12
VIN = 12
1
70
Over All Output Voltages
6
20
1
2
Gain (dB)
Figure 3. Power Dissipation vs. Output Current
3
4
Output Current (A)
120
30
90
20
60
10
30
0
0
−10
−30
−20
−60
−40
1000
Gain
Phase
PVIN = 12 V
VIN = 12 V
10000
Frequency (Hz)
5
6
Figure 4. Safe Operating Area
40
−30
Natural Convection
100000
Phase (°)
Efficiency (%)
85
50
(2)
−90
−120
400000
Figure 5. VOUT=1.2 V, IOUT=3 A, COUT1=47 µF ceramic, COUT2= 330 µF POSCAP, fSW=480 kHz
(1)
(2)
8
The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the
converter. Applies to Figure 1, Figure 2, and Figure 3.
The temperature derating curves represent the conditions at which internal components are at or below the manufacturer's maximum
operating temperatures. Derating limits apply to devices soldered directly to a 100 mm × 100 mm double-sided PCB with 1 oz. copper.
Applies to Figure 4.
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TYPICAL CHARACTERISTICS (PVIN = VIN = 5 V) (1)
100
100
Voltage Output Ripple, Vpp (mV)
95
90
80
75
70
65
VOUT = 3.3 V, fSW = 630 kHz
VOUT = 2.5 V, fSW = 530 kHz
VOUT = 1.8 V, fSW = 480 kHz
VOUT = 1.2 V, fSW = 480 kHz
60
PVIN = 5 V
VIN = 5 V
55
0
1
2
3
4
Output Current (A)
5
80
60
40
20
PVIN = 5 V
VIN = 5 V
0
6
VOUT = 3.3 V, fSW = 630 kHz
VOUT = 2.5 V, fSW = 530 kHz
VOUT = 1.8 V, fSW = 480 kHz
VOUT = 1.2 V, fSW = 480 kHz
0
Figure 6. Efficiency vs. Output Current
3
4
Output Current (A)
5
6
90
VOUT = 3.3 V, fSW = 630 kHz
VOUT = 2.5 V, fSW = 530 kHz
VOUT = 1.8 V, fSW = 480 kHz
VOUT = 1.2 V, fSW = 480 kHz
3
80
Ambient Temperature (°C)
3.5
Power Dissipation (W)
2
Figure 7. Voltage Ripple vs. Output Current
4
2.5
2
1.5
1
0.5
0
1
2
3
4
Output Current (A)
5
60
50
40
30
PVIN = 5 V
VIN = 5 V
1
70
Over All Output Voltages
6
20
1
2
Gain (dB)
Figure 8. Power Dissipation vs. Output Current
3
4
Output Current (A)
120
30
90
20
60
10
30
0
0
−10
−30
−20
−60
−40
1000
Gain
Phase
PVIN = 5 V
VIN = 5 V
10000
Frequency (Hz)
5
6
Figure 9. Safe Operating Area
40
−30
Natural Convection
100000
Phase (°)
Efficiency (%)
85
50
(2)
−90
−120
400000
Figure 10. VOUT=1.2 V, IOUT=3 A, COUT1=47 µF ceramic, COUT2= 330 µF POSCAP, fSW=480 kHz
(1)
(2)
The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the
converter. Applies to Figure 6, Figure 7, and Figure 8.
The temperature derating curves represent the conditions at which internal components are at or below the manufacturer's maximum
operating temperatures. Derating limits apply to devices soldered directly to a 100 mm × 100 mm double-sided PCB with 1 oz. copper.
Applies to Figure 9.
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TYPICAL CHARACTERISTICS (PVIN = 12 V, VIN = 5 V) (1)
100
100
Voltage Output Ripple, Vpp (mV)
95
90
80
75
70
VOUT = 5.0 V, fSW = 780 kHz
VOUT = 3.3 V, fSW = 630 kHz
VOUT = 2.5 V, fSW = 530 kHz
VOUT = 1.8 V, fSW = 480 kHz
VOUT = 1.2 V, fSW = 480 kHz
65
60
PVIN = 12 V
VIN = 5 V
55
0
1
2
3
4
Output Current (A)
5
VOUT = 5.0 V, fSW = 780 kHz
VOUT = 3.3 V, fSW = 630 kHz
VOUT = 2.5 V, fSW = 530 kHz
VOUT = 1.8 V, fSW = 480 kHz
VOUT = 1.2 V, fSW = 480 kHz
80
60
40
20
PVIN = 12 V
VIN = 5 V
0
6
0
Figure 11. Efficiency vs. Output Current
2.5
2
1.5
1
60
50
40
30
PVIN = 12 V
VIN = 5 V
1
2
3
4
Output Current (A)
5
100 LFM
Natural Convection
VOUT = 5 V
20
6
1
2
3
4
Output Current (A)
5
6
Figure 14. Safe Operating Area
90
80
40
120
30
90
20
60
10
30
0
0
70
Gain (dB)
Ambient Temperature (°C)
6
70
Figure 13. Power Dissipation vs. Output Current
60
50
40
−10
−30
−20
−60
−30
30
VOUT < 5 V
20
1
2
−40
1000
Natural Convection
3
4
Output Current (A)
5
Figure 15. Safe Operating Area
10
5
80
Ambient Temperature (°C)
Power Dissipation (W)
3
0.5
(2)
3
4
Output Current (A)
90
VOUT = 5.0 V, fSW = 780 kHz
VOUT = 3.3 V, fSW = 630 kHz
VOUT = 2.5 V, fSW = 530 kHz
VOUT = 1.8 V, fSW = 480 kHz
VOUT = 1.2 V, fSW = 480 kHz
3.5
(1)
2
Figure 12. Voltage Ripple vs. Output Current
4
0
1
6
Gain
Phase
PVIN = 12 V
VIN = 5 V
10000
Frequency (Hz)
100000
Phase (°)
Efficiency (%)
85
50
(2)
−90
−120
400000
Figure 16. VOUT=1.2 V, IOUT=3 A, COUT1=47 µF ceramic,
COUT2= 330 µF POSCAP, fSW=480 kHz
The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the
converter. Applies to Figure 11, Figure 12, and Figure 13.
The temperature derating curves represent the conditions at which internal components are at or below the manufacturer's maximum
operating temperatures. Derating limits apply to devices soldered directly to a 100 mm × 100 mm double-sided PCB with 1 oz. copper.
Applies to Figure 14 and Figure 15.
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APPLICATION INFORMATION
ADJUSTING THE OUTPUT VOLTAGE
The VADJ control sets the output voltage of the TPS84620. The output voltage adjustment range is from 1.2V to
5.5V. The adjustment method requires the addition of RSET, which sets the output voltage, the connection of
SENSE+ to VOUT, and in some cases RRT which sets the switching frequency. The RSET resistor must be
connected directly between the VADJ (pin 43) and AGND (pin 45). The SENSE+ pin (pin 44) must be connected
to VOUT either at the load for improved regulation or at VOUT of the module. The RRT resistor must be
connected directly between the RT/CLK (pin 35) and AGND (pin 34).
Table 1 gives the standard external RSET resistor for a number of common bus voltages, along with the required
RRT resistor for that output voltage.
Table 1. Standard RSET Resistor Values for Common Output Voltages
RESISTORS
OUTPUT VOLTAGE VOUT (V)
1.2
1.5
1.8
2.5
3.3
5.0
RSET (kΩ)
2.87
1.62
1.13
0.665
0.453
0.267
RRT (kΩ)
open
open
open
1000
332
165
For other output voltages, the value of the required resistor can either be calculated using the following formula,
or simply selected from the range of values given in Table 2.
1.43
RSET =
(kW )
æ æ VOUT ö ö
çç
÷ - 1÷
è è 0.8 ø ø
(1)
Table 2. Standard RSET Resistor Values
VOUT (V)
RSET (kΩ)
RRT(kΩ)
fSW(kHz)
VOUT (V)
RSET (kΩ)
RRT(kΩ)
fSW(kHz)
1.2
2.87
open
480
3.4
0.442
332
630
1.3
2.26
open
480
3.5
0.422
332
630
1.4
1.91
open
480
3.6
0.402
332
630
1.5
1.62
open
480
3.7
0.392
332
630
1.6
1.43
open
480
3.8
0.374
249
680
1.7
1.27
open
480
3.9
0.365
249
680
1.8
1.13
open
480
4.0
0.357
249
680
1.9
1.02
open
480
4.1
0.348
249
680
2.0
0.953
open
480
4.2
0.332
196
730
2.1
0.866
open
480
4.3
0.324
196
730
2.2
0.806
open
480
4.4
0.316
196
730
2.3
0.750
open
480
4.5
0.309
196
730
2.4
0.715
open
480
4.6
0.301
196
730
2.5
0.665
open
480
4.7
0.294
196
730
2.6
0.634
1000
530
4.8
0.287
165
780
2.7
0.604
1000
530
4.9
0.280
165
780
2.8
0.562
1000
530
5.0
0.267
165
780
2.9
0.536
1000
530
5.1
0.267
165
780
3.0
0.511
499
580
5.2
0.261
165
780
3.1
0.499
499
580
5.3
0.255
165
780
3.2
0.475
499
580
5.4
0.249
165
780
3.3
0.453
332
630
5.5
0.243
165
780
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CAPACITOR RECOMMENDATIONS FOR THE TPS84620 POWER SUPPLY
Capacitor Technologies
Electrolytic, Polymer-Electrolytic Capacitors
When using electrolytic capacitors, high-quality, computer-grade electrolytic capacitors are recommended.
Polymer-electrolytic type capacitors are recommended for applications where the ambient operating temperature
is less than 0°C. The Sanyo OS-CON capacitor series is suggested due to the lower ESR, higher rated surge,
power dissipation, ripple current capability, and small package size. Aluminum electrolytic capacitors provide
adequate decoupling over the frequency range of 2 kHz to 150 kHz, and are suitable when ambient temperatures
are above 0°C.
Ceramic Capacitors
The performance of aluminum electrolytic capacitors is less effective than ceramic capacitors above 150 kHz.
Multilayer ceramic capacitors have a low ESR and a resonant frequency higher than the bandwidth of the
regulator. They can be used to reduce the reflected ripple current at the input as well as improve the transient
response of the output.
Tantalum, Polymer-Tantalum Capacitors
Polymer-tantalum type capacitors are recommended for applications where the ambient operating temperature is
less than 0°C. The Sanyo POSCAP series and Kemet T530 capacitor series are recommended rather than many
other tantalum types due to their lower ESR, higher rated surge, power dissipation, ripple current capability, and
small package size. Tantalum capacitors that have no stated ESR or surge current rating are not recommended
for power applications.
Input Capacitor
The TPS84620 requires a minimum input capacitance of 100 mF of ceramic and/or polymer-tantalum capacitors.
The ripple current rating of the capacitor must be at least 450 mArms. Table 5 includes a preferred list of
capacitors by vendor.
Output Capacitor
The required output capacitance is determined by the output voltage of the TPS84620. See Table 3 for the
amount of required capacitance. The required output capacitance can be comprised of either all ceramic
capacitors, or a combination of ceramic and bulk capacitors. The required output capacitance must include at
least 1x 47 µF ceramic capacitor. When adding additional non-ceramic bulk capacitors, low-ESR devices like the
ones recommended in Table 5 are required. The required capacitance above the minimum is determined by
actual transient deviation requirements. See Table 4 for typical transient response values for several output
voltage, input voltage and capacitance combinations. Table 5 includes a preferred list of capacitors by vendor.
Table 3. Required Output Capacitance
VOUT RANGE (V)
(1)
12
MINIMUM REQUIRED COUT (µF)
MIN
MAX
1.2
< 3.0
200 (1)
3.0
< 4.0
100 (1)
4.0
5.5
47 µF ceramic
Minimum required must include at least one 47 µF ceramic capacitor.
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Table 4. Output Voltage Transient Response
CIN1 = 2 x 22 µF CERAMIC, CIN2 = 68 µF POSCAP, LOAD STEP = 3 A, 1 A/µs
VOUT (V)
PVIN (V)
3.3
1.2
5
12
3.3
1.5
5
12
3.3
1.8
5
12
3.3
2.5
5
12
5
3.3
12
5
5.0
12
COUT2 BULK
VOLTAGE
DEVIATION (mV)
PEAK-PEAK (mV)
RECOVERY TIME
(µs)
4x 47 µF
None
73
137
70
1x 47 µF
330 µF
50
90
75
4x 47 µF
None
63
117
70
1x 47 µF
330 µF
45
85
75
4x 47 µF
None
45
109
70
1x 47 µF
330 µF
35
70
75
4x 47 µF
None
80
160
80
1x 47 µF
220 µF
65
130
70
4x 47 µF
None
60
115
80
1x 47 µF
220 µF
60
120
70
4x 47 µF
None
45
98
80
1x 47 µF
220 µF
50
100
70
4x 47 µF
None
90
180
80
1x 47 µF
220 µF
72
142
110
4x 47 µF
None
80
160
80
1x 47 µF
220 µF
67
132
110
4x 47 µF
None
60
120
80
1x 47 µF
220 µF
60
119
110
4x 47 µF
None
108
214
75
1x 47 µF
100 µF
93
186
110
4x 47 µF
None
100
200
75
1x 47 µF
100 µF
92
180
110
4x 47 µF
None
88
174
75
1x 47 µF
100 µF
80
157
110
2x 47 µF
None
160
320
100
1x 47 µF
100 µF
110
220
100
2x 47 µF
None
140
280
100
1x 47 µF
100 µF
100
200
100
1x 47 µF
None
200
400
100
1x 47 µF
100 µF
150
300
130
1x 47 µF
None
180
360
100
1x 47 µF
100 µF
150
300
130
COUT1 Ceramic
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Table 5. Recommended Input/Output Capacitors (1)
CAPACITOR CHARACTERISTICS
VENDOR
SERIES
PART NUMBER
WORKING
VOLTAGE
(V)
CAPACITANCE
(µF)
ESR (2)
(mΩ)
Murata
X5R
GRM32ER61E226K
16
22
2
TDK
X5R
C3225X5R0J476K
6.3
47
2
Murata
X5R
GRM32ER60J476M
6.3
47
2
Sanyo
POSCAP
16TQC68M
16
68
50
Kemet
T520
T520V107M010ASE025
10
100
25
Sanyo
POSCAP
6TPE100MI
6.3
100
25
Sanyo
POSCAP
2R5TPE220M7
2.5
220
7
Kemet
T530
T530D227M006ATE006
6.3
220
6
Kemet
T530
T530D337M006ATE010
6.3
330
10
Sanyo
POSCAP
2TPF330M6
2.0
330
6
Sanyo
POSCAP
6TPE330MFL
6.3
330
15
(1)
(2)
14
Capacitor Supplier Verification
Please verify availability of capacitors identified in this table.
RoHS, Lead-free and Material Details
Please consult capacitor suppliers regarding material composition, RoHS status, lead-free status, and manufacturing process
requirements.
Maximum ESR @ 100kHz, 25°C.
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Transient Response
Figure 17. PVIN = 12V, VOUT = 1.2V, 3A Load Step
Figure 18. PVIN = 5V, VOUT = 1.2V, 3A Load Step
Figure 19. PVIN = 12V, VOUT = 1.8V, 3A Load Step
Figure 20. PVIN = 5V, VOUT = 1.8V, 3A Load Step
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Figure 21. PVIN = 12V, VOUT = 2.5V, 3A Load Step
Figure 22. PVIN = 5V, VOUT = 2.5V, 3A Load Step
Figure 23. PVIN = 12V, VOUT = 3.3V, 3A Load Step
Figure 24. PVIN = 5V, VOUT = 3.3V, 3A Load Step
16
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Application Schematics
TPS84620
VIN
VIN / PVIN
4.5 V to 14.5 V
PWRGD
PVIN
+
CIN2
68 mF
CIN1
47 mF
VOUT
1.8 V
SENSE+
INH/UVLO
VOUT
COUT1 +
47 mF
SS/TR
COUT2
220 mF
RT/CLK
VADJ
RSET
1.13 kW
STSEL AGND PGND
UDG-10130
Figure 25. Typical Schematic
PVIN = VIN = 4.5 V to 14.5 V, VOUT = 1.8 V
TPS84620
VIN
VIN / PVIN
4.5 V to 14.5 V
PWRGD
PVIN
+
CIN2
68 mF
CIN1
47 mF
VOUT
3.3 V
SENSE+
INH/UVLO
VOUT
SS/TR
COUT1 +
47 mF
COUT2
100 mF
RT/CLK
RRT
332 kW
VADJ
RSET
453 W
STSEL AGND PGND
UDG-10129
Figure 26. Typical Schematic
PVIN = VIN = 4.5 V to 14.5 V, VOUT = 3.3 V
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VIN
4.5 V to 14.5 V
CIN3
4.7 mF
VIN
TPS84620
PVIN
3.3 V
+
PWRGD
PVIN
CIN2
68 mF
CIN1
47 mF
VOUT
1.2 V
SENSE+
INH/UVLO
VOUT
SS/TR
COUT1 +
47 mF
COUT2
330 mF
RT/CLK
VADJ
RSET
2.87 kW
STSEL AGND PGND
UDG-10131
Figure 27. Typical Schematic
PVIN = 3.3 V, VIN = 4.5 V to 14.5 V, VOUT = 1.2 V
VIN and PVIN Input Voltage
The TPS84620 allows for a variety of applications by using the VIN and PVIN pins together or separately. The
VIN voltage supplies the internal control circuits of the device. The PVIN voltage provides the input voltage to the
power converter system.
If tied together, the input voltage for the VIN pin and the PVIN pin can range from 4.5 V to 14.5 V. If using the
VIN pin separately from the PVIN pin, the VIN pin must be between 4.5 V and 14.5 V, and the PVIN pin can
range from as low as 1.7 V to 14.5 V. A voltage divider connected to the INH/UVLO pin can adjust the either
input voltage UVLO appropriately. See the Programmable Undervoltage Lockout (UVLO) section of this
datasheet for more information.
Power Good (PWRGD)
The PWRGD pin is an open drain output. Once the voltage on the SENSE+ pin is between 94% and 106% of the
set voltage, the PWRGD pin pull-down is released and the pin floats. The recommended pull-up resistor value is
between 10 kΩ and 100 kΩ to a voltage source that is 5.5 V or less. The PWRGD pin is in a defined state once
VIN is greater than 1.0 V, but with reduced current sinking capability. The PWRGD pin achieves full current
sinking capability once the VIN pin is above 4.5V. The PWRGD pin is pulled low when the voltage on SENSE+ is
lower than 91% or greater than 109% of the nominal set voltage. Also, the PWRGD pin is pulled low if the input
UVLO or thermal shutdown is asserted, the INH pin is pulled low, or the SS/TR pin is below 1.4 V.
18
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Power-Up Characteristics
When configured as shown in the front page schematic, the TPS84620 produces a regulated output voltage
following the application of a valid input voltage. During the power-up, internal soft-start circuitry slows the rate
that the output voltage rises, thereby limiting the amount of in-rush current that can be drawn from the input
source. The soft-start circuitry introduces a short time delay from the point that a valid input voltage is
recognized. Figure 28 shows the start-up waveforms for a TPS84620, operating from a 5-V input (PVIN=VIN)
and with the output voltage adjusted to 1.8 V. Figure 29 shows the start-up waveforms for a TPS84620 starting
up into a pre-biased output voltage. The waveforms were measured with a 3-A constant current load.
Figure 28. Start-Up Waveforms
Figure 29. Start-up into Pre-bias
Pre-Biased Start-Up
The TPS84620 has been designed to prevent discharging a pre-biased output. During monotonic pre-biased
startup, the TPS84620 does not allow current to sink until the SS/TR pin voltage is higher than 1.4 V.
Remote Sense
The SENSE+ pin must be connected to VOUT at the load, or at the device pins.
Connecting the SENSE+ pin to VOUT at the load improves the load regulation performance of the device by
allowing it to compensate for any I-R voltage drop between its output pins and the load. An I-R drop is caused by
the high output current flowing through the small amount of pin and trace resistance. This should be limited to a
maximum of 300 mV.
NOTE
The remote sense feature is not designed to compensate for the forward drop of nonlinear
or frequency dependent components that may be placed in series with the converter
output. Examples include OR-ing diodes, filter inductors, ferrite beads, and fuses. When
these components are enclosed by the SENSE+ connection, they are effectively placed
inside the regulation control loop, which can adversely affect the stability of the regulator.
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Output On/Off Inhibit (INH)
The INH pin provides electrical on/off control of the device. Once the INH pin voltage exceeds the threshold
voltage, the device starts operation. If the INH pin voltage is pulled below the threshold voltage, the regulator
stops switching and enters low quiescent current state.
The INH pin has an internal pull-up current source, allowing the user to float the INH pin for enabling the device.
If an application requires controlling the INH pin, use an open drain/collector device, or a suitable logic gate to
interface with the pin.
Figure 30 shows the typical application of the inhibit function. The Inhibit control has its own internal pull-up to
VIN potential. An open-collector or open-drain device is recommended to control this input.
Turning Q1 on applies a low voltage to the inhibit control (INH) pin and disables the output of the supply, shown
in Figure 31. If Q1 is turned off, the supply executes a soft-start power-up sequence, as shown in Figure 32. A
regulated output voltage is produced within 10 ms. The waveforms were measured with a 3-A constant current
load.
TPS84620
INH/UVLO
Q1
INH
Control
AGND
STSEL
UDG-10081
Figure 30. Typical Inhibit Control
Figure 31. Inhibit Turn-Off
20
Figure 32. Inhibit Turn-On
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Slow Start (SS/TR)
Connecting the STSEL pin to AGND and leaving SS/TR pin open enables the internal SS capacitor with a slow
start interval of approximately 1.1 ms. Adding additional capacitance between the SS pin and AGND increases
the slow start time. Table 6 shows an additional SS capacitor connected to the SS/TR pin and the STSEL pin
connected to AGND. See Table 6 below for SS capacitor values and timing interval.
TPS84620
SS/TR
CSS
(Optional)
AGND
STSEL
UDG-10082
Figure 33. Slow-Start Capacitor (CSS) and STSEL Connection
Table 6. Slow-Start Capacitor Values and Slow-Start Time
CSS (pF)
open
2200
4700
10000
15000
22000
25000
SS Time (msec)
1.1
1.9
2.8
4.6
6.4
8.8
9.8
Overcurrent Protection
For protection against load faults, the TPS84620 uses current limiting. The device is protected from overcurrent
conditions by cycle-by-cycle current limiting. During an overcurrent condition the output current is limited and the
output voltage is reduced, as shown in Figure 34. When the overcurrent condition is removed, the output voltage
returns to the established voltage, as shown in Figure 35.
Figure 34. Overcurrent Limiting
Figure 35. Removal of Overcurrent Condition
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Synchronization (CLK)
An internal phase locked loop (PLL) has been implemented to allow synchronization between 480 kHz and
780 kHz, and to easily switch from RT mode to CLK mode. To implement the synchronization feature, connect a
square wave clock signal to the RT/CLK pin with a duty cycle between 20% to 80%. The clock signal amplitude
must transition lower than 0.8 V and higher than 2.0 V. The start of the switching cycle is synchronized to the
falling edge of RT/CLK pin. In applications where both RT mode and CLK mode are needed, the device can be
configured as shown in .
Before the external clock is present, the device works in RT mode and the switching frequency is set by RT
resistor. When the external clock is present, the CLK mode overrides the RT mode. The first time the CLK pin is
pulled above the RT/CLK high threshold (2.0 V), the device switches from RT mode to th CLK mode and the
RT/CLK pin becomes high impedance as the PLL starts to lock onto the frequency of the external clock. It is not
recommended to switch from CLK mode back to RT mode because the internal switching frequency drops to 100
kHz first before returning to the switching frequency set by the RT resistor (RRT).
TPS84620
External Clock
480 kHz to 780 kHz
RT/CLK
RRT
AGND
UDG-10128
Figure 36. CLK/RT Configuration
The synchronization frequency must be selected based on the output voltages of the devices being
synchronized. Table 7 shows the allowable frequencies for a given range of output voltages. For the most
efficient solution, always synchronize to the lowest allowable frequency. For example, an application requires
synchronizing three TPS84620 devices with output voltages of 1.2 V, 1.8 V and 2. 5V, all powered from PVIN =
12 V. Table 7 shows that all three output voltages can be synchronized to either 530 kHz or 580 kHz. For best
efficiency, choose 530 kHz as the sychronization frequency.
Table 7. Synchronization Frequency vs Output Voltage
SYNCHRONIZATION
FREQUENCY (kHz)
22
RRT (kΩ)
PVIN = 12 V
PVIN = 5 V
VOUT RANGE (V)
VOUT RANGE (V)
MIN
MAX
480
OPEN
1.2
2.2
530
1000
1.2
2.5
580
499
1.2
2.9
630
332
1.3
3.3
680
249
1.4
3.8
730
196
1.5
4.3
780
165
1.6
5.5
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MAX
1.2
4.5
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Sequencing (SS/TR)
Many of the common power supply sequencing methods can be implemented using the SS/TR, INH and
PWRGD pins. The sequential method is illustrated in Figure 37 using two TPS84620 devices. The PWRGD pin
of the first device is coupled to the INH pin of the second device which enables the second power supply once
the primary supply reaches regulation. Figure 38 shows sequential turn-on waveforms of two TPS84620 devices.
TPS84620
TPS84620
PWRGD
INH/UVLO
INH/UVLO
PWRGD
SS/TR
SS/TR
UDG-10106
Figure 37. Sequencing Schematic
Figure 38. Sequencing Waveforms
Simultaneous power supply sequencing can be implemented by connecting the resistor network of R1 and R2
shown in Figure 39 to the output of the power supply that needs to be tracked or to another voltage reference
source. Figure 40 shows simultaneous turn-on waveforms of two TPS84620 devices. Use Equation 2 and
Equation 3 to calculate the values of R1 and R2.
R1 =
(VOUT2 ´ 12.6 )
0.8
R2 =
(kW )
(2)
0.8 ´ R1
(kW )
(VOUT2 - 0.8 )
(3)
TPS84620
VOUT1
VOUT
INH/UVLO
STSEL
SS/TR
TPS84620
VOUT2
VOUT
INH/UVLO
R1
STSEL
SS/TR
R2
UDG-10107
Figure 39. Simultaneous Tracking Schematic
Figure 40. Simultaneous Tracking Waveforms
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Programmable Undervoltage Lockout (UVLO)
The TPS84620 implements internal UVLO circuitry on the VIN pin. The device is disabled when the VIN pin
voltage falls below the internal VIN UVLO threshold. The internal VIN UVLO rising threshold is 4.5 V(max) with a
typical hysteresis of 150 mV.
If an application requires either a higher UVLO threshold on the VIN pin or a higher UVLO threshold for a
combined VIN and PVIN, then the UVLO pin can be configured as shown in Figure 41 or Figure 42. Table 8 lists
standard values for RUVLO1 and RUVLO2 to adjust the VIN UVLO voltage up.
TPS84620
TPS84620
PVIN
PVIN
VIN
VIN
RUVLO1
RUVLO1
INH/UVLO
INH/UVLO
RUVLO2
RUVLO2
UDG-10108
UDG-10109
Figure 41. Adjustable VIN UVLO
Figure 42. Adjustable VIN and PVIN Undervoltage
Lockout
Table 8. Standard Resistor values for Adjusting VIN UVLO
VIN UVLO (V)
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
RUVLO1 (kΩ)
68.1
68.1
68.1
68.1
68.1
68.1
68.1
68.1
68.1
68.1
68.1
RUVLO2 (kΩ)
21.5
18.7
16.9
15.4
14.0
13.0
12.1
11.3
10.5
9.76
9.31
Hysteresis (V)
400
415
430
450
465
480
500
515
530
550
565
For a split rail application, if a secondary UVLO on PVIN is required, VIN must be ≥ 4.5V. Figure 43 shows the
PVIN UVLO configuration. Use Table 9 to select RUVLO1 and RUVLO2 for PVIN. If PVIN UVLO is set for less than
3.0 V, a 5.1-V zener diode should be added to clamp the voltage on the UVLO pin below 6 V.
TPS84620
> 4.5 V
VIN
PVIN
RUVLO1
INH/UVLO
RUVLO2
UDG-10110
Figure 43. Adjustable PVIN Undervoltage Lockout, (VIN ≥4.5 V)
Table 9. Standard Resistor Values for Adjusting PVIN UVLO, (VIN ≥4.5 V)
PVIN UVLO (V)
24
2.0
2.5
3.0
3.5
4.0
4.5
RUVLO1 (kΩ)
68.1
68.1
68.1
68.1
68.1
68.1
RUVLO2 (kΩ)
95.3
60.4
44.2
34.8
28.7
24.3
Hysteresis (V)
300
315
335
350
365
385
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For higher PVIN UVLO voltages see
Table UV for resistor values
Copyright © 2010–2011, Texas Instruments Incorporated
Product Folder Link(s): TPS84620
TPS84620
www.ti.com
SLVSA43A – OCTOBER 2010 – REVISED JANUARY 2011
Thermal Shutdown
The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds
175°C typically. The device reinitiates the power up sequence when the junction temperature drops below 165°C
typically.
Layout Considerations
To achieve optimal electrical and thermal performance, an optimized PCB layout is required. Figure 44, shows a
typical PCB layout. Some considerations for an optimized layout are:
• Use large copper areas for power planes (VIN, VOUT, and PGND) to minimize conduction loss and thermal
stress.
• Place ceramic input and output capacitors close to the module pins to minimize high frequency noise.
• Locate additional output capacitors between the ceramic capacitor and the load.
• Place a dedicated AGND copper area beneath the TPS84620.
• Isolate the PH copper area from the VOUT copper area using the AGND copper area.
• Connect the AGND and PGND copper area at one point; near the output capacitors.
• Place RSET, RRT, and CSS as close as possible to their respective pins.
• Use multiple vias to connect the power planes to internal layers.
VOUT
SENSE+
Via
COUT2
COUT1
PGND
RRT
CIN1
CIN2
AGND
PH
RSET
VIN/PVIN
SENSE+
Via
CSS
UDG-10132
Figure 44. Typical Recommended Layout
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Copyright © 2010–2011, Texas Instruments Incorporated
Product Folder Link(s): TPS84620
25
TPS84620
SLVSA43A – OCTOBER 2010 – REVISED JANUARY 2011
www.ti.com
EMI
The TPS84620 is compliant with EN55022 Class B radiated emissions. Figure 45 and Figure 46 show typical
examples of radiated emissions plots for the TPS84620 operating from 5V and 12V respectively. Both graphs
include the plots of the antenna in the horizontal and vertical positions.
Figure 45. Radiated Emissions 5-V Input, 1.8-V
Output, 6-A Load (EN55022 Class B)
26
Figure 46. Radiated Emissions 12-V Input, 1.8-V
Output, 6-A Load (EN55022 Class B)
Submit Documentation Feedback
Copyright © 2010–2011, Texas Instruments Incorporated
Product Folder Link(s): TPS84620
TPS84620
www.ti.com
SLVSA43A – OCTOBER 2010 – REVISED JANUARY 2011
Changes from Original (October 2010) to Revision A
Page
•
Changed EN maximum voltage value from 3 V to 6 V ......................................................................................................... 2
•
Changed (corrected) resistor label from RRT to RSET on schematic ................................................................................... 17
•
Changed (corrected) minor typographical error on schematic ........................................................................................... 18
•
Changed (corrected) typographical error. ........................................................................................................................... 18
•
Changed (corrected) time axis division units label from 5 µs/div to 5 ms/div in Inhibit Turn-On waveform. ...................... 20
Submit Documentation Feedback
Copyright © 2010–2011, Texas Instruments Incorporated
Product Folder Link(s): TPS84620
27
PACKAGE OPTION ADDENDUM
www.ti.com
27-Jan-2011
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
TPS84620RUQR
ACTIVE
B1QFN
RUQ
47
500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Add to cart
TPS84620RUQT
ACTIVE
B1QFN
RUQ
47
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Add to cart
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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