PI74ALVCH1622601 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 18-Bit Universal Bus Transceiver With 3-State Outputs Product Features Product Description • • • • Pericom Semiconductor’s PI74ALVCH series of logic circuits are produced in the Company’s advanced 0.5 micron CMOS technology, achieving industry leading speed. • • • • • PI74ALVCH1622601is designed for low voltage operation VCC = 2.3V to 3.6V Hysteresis on all inputs Typical VOLP (Output Ground Bounce) < 0.8V at VCC = 3.3V, TA = 25°C Typical VOHV (Output VOH Undershoot) < 2.0V at VCC = 3.3V, TA = 25°C Inputs/Outputs have equivalent 26Ω series resistors, no external resistors are required. Bus Hold retains last active bus state during 3-state eliminates the need for external pullup resistors Industrial operation at –40°C to +85°C Packages available: – 56-pin 240 mil wide plastic TSSOP (A) – 56-pin 300 mil wide plastic SSOP (V) The PI74ALVCH1622601 uses D-type latches and D-type flipflops with 3-state outputs to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by Output Enable (OEAB and OEBA), Latched Enable (LEAB and LEBA), and Clock (CLKAB and CLKBA) inputs. The clock can be controlled by the Clock Enable (CLKENAB and CLKENBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A-bus is stored in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB is low, the outputs are active. When OEAB is HIGH, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, CLKBA, and CLKENBA. To reduce overshoot and undershoot, the inputs/outputs include 26Ω series resistors. To ensure the high-impedance state during power up or power down, OE should be tied to Vcc through a pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The PI74ALVCH1622601 has “Bus Hold” which retains the data input’s last state whenever the data input goes to high-impedance preventing “floating” inputs and eliminating the need for pullup/ down resistors. Logic Block Diagram 1 PS8115B 02/03/98 PI74ALVCH1622601 18-BIT UNIVERSAL BUS TRANSCEIVER 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Truth Table(1)† Product Pin Description Pin Name CLKEN OE LE CLK Ax Bx GND VCC Description Clock Enable Input (Active LOW) Output Enable Input (Active LOW) Latch Enable (Active HIGH) Clock Input (Active HIGH) Data I/O Data I/O Ground Power CLKENAB X X X H H L L L L 1 2 56 55 CLKENAB 3 4 5 54 53 52 B1 A4 6 7 8 51 56-PIN 50 A-56 49 A5 A6 9 10 GND LEAB A1 GND A2 A3 VCC V-56 CLKAB GND B2 B3 VCC B4 48 47 B5 11 12 13 46 45 44 GND 14 15 16 43 42 41 B9 17 18 40 39 B12 19 20 21 38 37 36 22 23 24 35 34 33 A18 25 26 32 31 OEBA LEBA 27 28 30 29 A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC A16 A17 GND CLKAB X X S X X L H A X L H X X L H X X Output B Z L H B0 B0 L H B0 B0§ Notes: 1. H = High Signal Level L = Low Signal Level Z = High Impedance ↑ = LOW-to-HIGH Transition † A-to-B data flow is shown: B-to-A flow is similar but uses OEBA, LEBA, CLKBA, and CLKENBA. ‡ Output level before the indicated steady-state input conditions were established. § Output level before the indicated steady-state input conditions were established, provided that CLKAB is LOW before LEAB goes LOW. Product Pin Configuration OEAB Inputs OEAB LEAB H X L H L H L L L L L L L L L L L L B6 B7 B8 B10 B11 GND B13 B14 B15 VCC B16 B17 GND B18 CLKBA CLKENBA 2 PS8115B 02/03/98 PI74ALVCH1622601 18-BIT UNIVERSAL BUS TRANSCEIVER 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................................. 65°C to +150°C Ambient Temperature with Power Applied ................. 40°C to +85°C Input Voltage Range, VIN ..................................... 0.5V to VCC +0.5V Output Voltage Range, VOUT ............................... 0.5V to VCC +0.5V DC Input Voltage .......................................................... 0.5V to +5.0V DC Output Current ...................................................................... 100mA Power Dissipation .......................................................................... 1.0W Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Recommended Operating Conditions(1) Parame te rs De s cription VCC Supply Voltage VIH Input HIGH Voltage VIL Input LOW Voltage VIN Input Voltage 0 VCC VOUT Output Voltage 0 VCC IOH IOL TA High- level Output Current Low- level Output Current Te s t Conditions M in. 2.3 VCC = 2.3V to 2.7V 1.7 VCC = 2.7V to 3.6V 2.0 Typ. M ax. 3.6 VCC = 2.3V to 2.7V 0.7 VCC = 2.7V to 3.6V 0.8 VCC = 2.3V -6 VCC = 2.7V -8 VCC = 3.0V - 12 VCC = 2.3V 6 VCC = 2.7V 8 VCC = 3.0V 12 Operating Free- Air Temperature - 40 Units 85 V mA °C Note: 1. Unused control inputs must be held HIGH or LOW to prevent them from floating. 3 PS8115B 02/03/98 PI74ALVCH1622601 18-BIT UNIVERSAL BUS TRANSCEIVER 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 DC Electrical Characteristics (Over the Operating Range, TA = –40°C to +85°C, VCC = 3.3V ± 10%) Parame te rs VCC(1) M in. Min. to Max. VCC - 0.2 VIH = 1.7V 2.3V 1.9 VIH = 1.7V 2.3V 1.7 Te s t Conditions IOH = - 100 mA IOH = - 4 mA VOH IOH = - 6 mA VIH = 2.0V 3.0V 2.4 IOH = - 8 mA VIH = 2.0V 2.7V 2.0 IOH = - 12 mA VIH = 2.0V 3.0V 2.0 Min. to Max. VCC - 0.2 IOL = 100 mA IOL = 4 mA VOL II II (Hold)(3) ICC DICC M ax. Units 0.2 V VIL = 0.7V 2.3V 0.4 VIL = 0.7V 2.3V 0.55 VIL = 0.8V 3.0V 0.55 IOL = 8 mA VIL = 0.8V 2.7V 0.6 IOL = 12 mA VIL = 0.8V 3.0V 0.8 3.6V ±5 IOL = 6 mA VI = VCC or GND VI = 0.7V 45 2.3V VI = 1.7V VI = 0.8V - 45 75 3.0V VI = 2.0V IOZ(4) Typ.(2) - 75 mA VI = 0 to 3.6V 3.6V ±500 VO = VCC or GND 3.6V ±10 VI = VCC or GND IO = 0 One input at VCC - 0.6V, other inputs at VCC or GND 3.6V 40 3V to 3.6V 750 CI Control Inputs VI = VCC or GND CIO A or B ports VO = VCC or GND 3.3V 4 3.3V 8 pF Notes: 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, +25°C ambient and maximum loading. 3. Bus Hold maximum dynamic current required to switch the input from one state to another. 4. For I/O ports, the IOZ includes the input leakage current. Operating Characteristics, TA = 25°C Parame te r Te s t Conditions Vcc = 2.5V ± 0.2V Vcc = 3.3V ± 0.3V Typical Typical CPD Power Dissipation Outputs Enabled Capacitance Outputs Disabled CL= 50pF, F = 10 MHz 41 50 6 6 4 Units pF PS8115B 02/03/98 PI74ALVCH1622601 18-BIT UNIVERSAL BUS TRANSCEIVER 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Timing Requirements over Operating Range Parame te rs VCC= 2.5 V ± 0.2 V D e s cription VCC= 2.7 V VCC= 3.3 V ± 0.3 V M in. M ax. M in. M ax. M in. M ax. 0 140 0 150 0 150 fCLOCK Clock frequency tW Pulse Duration LE high 3.3 3.3 3.3 CLK high or low 3.3 3.3 3.3 Data before CLK high 2.3 2.4 2.1 Data before LE low, CLK high 2.0 1.6 1.6 Data before LE low, CLK low 1.3 1.2 1.1 CLK EN before CLK high 2.0 2.0 1.7 Data after CLK high 0.7 0.7 0.8 Data after LE low, CLK high 1.3 1.6 1.4 Data after LE low, CLK low 1.7 2.0 1.7 CLK EN after CLK high 0.3 0.5 0.6 tSU Setup time tH Hold time Dt/Dv(1) Input Transition Rise or Fall 0 10 0 10 0 Units MHz ns 10 ns/V Note: 1. Unused control inputs must be held HIGH or LOW to prevent them from floating. Switching Characteristics over Operating Range(1) Parame te rs From (INPUT) To (OUTPUT) VCC = 2.5 V ± 0.2 V M in.(2) M in.(2) M ax. 140 fMAX VCC = 2.7 V M ax. 150 VCC = U3.3 V ± 0.3 V M in.(2) Units M ax. 150 MHz tPD A B 1.8 5.4 5.2 1.6 4.5 tPD B A 1.8 5.4 5.2 1.6 4.5 tPD LEAB B 1.5 6.1 5.9 1.5 5.1 tPD LEBA A 1.5 6.1 5.9 1.5 5.1 tPD CLKAB B 2 6.7 6.3 1.6 5.5 tPD CLKBA A 1.2 6.7 6.3 1.6 5.5 tEN OEAB B 1.7 6.6 6.7 1.6 5.7 tDIS OEAB B 2.5 5.9 5.3 1.8 4.8 tEN OEBA A 1.7 6.6 6.7 1.6 5.7 tDIS OEBA A 2.5 5.9 5.3 1.8 4.8 ns Notes: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com 5 PS8115B 02/03/98