TI SN65HVD1040D

SN65HVD1040
www.ti.com
SLLS631B – MARCH 2007 – REVISED APRIL 2007
LOW-POWER CAN TRANSCEIVER WITH BUS WAKE-UP
FEATURES
APPLICATIONS
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Improved Drop-in Replacement for the
TJA1040
±12 kV ESD Protection
Low-Current Standby Mode with Bus
Wake-up: 5 µA Typical
Bus-Fault Protection of –27 V to 40 V
Rugged Split-Pin Bus Stability
Dominant Time-Out Function
Power-Up/Down Glitch-Free Bus Inputs and
Outputs
– High Input Impedance with Low VCC
– Monotonic Outputs During Power Cycling
DeviceNet Vendor ID # 806
Battery Operated Applications
Hand-Held Diagnostics
Medical Scanning and Imaging
HVAC
Security Systems
Telecom Base Station Status and Control
SAE J1939 Standard Data Bus Interface
NMEA 2000 Standard Data Bus Interface
ISO 11783 Standard Data Bus Interface
Industrial Automation
– DeviceNet™ Data Buses
DESCRIPTION
The SN65HVD1040 meets or exceeds the specifications of the ISO 11898 standard for use in applications
employing a Controller Area Network (CAN). As CAN transceivers, these devices provide differential transmit
and receive capability for a CAN controller at signaling rates of up to 1 megabit per second (Mbps). (1)
Designed for operation in especially harsh environments, the device features ±12 kV ESD protection on the bus
and split pins, cross-wire, overvoltage and loss of ground protection from –27 to 40 V, overtemperature
shutdown, a –12 V to 12 V common-mode range, and will withstand voltage transients from –200 V to 200 V
according to ISO 7637.
VCC
VCC
TXD
DOMINANT
TIME -OUT
30 mA
1
OVER
TEMPERATURE
SENSOR
INPUT
LOGIC
3
VCC / 2
5
SPLIT
DRIVER
VCC
7
STB
RXD
8
4
10 mA
6
SLEEP
OUTPUT
LOGIC
MODE
CANH
CANL
MUX
WAKE UP
FILTER
BUS MONITOR
2
(1)
The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DeviceNet is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
SN65HVD1040
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SLLS631B – MARCH 2007 – REVISED APRIL 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (Continued)
The STB input (pin 8) selects between two different modes of operation; high-speed or low-power mode. The
high-speed mode of operation is selected by connecting STB to ground.
If a high logic level is applied to the STB pin of the SN65HVD1040, the device enters a low-power bus-monitor
standby mode. While the SN65HVD1040 is in the low-power bus-monitor standby mode, a dominant bit greater
than 5 µs on the bus is passed by the bus-monitor circuit to the receiver output. The local protocol controller
may then reactivate the device when it needs to transmit to the bus.
A dominant-time-out circuit in the SN65HVD1040 prevents the driver from blocking network communication
during a hardware or software failure. The time-out circuit is triggered by a falling edge on TXD (pin 1). If no
rising edge is seen before the time-out constant of the circuit expires, the driver is disabled. The circuit is then
reset by the next rising edge on TXD.
The SPLIT output (pin 5) is available on the SN65HVD1040 as a VCC/2 common-mode bus voltage bias for a
split-termination network.
The SN65HVD1040 is characterized for operation from –40°C to 125°C.
SN65HVD1040
TXD
GND
VCC
RXD
1
8
2
7
3
6
4
5
STB
CANH
CANL
SPLIT
ORDERING INFORMATION
(1)
2
PART NUMBER
DOMINANT
TIME-OUT
LOW-POWER
BUS MONITOR
PACKAGE (1)
MARKED
AS
SN65HVD1040
YES
YES
SOIC-8
VP1040
ORDERING NUMBER
SN65HVD1040D (rail)
SN65HVD1040DR (reel)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
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SLLS631B – MARCH 2007 – REVISED APRIL 2007
ABSOLUTE MAXIMUM RATINGS
(1)
VALUE
voltage (2)
VCC
Supply
VI(bus)
Voltage range at any bus terminal (CANH, CANL, SPLIT)
–0.3 V to 7 V
IO(OUT)
Receiver output current
Voltage input, transient
-20 mA to 20 mA
pulse (3),
(CANH, CANL, SPLIT)
Human Body Model
Human body model
ESD
–27 V to 40 V
(4)
Charged-device-model (5)
–200 V to 200 V
Bus terminals and GND
±12 kV
All pins
±4 kV
±1 kV
All pins
±200 V
Machine model
VI
Voltage input range (TXD, STB)
TJ
Junction temperature
(1)
(2)
(3)
(4)
(5)
–0.5 V to 6 V
–55°C to 170°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
Tested in accordance with ISO 7637, test pulses 1, 2, 3a, 3b, 5, 6 & 7.
Tested in accordance JEDEC Standard 22, Test Method A114-A.
Tested in accordance JEDEC Standard 22, Test Method C101.
RECOMMENDED OPERATING CONDITIONS
MIN
VCC
Supply voltage
VI or VIC
Voltage at any bus terminal (separately or common mode)
VIH
High-level input voltage
VIL
Low-level input voltage
VID
Differential input voltage
IOH
High-level output current
IOL
Low-level output current
tSS
Maximum pulse width to remain in standby
TJ
Junction temperature
(1)
MAX
UNIT
4.75
5.25
V
–12 (1)
12
V
2
5.25
V
0
0.8
V
–6
6
V
TXD, STB
Driver
NOM
–70
Receiver
mA
–2
Driver
70
Receiver
2
–40
mA
0.7
µs
150
C
The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
SUPPLY CURRRENT
over operating free-air temperature range (unless otherwise noted)
PARAMETER
ICC
Supply current, VCC
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Dominant
VI = 0 V, 60 Ω Load, STB at 0 V
50
70
Recessive
VI = VCC, STB at 0 V
6
10
Standby
STB at VCC, VI = VCC
5
12
µA
MAX
UNIT
mA
DEVICE SWITCHING CHARACTERISTICS
over recommended operating conditiions (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
tloop1
Total loop delay, driver input to receiver output, Recessive to Dominant
tloop2
Total loop delay, driver input to receiver output, Dominant to Recessive
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STB at 0 V,
See Figure 9
MIN
TYP
90
230
90
230
ns
3
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SLLS631B – MARCH 2007 – REVISED APRIL 2007
DRIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditiions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
CANH
VI = 0 V, STB at 0 V, RL = 60 Ω, See Figure 1 and
Figure 2
MIN TYP (1)
2.9
3.4
MAX
4.5
UNIT
VO(D)
Bus output voltage
(Dominant)
VO(R)
Bus output voltage (Recessive)
VI = 3 V, STB at 0 V, See Figure 1 and Figure 2
3
V
VO
Bus output voltage (Standby)
RL = 60 Ω, STB at VCC, See Figure 1 and Figure 2
–0.1
0.1
V
VI = 0 V, RL = 60 Ω, STB at 0 V, See Figure 1 and
Figure 2, and Figure 3
1.5
3
VI = 0 V, RL = 45 Ω, STB at 0 V, See Figure 1 and
Figure 2
1.4
3
0.9×VCC
VCC 1.1×VCC
–0.012
0.012
–0.5
0.05
VOD(D)
CANL
Differential output voltage (Dominant)
VSYM
Output symmetry (Dominant or
Recessive) [ VO(CANH) + VO(CANL) )
VOD(R)
VI = 3 V, RL = 60 Ω, STB at 0 V, See Figure 1 and
Differential output voltage (Recessive) Figure 2
VI = 3 V, STB at 0 V, No Load
VOC(D)
Common-mode output voltage
(Dominant)
STB at 0 V, See Figure 2 and Figure 13
0.8
2
1.75
2.5
V
V
2
2.3
V
V
3
STB at 0 V, See Figure 8
V
VOC(pp)
Peak-to-peak common-mode output
voltage
IIH
High-level input current, TXD input
VI at VCC
–2
2
µA
IIL
Low-level input current, TXD input
VI at 0 V
–50
–10
µA
IO(off)
Power-off TXD Leakage current
VCC at 0 V, TXD at 5 V
1
µA
0.3
VCANH = –12 V, CANL Open, See Figure 12
IOS(ss)
Short-circuit steady-state output
current
–120
VCANH = 12 V, CANL Open, See Figure 12
VCANL = –12 V, CANH Open, See Figure 12
0.36
–1
VCANL = 12 V, CANH Open, See Figure 12
CO
(1)
Output capacitance
–72
1
–0.5
71
mA
120
See Input capacitance to ground in RECEIVER
ELECTRICAL CHARACTERISTICS.
All typical values are at 25 C with a 5-V supply.
DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
4
TEST CONDITIONS
MIN
TYP
MAX
tPLH
Propagation delay time, low-to-high-level output
25
65
120
tPHL
Propagation delay time, high-to-low-level output
25
45
120
tsk(p)
Pulse skew (|tPHL– tPLH|)
tr
Differential output signal rise time
tf
Differential output signal fall time
ten
Enable time from silent mode to dominant
See Figure 7
tdom
Dominant time-out
See Figure 10
STB at 0 V, See Figure 4
UNIT
25
ns
10
µs
700
µs
25
50
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300
450
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RECEIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Positive-going input threshold
voltage
VIT+
High-speed
mode
MIN
TYP (1)
MAX
800
900
STB at 0 V, See Table 1
VIT–
Negative-going input threshold
voltage
Vhys
Hysteresis voltage (VIT+– VIT–)
VIT
Input threshold voltage
VOH
High-level output voltage
IO = –2 mA, See Figure 6
VOL
Low-level output voltage
IO = 2 mA, See Figure 6
II(off)
Power-off bus input current
CANH or CANL = 5 V, VCC at 0 V,
TXD at 0 V
IO(off)
Power-off RXD leakage current
VCC at 0 V, RXD at 5 V
CI
Input capacitance to ground, (CANH or CANL)
TXD at 3 V, VI = 0.4 sin (4E6πt) + 2.5 V
CID
Differential input capacitance
TXD at 3 V, VI = 0.4 sin (4E6πt)
RID
Differential input resistance
TXD at 3 V, STD at 0 V
30
RIN
Input resistance, (CANH or CANL)
TXD at 3 V, STD at 0 V
15
30
40
RI(m)
Input resistance matching
[1 – (RIN (CANH) / RIN (CANL))] x 100%
VCANH = VCANL
–3%
0%
3%
(1)
Standby mode
UNIT
500
650
STB at VCC
100
125
STB at VCC
500
mV
1150
4
4.6
0.2
V
0.4
V
5
µA
20
µA
20
pF
10
pF
80
kΩ
All typical values are at 25 C with a 5-V supply.
RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditiions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tpLH
Propagation delay time, low-to-high-level output
tpHL
Propagation delay time, high-to-low-level output
tr
Output signal rise time
tf
Output signal fall time
tBUS
Dominant time required on bus for wake-up from
standby (1)
(1)
STB at 0 V, TXD at 3 V, See
Figure 6
MIN
TYP
MAX
60
100
130
45
70
130
8
UNIT
ns
8
STB at VCC Figure 11
0.7
5
µs
The device under test shall not signal a wake-up condition with dominant pulses shorter than tBUS (min) and shall signal a wake-up
condition with dominant pulses longer than tBUS (max). Dominant pulses with a length between tBUS (min) and tBUS (max) may lead to a
wake-up.
SPLIT-PIN CHARACTERISTICS
over recommended operating conditiions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VO
Output voltage
–500 µA < IO < 500 µA
IO(stb)
Standby mode leakage current
STB at 2 V, –12 V ≤ VO ≤ 12 V
MIN
TYP
MAX
0.3×VCC
0.5×VCC
0.7×VCC
V
5
µA
–5
UNIT
STB-PIN CHARACTERISTICS
over recommended operating conditiions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IIH
High level input current
STB at 2 V
–10
0
µA
IIL
Low level input current
STB at 0 V
–10
0
µA
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PARAMETER MEASUREMENT INFORMATION
Dominant
IO(CANH)
II
TXD
VOD
3.5 V
Recessive
RL VO(CANH)
2.5 V
VO(CANH) + VO(CANL)
VI
2
STB
VO(CANH)
1.5 V
VO(CANL)
VOC
IO(CANL)
VO(CANL)
Figure 1. Driver Voltage, Current, and Test Definition
CANH
0V
TXD
VOD
Figure 2. Bus Logic State Voltage Definitions
330 +1%
60 +1%
+
_
STB
CANL
−2 V 3 VTEST 3 7 V
330 +1%
Figure 3. Driver VOD Test Circuit
CANH
VCC
TXD
RL = 60 W
VO
+1‘%
VI
(see Note A)
VCC
2
VI
STB
0V
CL = 100 pF +20%
(see Note B)
tPLH
tPHL
90%
0.9 V
VO
CANH
CANH
RXD
V I (CANH)
IO
V ID
VI(CANH) + VI(CANL)
2
V I (CANL)
CANL
VO
Figure 5. Receiver Voltage and Current Definitions
6
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VO(R)
tf
Figure 4. Driver Test Circuit and Voltage Waveforms
V O(D)
0.5 V
10%
tr
VIC =
VCC
2
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PARAMETER MEASUREMENT INFORMATION (continued)
3.5 V
CANH
1.5 V
CANL
1.5 V
IO
VI
(see Note A)
2.4 V
2V
VI
RXD
t PLH
CL = 15 pF 20%
(see Note B)
VO
STB
t PLH
V OH
90%
0.7 VCC
0.3 VCC
VO
10%
tf
tr
VOL
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle, tr ≤
6 ns, tf ≤ 6ns, ZO = 50 Ω.
B.
CL includes instrumentation and fixture capacitance within 20%.
Figure 6. Receiver Test Circuit and Voltage Waveforms
Table 1. Differential Input Voltage Threshold Test
INPUT
OUTPUT
VCANH
VCANL
|VID|
–11.1 V
–12 V
900 mV
L
R
12 V
11.1 V
900 mV
L
–6 V
–12 V
6V
L
12 V
6V
6V
L
–11.5 V
–12 V
500 mV
H
12 V
11.5 V
500 mV
H
–12 V
–6 V
6V
H
6V
12 V
6V
H
Open
Open
X
H
VOL
VOH
DUT
CANH
TXD
C
L
VCC
60 W 1%
VI
50%
0V
STB
CANL
NOTE: CL = 100 pF
Includes Instrumentation
and Fixture Capacitance
Within ±20%
RXD
+
VO
−
VOH
50%
VO
VOL
ten
15 pF 20%
Figure 7. ten Test Circuit and Voltage Waveforms
CANH
27 W +1%
TXD
V
I
CANL
STB
A.
27 W +1%
VOC(PP)
47 nF
+20%
VOC =
VO (CANH) + VO (CANL)
2
VOC
All VI input pulses are from 0 V to VCC and supplied by a generator having the following characteristics: tr or tf ≤ 6 ns.
Pulse Repetition Rate (PRR) = 125 kHz, 50% duty cycle.
Figure 8. Peak-to-Peak Common Mode Output Voltage Test and Waveform
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DUT
CANH
TXD
C
L
STB
A.
TXD
Input
CANL
50%
0V
tloop2
NOTE: CL = 100 pF
Includes Instrumentation
and Fixture Capacitance
Within ±20%
RXD
+
VO
−
VCC
60 W 1%
tloop1
VOH
RXD Output
50%
50%
VOL
15 pF 20%
All VI input pulses are from 0 V to VCC and supplied by a generator with the following characteristics: tr or tf ≤ 6 ns.
Pulse Repetition Rate (PRR) = 125 kHz, 50% duty cycle.
Figure 9. tloop Test Circuit and Voltage Waveforms
CANH
VCC
VI
TXD
RL = 60 W +1%
0V
VO
CL
(see Note B)
VI
(see Note A)
VOD(D)
VO
CANL
STB
900 mV
500 mV
0V
tdom
A.
All VI input pulses are from 0 V to VCC and supplied by a generator with the following characteristics: tr or tf ≤ 6 ns.
Pulse Repetition Rate (PRR) = 500 Hz, 50% duty cycle.
B.
CL = 100 pF includes instrumentation and fixture capacitance within 20%.
Figure 10. Dominant Time-Out Test Circuit and Waveform
CANH
VCC
3.5 V
STB
VI
IO
RXD
2.65 V
VI
(see Note A)
1.5 V
CANL
1.5 V
(see Note B)
CL
VO
0.7 s
tBUS
VOH
VO
400 mV
V OL
A.
For VI bit width ≤ 0.7 µs, VO = VOH. For VII bit width ≥ 5 µs, VO = VOL. VI input pulses are supplied from a generator
with the following characteristics; tr or tf ≤ 6 ns. Pulse Repetition Rate (PRR) = 50 Hz, 30% duty cycle.
B.
CL = 15 pF includes instrumentation and fixture capacitance within 20%.
Figure 11. tBUS Test Circuit and Waveform
8
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IOS
IOS(SS)
IOS(P)
CANH
TXD
200 ms
0 V or VCC
0V
STB
CANL
VIN
12 V
−12 V or 12 V
Vin
0V
10 ms
or
0V
Vin
−12 V
Figure 12. Driver Short-Circuit Current Test and Waveform
CANH
60 W ± 1%
TXD
VI
60 W ± 1%
STB
CANL
V O (CANL)
VSYM =
4.7 nF
± 20%
+VO
VO(CANH)
(CANL)
VO (CANH)
Figure 13. Driver Output Symmetry Test Circuit
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DEVICE INFORMATION
Table 2. DRIVER FUNCTION TABLE (1)
INPUTS
(1)
OUTPUTS
BUS STATE
TXD
STB
CANH
L
L
H
CANL
L
DOMINANT
H
L
Z
Z
RECESSIVE
Open
X
Z
Z
RECESSIVE
X
H or Open
Z
Z
RECESSIVE
H = high level; L = low level; X = irrelevant; Z = high impedance
Table 3. RECEIVER FUNCTION TABLE (1)
DIFFERENTIAL INPUTS
VID = CANH - CANL
(1)
STB
OUTPUT
RXD
BUS STATE
VID ≥ 0.9 V
L
L
DOMINANT
VID ≥ 1.15 V
H or Open
L
DOMINANT
0.5 V < VID < 0.9 V
X
?
?
VID ≤ 0.5 V
X
H
RECESSIVE
Open
X
H
RECESSIVE
H = high level; L = low level; X = irrelevant; ? = indeterminate; Z =
high impedance
THERMAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
°C/W
High-K Thermal Resistance
131
°C/W
Thermal Resistance, Junction-to-Air
θJB
Thermal Resistance,
Junction-to-Board
53
θJC
Thermal Resistance,
Junction-to-Case
79
PD
Device Power Dissipation
TJS
Junction Temperature, Thermal Shutdown
10
UNIT
211
θJA
(1)
(2)
MAX
Low-K Thermal Resistance (1)
RL = 60 Ω, S at 0 V,
Input to TXD a 500kHz 50% duty-cycle square wave
(2)
112
°C/W
170
190
Tested in accordance with the Low-K or High-K thermal metric definitions of EIA/JESD51-3 for leaded surface mount packages.
Extended operation in thermal shutdown may affect device reliability, see the Application Information section.
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°C
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DEVICE INFORMATION
Table 4. Parametric Cross Reference With the TJA1040
TJA1040 (1)
PARAMETER
HVD10xx
TJA1040 DRIVER SECTION
VIH
High-level input voltage
Recommended VIH
VIL
Low-level input voltage
Recommended VIL
IIH
High-level input current
Driver IIH
IIL
Low-level input current
Driver IIL
Vth(dif)
Differential input voltage
Receiver VIT and recommended VID
Vhys(dif)
Differential input hysteresis
Receiver Vhys
VO(dom)
Dominant output voltage
Driver VO(D)
VO(reces)
Recessive output voltage
Driver VO(R)
Vi(dif)(th)
Differential input voltage
Receiver VIT and recommended VID
VO(dif0(bus)
Differential bus voltage
Driver VOD(D) and VOD(R)
ILI
Power-off bus input current
Receiver II(off)
IO(SC)
Short-circuit output current
Driver IOS(SS)
Ri(cm)
CANH, CANL input resistance
Receiver RIN
Ri(def)
Differential input resistance
Receiver RID
Ri(cm) (m)
Input resistance matching
Receiver RI (m)
Ci(cm)
Input capacitance to ground
Receiver CI
Ci(dif)
Differential input capacitance
Receiver CID
TJA1040 BUS SECTION
TJA1040 RECEIVER SECTION
IOH
High-level output current
Recommended IOH
IOL
Low-level output current
Recommended IOL
TJA1040 SPLIT PIN SECTION
VO
Reference output voltage
VO
TJA1040 TIMING SECTION
td(TXD-BUSon)
Delay TXD to bus active
Driver tPLH
td(TXD-BUSoff)
Delay TXD to bus inactive
Driver tPHL
td(BUSon-RXD)
Delay bus active to RXD
Receiver tPHL
td(BUSoff-RXD)
Delay bus inactive to RXD
Receiver tPLH
tPD(TXD–RXD)
Prop delay TXD to RXD
Device tLOOP1 and tLOOP2
td(stb-norm)
Enable time from standby to dominant
Driver ten
VIH
High-level input voltage
Recommended VIH
VIL
Low-level input voltage
Recommended VIL
IIH
High-level input current
IIH
IIL
Low-level input current
IIL
TJA1040 STB PIN SECTION
(1)
From TJA1040 Product Specification, Philips Semiconductors, 2003 February 19.
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Equivalent Input and Output Schematic Diagrams
TXD Input
RXD Output
Vcc
Vcc
15 W
4. 3 k W
Output
Input
6V
6V
CANH Input
CANL Input
Vcc
Vcc
10 k W
10 k W
Input
20 k W
Input
10 kW
40 V
40 V
10 k W
CANH and CANL Outputs
STB Input
Vcc
Vcc
4. 3 k W
Output
Input
40 V
6V
SPLIT Output
Vcc
2kW
Output
2k W
40 V
12
20 k W
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SN65HVD1040
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SLLS631B – MARCH 2007 – REVISED APRIL 2007
TYPICAL CHARACTERISTICS
150
145
140
DOMINANT-TO-RECESSIVE LOOP TIME
vs
FREE-AIR TEMPERATURE (across VCC)
t LOOP2 − Dominant-to-Recessive Loop Time − ns
t LOOP1− Recessive-to-Dominant Loop Time − ns
RECESSIVE-TO-DOMINANT LOOP TIME
vs
FREE-AIR TEMPERATURE (across VCC)
S at 0 V,
RL = 60 W,
CL = 100 pF,
Air Flow at 7 cf/m,
TXD Input is a 125 kHz,
50% Duty Cycle Pulse
VCC = 4.75 V
135
130
VCC = 5 V
125
VCC = 5.25 V
120
−40
0
25
70
TA − Free-Air Temperature − °C
160
S at 0 V,
RL = 60 W,
CL = 100 pF,
Air Flow at 7 cf/m,
TXD Input is a 125 kHz,
50% Duty Cycle Pulse
VCC = 5.25 V
155
VCC = 5 V
150
145
VCC = 4.75 V
140
−40
0
25
70
125
TA − Free-Air Temperature − °C
Figure 14.
Figure 15.
SUPPLY CURRENT (RMS)
vs
SIGNALING RATE
DRIVER LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
90
TA = 255C,
VCC = 5 V,
S at 0 V,
RL = 60 W,
RXD = 15 pF
80
I OL − Low-Level Output Current − mA
I CC − RMS Supply Current − mA
40
165
125
50
45
170
35
30
25
20
15
10
5
70
60
50
40
30
20
TA = 255C,
VCC = 5 V,
S at 0 V,
TXD Input is a 125 kHz
1% Duty Cycle Pulse
10
0
0
200
400
500
600
800
Signaling Rate − kbps
1000
−10
Figure 16.
0
1
2
3
4
5
VOCANL − Low-Level Output Voltage − V
Figure 17.
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SN65HVD1040
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SLLS631B – MARCH 2007 – REVISED APRIL 2007
TYPICAL CHARACTERISTICS (continued)
DRIVER HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
TA = 25 C,
VCC = 5 V,
S at 0 V,
TXD Input is a 125 kHz
1% Duty Cycle Pulse
-70
-60
-50
-40
-30
-20
-10
3
Dominant Driver Differential Output Voltage − V
-0
1
S at 0 V,
RL = 60 W,
Air Flow at 7 cf/m,
TXD Input is a 125 kHz
1% Duty Cycle Pulse
0.5
0
25
70
TA − Free-Air Temperature − °C
Figure 18.
Figure 19.
DRIVER OUTPUT CURRENT
vs
SUPPLY VOLTAGE
RECEIVER OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
VIT+
VIT−
5
30
25
20
15
10
VCM = 12 V
4
VCM = 2.5 V
3
VCM = −12 V
2
TA = 255C,
VCC = 5 V,
S at 0 V,
RXD = 15 pF
1
VID − Differential Input Voltage − V
Figure 20.
Figure 21.
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0.65
0.60
0.70
5.25
0.75
5
0.85
3.5
4
4.5
VCC − Supply Voltage − V
0.80
3
0.85
1
2
0.80
−1
1
0.70
0
5
0
14
125
6
TA = 255C,
VCC = 5 V,
S at 0 V,
RL = 60 W,
TXD Input is a 125 kHz
1% Duty Cycle Pulse
0.75
35
VCC = 4.75 V
1.5
0.65
40
2
−40
VO − Receiver Output Voltage − V
I O − Differential Driver Output Current − mA
45
VCC = 5.25 V
0
0
1
2
3
4
5
VOCANH − High-Level Output Voltage − V
50
VCC = 5 V
2.5
0.60
I OH − High-Level Output Current − mA
-80
DRIVER DIFFERENTIAL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE (across VCC)
SN65HVD1040
www.ti.com
SLLS631B – MARCH 2007 – REVISED APRIL 2007
TYPICAL CHARACTERISTICS (continued)
TYPICAL ELECTROMAGNETIC EMISSIONS
UP TO 50 MHZ (Peak Amplitude)
TYPICAL ELECTROMAGNETIC
IMMUNITY PERFORMANCE
80
dBm
DB mV
60
40
20
0
0.1
Figure 22. Frequency Spectrum of Common-Mode
Emissions
1
10
f − Frequency − MHz
100
1000
Figure 23. Direct Power Injection (DPI) Response vs
Frequency
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SN65HVD1040
www.ti.com
SLLS631B – MARCH 2007 – REVISED APRIL 2007
APPLICATION INFORMATION
CAN Basics
The basics of arbitration require that the receiver at the sending node designate the first bit as dominant or
recessive after the initial wave of the first bit of a message travels to the most remote node on a network and
back again. Typically, this “sample” is made at 75% of the bit width, and within this limitation, the maximum
allowable signal distortion in a CAN network is determined by network electrical parameters.
Factors to be considered in network design include the approximately 5 ns/m propagation delay of typical
twisted-pair bus cable; signal amplitude loss due to the loss mechanisms of the cable; and the number, length,
and spacing of drop-lines (stubs) on a network. Under strict analysis, variations among the different oscillators in
a system also need to be accounted for with adjustments in signaling rate and stub and bus length. Table 5 lists
the maximum signaling rates achieved with the SN65HVD1040 with several bus lengths of category 5, shielded
twisted pair (CAT 5 STP) cable.
Table 5. Maximum Signaling Rates for Various Cable
Lengths
Bus Length (m)
Signaling Rate (kbps)
30
1000
100
500
250
250
500
125
1000
62.5
The ISO 11898 Standard specifies a maximum bus length of 40 m and maximum stub length of 0.3 m with a
maximum of 30 nodes. However, with careful design, users can have longer cables, longer stub lengths, and
many more nodes to a bus. (Note: Non-standard application may come with a trade-off in signaling rate.) A large
number of nodes requires a transceiver with high input impedance such as the HVD1040.
The Standard specifies the interconnect to be a single twisted-pair cable (shielded or unshielded) with 120 Ω
characteristic impedance (ZO). Resistors equal to the characteristic impedance of the line terminate both ends of
the cable to prevent signal reflections. Unterminated drop-lines connect nodes to the bus and should be kept as
short as possible to minimize signal reflections.
Connectors, while not specified by the standard should have as little effect as possible on standard operating
parameters such as capacitive loading. Although unshielded cable is used in many applications, data
transmission circuits employing CAN transceivers are usually used in applications requiring a rugged
interconnection with a wide common-mode voltage range. Therefore, shielded cable is recommended in these
electronically harsh environments, and when coupled with the Standard’s –2-V to 7-V common-mode range of
tolerable ground noise, helps to ensure data integrity. The HVD1040 enhances the Standard’s insurance of data
integrity with an extended –12 V to 12 V range of common-mode operation.
16
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SN65HVD1040
www.ti.com
SLLS631B – MARCH 2007 – REVISED APRIL 2007
NOISE MARGIN
900 mV Threshold
75% SAMPLE POINT
RECEIVER DETECTION WINDOW
500 mV Threshold
NOISE MARGIN
ALLOWABLE JITTER
Figure 24. Typical CAN Differential Signal Eye-Pattern
An eye pattern is a useful tool for measuring overall signal quality. As displayed in Figure 25, the differential
signal changes logic states in two places on the display, producing an “eye.” Instead of viewing only one logic
crossing on the scope, an entire “bit” of data is brought into view. The resulting eye pattern includes all of the
effects of systemic and random distortion, and displays the time during which a signal may be considered valid.
The height of the eye above or below the receiver threshold voltage level at the sampling point is the noise
margin of the system. Jitter is typically measured at the differential voltage zero-crossing during the logic state
transition of a signal. Note that jitter present at the receiver threshold voltage level is considered by some to be a
more effective representation of the jitter at the input of a receiver.
As the sum of skew and noise increases, the eye closes and data is corrupted. Closing the width decreases the
time available for accurate sampling, and lowering the height enters the 900 mV or 500 mV threshold of a
receiver.
Different sources induce noise onto a signal. The more obvious noise sources are the components of a
transmission circuit themselves; the signal transmitter, traces and cables, connectors, and the receiver. Beyond
that, there is a termination dependency, cross-talk from clock traces and other proximity effects, VCC and ground
bounce, and electromagnetic interference from near-by electrical equipment.
The balanced receiver inputs of the HVD1040 mitigate most all sources of signal corruption, and when used with
a quality shielded twisted-pair cable, help insure data integrity.
CANH
Bus Lines -- 40 m max
120 W
120 W
Stub Lines -- 0.3 m max
CANL
5V
SPLIT
Vcc
0.1m F
SN65HVD1040
STB
GND
D
CANTX
5V
SPLIT
R
CANRX
3.3 V
Vcc
0.1mF
SN65HVD1040
STB
Vref
GND
D
CANTX
Vcc
0.1mF
SN65HVD230
Rs
GND
R
D
CANRX
CANTX
R
CANRX
TMS320LF243
TMS320LF243
TMS320LF2407A
Sensor, Actuator, or Control
Equipment
Sensor, Actuator, or Control
Equipment
Sensor, Actuator, or Control
Equipment
Figure 25. Typical HVD1040 Application
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17
SN65HVD1040
www.ti.com
SLLS631B – MARCH 2007 – REVISED APRIL 2007
Thermal Shutdown
The SN65HVD1040 has a thermal shutdown that turns off the driver outputs when the junction temperature
nears 190°C. This shutdown prevents catastrophic failure from bus shorts, but does not protect the circuit from
possible damage. The user should strive to maintain recommended operating conditions, and not exceed
absolute maximum ratings at all times. If the SN65HVD1040 is subjected to many or long durations faults that
can put the device into thermal shutdown, it should be replaced.
18
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PACKAGE OPTION ADDENDUM
www.ti.com
7-May-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN65HVD1040D
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD1040DG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD1040DR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD1040DRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
Device
SN65HVD1040DR
17-May-2007
Package Pins
D
8
Site
Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
TAI
330
12
6.4
5.2
2.1
8
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm)
Width (mm)
Height (mm)
SN65HVD1040DR
D
8
TAI
346.0
346.0
29.0
Pack Materials-Page 2
W
Pin1
(mm) Quadrant
12
PKGORN
T1TR-MS
P
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