RF2162 Preliminary 2 3V 900MHZ LINEAR AMPLIFIER Typical Applications • Spread-Spectrum Systems • 3V JCDMA/TACS Cellular Handsets • CDPD Portable Data Cards • 3V TDMA/AMPS Cellular Handsets • Portable Battery-Powered Equipment Product Description 2 0.45 0.28 3.75 The RF2162 is a high-power, high-efficiency linear amplifier IC targeting 3V handheld systems. The device is manufactured on an advanced Gallium Arsenide Heterojunction Bipolar Transistor (HBT) process, and has been designed for use as the final RF amplifier in dual-mode 3V CDMA/AMPS hand-held digital cellular equipment, spread-spectrum systems, and other applications in the 800MHz to 960MHz band. The RF2162 has an analog bias control voltage to maximize efficiency. The device is self-contained with 50Ω input and the output can be easily matched to obtain optimum power, efficiency, and linearity characteristics. The device is packaged in a compact 4mmx4mm, 16-pin, leadless chip carrier. Optimum Technology Matching® Applied VCC1 VCC BIAS Si CMOS VCC1 SiGe HBT GND GaAs MESFET 3.75 + 1 16 15 14 1 1.60 4.00 12° 1.50 SQ INDEX AREA 3 3.20 0.75 0.65 4.00 1.00 0.90 0.05 0.00 NOTES: 1 Shaded Pin is Lead 1. 2 Dimensions in mm. Dimension applies to plated terminal and is measured between 0.10 mm and 0.25 mm from terminal tip. The terminal #1 identifier and terminal numbering convention 3 shall conform to JESD 95-1 SPP-012. Details of terminal #1 identifier are optional, but must be located within the zone indicated. The identifier may be either a mold or marked feature. Pins 1 and 9 are fused. Package Warpage: 0.05 max. Package Style: LCC, 16-Pin, 4x4 Features • Single 3V Supply • 29dBm Linear Output Power 2F0 ü Si Bi-CMOS GaAs HBT 1 0.80 TYP 0.75 0.50 4 5 Si BJT 2 • 29dB Linear Gain 13 GND 2 12 RF OUT GND 3 11 RF OUT RFIN 4 10 RF OUT • 35% Linear Efficiency • On-board Power Down Mode • 800MHz to 960MHz Operation 9 GND 8 BIAS GND 7 VREG2 6 VMODE VREG1 5 Functional Block Diagram Rev A17 011011 Ordering Information RF2162 RF2162 PCBA 3V 900MHz Linear Amplifier Fully Assembled Evaluation Board RF Micro Devices, Inc. 7628 Thorndike Road Greensboro, NC 27409, USA Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com 2-205 POWER AMPLIFIERS • 3V CDMA/AMPS Cellular Handsets RF2162 Preliminary Absolute Maximum Ratings Parameter Rating Unit +8.0 +4.5 +3.0 VDC VDC VDC +3.0 +12 -30 to +110 -30 to +150 Modified JEDEC Level 2 VDC dBm °C °C Supply Voltage (RF off) Supply Voltage (POUT ≤31dBm) Mode Voltage (VMODE) POWER AMPLIFIERS 2 Control Voltage (VPD) Input RF Power Operating Case Temperature Storage Temperature Moisture Sensitivity Parameter Specification Min. Typ. Max. Caution! ESD sensitive device. RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s). Unit T=25°C, VCC =3.4V, Freq=824MHz to 849MHz unless otherwise specified Overall Usable Frequency Range Typical Frequency Range Linear Gain Second Harmonic (including second harmonic trap) Max CW Output Power Total Efficiency (AMPS mode) Maximum Linear Output Power (CDMA Modulation) Total Linear Efficiency Adjacent Channel Power Rejection 800 28 960 824-849 29 -30 31 31.5 50 29 30 Noise Power Maximum Linear Output Power (CDMA Modulation) Total Efficiency (AMPS mode) Max CW Output Power Total Linear Efficiency Adjacent Channel Power Rejection Condition dBm % dBm 35 -46 -44 % dBc -58 -90 -56 -89 dBc dBm 50 30.5 36 -46 -58 <2:1 Input VSWR Output Load VSWR ACPR @ 885kHz dBm ACPR @1980kHz VCC =3.4V; BW =30kHz; RX Band NF measure from TX center band to RX center band. VCC =3.0V -44 % dBm % dBc ACPR @ 885kHz -56 dBc ACPR @ 1980kHz 29 30 30 MHz MHz dB dBc 31 10:1 No damage. TDMA Linear Output Power Linear ACP Linear ALT CP Efficiency 45 30 -29 -49 46 dBm -28 -48 30kHZ offset 60kHZ offset O/P=30dBm Power Supply Power Supply Voltage Idle Current VREG Current Turn On/Off time Total Current (Power down) VREG “Low” Voltage VREG “High” Voltage VMODE Bias Control Voltage Range 2-206 3.0 2.7 3.4 135 10 0 2.8 0 to 2.5 4.5 200 15 <100 10 0.2 2.9 V mA mA ns µA V V V VMODE =0V to 0.5V Total pins 6 and 7, VREG =2.8V VPD =Low Rev A17 011011 RF2162 Preliminary Function GND 2 GND1 3 4 GND1 RF IN Description Interface Schematic Ground connection. Connect to package base ground. This ground should be isolated from the backside ground contact on top metal layer. Ground for stage 1. Keep traces physically short and connect immediately to ground plane for best performance. This ground should be isolated from the backside ground contact on top metal layer. Same as Pin 2. RF input. An external DC blocking capacitor is required if this port is connected to a DC path to ground or a DC voltage. 2 VCC1 POWER AMPLIFIERS Pin 1 RF IN From Bias Stages GND1 5 VREG1 6 VMODE 7 VREG2 8 9 GND GND 10 RF OUT Enable voltage for first stage. When this pin is “low”, all circuits are shut off. When this pin is 2.8V, all circuits are operating normally. VREG requires a regulated 2.8V for the amplifier to operate properly over all specified temperature and voltage ranges. A dropping resistor from a higher regulated voltage may be used to provide the required 2.8V. A 100pF high frequency bypass capacitor is recommended. This is an analog bias current control pin. The range is 0V for minimum bias to 3.0 for maximum bias. Enable voltage for second or output stage. When this pin is “low”, all circuits are shut off. When this pin is 2.8V, all circuits are operating normally. VREG requires a regulated 2.8V for the amplifier to operate properly over all specified temperature and voltage ranges. A dropping resistor from a higher regulated voltage may be used to provide the required 2.8V. A 100pF high frequency bypass capacitor is recommended. Bias circuitry ground. See application schematic. Ground connection. Connect to package base ground. This ground should be isolated from the backside ground contact on top metal layer. RF output and power supply for the output stage. The bias for the output stage is provided through this pin and pin 13. An external matching network is required to provide the optimum load impedance; see the application schematics for details. RF OUT From Bias Stages 11 12 13 RF OUT RF OUT 2FO 14 VCC BIAS 15 16 Pkg Base VCC1 VCC1 GND Rev A17 011011 Same as pin 10. See pin 10. Same as pin 10. Harmonic trap. This pin connects to the RF output but is used for providing a low impedance to the second harmonic of the operating frequency. An inductor or transmission line resonating with an on chip capacitor at 2fo is required at this pin. Power supply for bias circuitry. A 100pF high frequency bypass capacitor is recommended. Interstage tuning and bias supply for first stage. Interstage tuning and bias supply for first stage. Ground connection. The backside of the package should be soldered to a top side ground pad which is connected to the ground plane with multiple vias. The pad should have a short thermal path to the ground plane. 2-207 RF2162 Preliminary Application Schematic - US CDMA VCC 10 nF Bypassing for VCC 100 pF 2 100 pF POWER AMPLIFIERS Interstage tuning for centering frequency response TL3 100 pF To Vary Gain 100 pF 330 Ω RF IN 15 nH 16 15 TL4 14 13 2 12 3 11 4 10 5 Matching network for optimum input return loss 6 100 pF 1 nH 1.8 nH 1 2nd Harmonic Trap 7 0Ω 8 27 nH* TL1 TL2 1 pF 100 pF RF OUT 9.1 pF** 5.1 pF** Matching network for optimum load impedance 9 10 nH 100 pF Bias Return 0Ω 100 pF Bypassing for VREG1 and V REG2 VREG 1 kΩ VMODE * High Q inductor (i.e., Coilcraft 0805HQ-series). **High Q capacitors (i.e., Johanson C-series). 2-208 Rev A17 011011 RF2162 Preliminary Application Schematic - US TDMA P1-1 10 nF TL5 3.6 pF 1.5 nH 100 pF To Vary Gain 820 Ω RF IN 16 15 2 2nd Harmonic Trap POWER AMPLIFIERS Interstage tuning for centering frequency response 1 Bypassing for VCC 100 pF C30 100 pF TL7 14 13 2 12 3 11 16 nH* TL1 1.5 nH TL3 100 pF RF OUT 12 pF** 10 4 TL2 1 pF 4.7 pF** 100 pF 15 nH 5 Matching network for optimum input return loss 6 0Ω 7 8 9 Matching network for optimum load impedance 27 nH 100 pF Bias Return 100 pF Bypassing for VREG1 and VREG2 * L1 is a High Q inductor (i.e.,Coilcraft 0805HQ-series). **C1 and C14 are High Q capacitors (i.e., Johanson C-series). VREG 1 kΩ VMODE Rev A17 011011 2-209 RF2162 Preliminary Evaluation Board Schematic - US CDMA (Download Bill of Materials from www.rfmd.com.) C2 4.7 uF P1-1 2 C25 4.7 µF POWER AMPLIFIERS P1 P1-1 1 VCC 2 GND C28 10 nF C30 C6 100 pF C4 100 pF TL4 P2 1 VREG P2-2 2 VMODE TL3 1 C18 100 pF J1 RF IN L5 1 nH L3 1.8 nH P2-1 C5 100 pF 16 TL5 15 14 13 2 R2 L2 15 nH 12 3 11 4 10 5 C27 100 pF L1* 6 7 8 R3 0Ω TL1 TL2 C1** C17 1 pF C3 100 pF J4 RF OUT C14** 9 L4 18 nH 2162400B R4 0Ω C10 4.7 µF C13 100 pF * L1 is a High Q inductor (i.e., Coilcraft 0805HQ-series). **C1 and C14 are High Q capacitors (i.e., Johanson C-series). P2-1 R1 1 kΩ P2-2 Board CDMA (US) Transmission Line Length CDMA (US) 2-210 R2 (Ω) C30 (pF) C1 (pF) L1 (nH) C14 (pF) 330 100 9.1 27 5.1 TL1 TL2 TL3 TL4 TL5 175 mils 165 mils L=15 mils W=16 mils L=40-45 mils from L3 W=16 mils L=15-20 mils W=14 mils Rev A17 011011 RF2162 Preliminary Evaluation Board Schematic - US TDMA C2 4.7 uF C25 1 µF P1 P1-1 TL5 C28 10 nF 1 VCC 2 GND 2 POWER AMPLIFIERS P1-1 C30 C6 100 pF TL4 1 C18 100 pF J1 RF IN C55 3.6 pF L3 1.5 nH Er = 4.7 H = 14 mils t = 1 mil C5 100 pF 16 TL6 15 14 L2 15 nH 11 4 10 C27 100 pF R3 0Ω L1* 6 7 R1 1 kΩ 8 1 VREG P2-2 2 VMODE C17 1 pF 12 3 5 P2-1 TL7 13 2 R2 P2 C4 100 pF L10 1.5 nH TL2 TL1 TL3 J4 RF OUT C14** C1** 9 C3 100 pF L4 27 nH C13 100 pF 2162401B R4 0Ω P2-2 P2-1 * L1 is a High Q inductor (i.e., Coilcraft 0805HQ-series). **C1 and C14 are High Q capacitors (i.e., Johanson C-series). Board TDMA (US) R2 (Ω) 820 Transmission Line Length TL1 TL2 TL3 TL4 TL5 TL6 TL7 90 mils 82 mils 135 mils L=12 mils W=16 mils L=49 mils W=16 mils L=12 mils L=12 mils W=14 mils TDMA (US) Rev A17 011011 C30 (pF) 56 C1 (pF) 12 L1 (nH) 16 C14 (pF) 5.6 2-211 RF2162 Preliminary Evaluation Board Layout - CDMA Board Size 2.0" x 2.0" Board Thickness 0.031”, Board Material FR-4 POWER AMPLIFIERS 2 2-212 Rev A17 011011 RF2162 Preliminary Evaluation Board Layout - TDMA POWER AMPLIFIERS 2 Rev A17 011011 2-213 RF2162 Preliminary POWER AMPLIFIERS 2 2-214 Rev A17 011011