RF5176 Preliminary 2 3V W-CDMA POWER 1900MHZ/ 3V LINEAR POWER AMPLIFIER Typical Applications • Commercial and Consumer Systems • 3V 1920-1980MHz W-CDMA Handsets • Portable Battery-Powered Equipment 2 • Spread-Spectrum Systems Product Description 1.00 0.90 The RF5176 is a high-power, high-efficiency linear amplifier IC targeting 3V handheld systems. The device is manufactured on an advanced Gallium Arsenide Heterojunction Bipolar Transistor (HBT) process, and has been designed for use as the final RF amplifier in 3V CDMA-2000 and W-CDMA handsets as well as other applications in the 1850MHz to 2000MHz band. The device is self-contained, and the output can be easily matched to obtain optimum power, efficiency, and linearity characteristics over all recommended supply voltages. The device has a continuously variable bias circuit to allow idle current to be optimized for a given output power. 0.60 0.24 typ NC RF IN Si CMOS Q1B SiGe HBT NC ü GaAs MESFET NC Si Bi-CMOS GaAs HBT 20 19 18 17 16 VCC BIAS 2 14 NC Bias 13 VCC1 0.05 0.23 0.13 0.50 4 PLCS Dimensions in mm. Note orientation of package. NOTES: 1 Shaded lead is Pin 1. 2 Pin 1 identifier must exist on top surface of package by identification mark or feature on the package body. Exact shape and size is optional. 3 Dimension applies to plated terminal: to be measured between 0.02 mm and 0.25 mm from terminal end. 4 Package Warpage: 0.05 mm max. 5 Die Thickness Allowable: 0.305 mm max. Package Style: LCC, 20-Pin, 4x4 Features • 26dB Linear Gain • 40% Linear Efficiency • On-board Power Down Mode 12 VCC1 6 7 8 9 10 NC RF OUT RF OUT RF OUT 11 NC NC BIAS GND 5 Functional Block Diagram Rev A0 010910 0.75 0.50 12° MAX • 27dBm Linear Output Power 15 NC VS2 4 2.10 sq. 3 0.20 • Single 3V Supply VREG1 1 VREG2 3 0.65 0.30 4 PLCS Optimum Technology Matching® Applied Si BJT 4.00 sq. Ordering Information RF5176 RF5176 PCBA 3V W-CDMA Power 1900MHZ/ 3V Linear Power Amplifier Fully Assembled Evaluation Board RF Micro Devices, Inc. 7628 Thorndike Road Greensboro, NC 27409, USA Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com 2-197 POWER AMPLIFIERS • 3V 1850-1910MHz CDMA-2000 Handsets RF5176 Preliminary Absolute Maximum Ratings Parameter Supply Voltage (RF off) Supply Voltage (POUT ≤31dBm) Bias Voltage (VBIAS) POWER AMPLIFIERS 2 Control Voltage (VREG) Input RF Power Operating Case Temperature Storage Temperature Parameter Rating Unit +8.0 +5.0 +3.0 VDC VDC VDC +3.0 +6 -30 to +100 -30 to +150 VDC dBm °C °C Specification Min. Typ. Max. Caution! ESD sensitive device. RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s). Unit T=25°C, VCC =3.4V, Freq=1920MHz to 1980MHz, VREG =2.5V, unless otherwise specified Overall Usable Frequency Range Typical Frequency Range Condition 1850 Linear Gain Second Harmonic (including second harmonic trap) Third Harmonic Maximum Linear Output Power (W-CDMA Modulation) Total Linear Efficiency 1850 to 1910 1920 to 1980 26 -55 2000 MHz MHz MHz dB dBc -50 27 dBc dBm 40 Adjacent Channel Power Rejection@5MHz Adjacent Channel Power Rejection@10MHz Noise Power % -40 -38 dBc -50 -48 dBc -144 Input VSWR Output Load VSWR dBm/Hz POUT =27dBm POUT =27dBm, W-CDMA Modulation, 3GPP 3.2 03-00 DPCCH + 1 DPDCH POUT =27dBm, W-CDMA Modulation, 3GPP 3.2 03-00 DPCCH + 1 DPDCH POUT =+27dBm, Rx Band 2110MHz to 2170MHz < 2:1 5:1 No oscillations Power Supply Power Supply Voltage Idle Current VREG Current Turn On/Off time Total Current (Power down) VREG “Low” Voltage VREG “High” Voltage 2-198 3.0 3.4 80 10 0 2.5 5.0 10 0.2 V mA µA ns µA V V VREG =2.5V Total pins 1 and 3, VREG =2.5V VREG =Low See Alternative Biasing Network table following the application schematic. Rev A0 010910 RF5176 Preliminary Function VREG1 2 3 VCC BIAS VREG2 4 VS2 5 BIAS GND 6 7 8 NC NC RF OUT 9 10 11 12 RF OUT RF OUT NC VCC1 13 14 15 16 VCC1 NC NC RF IN 17 18 NC Q1B 19 20 Pkg Base NC NC GND Rev A0 010910 Description Interface Schematic Bias control for the first stage. Needs to be divided down from its nominal value of 2.5V using a resistive divider network of 240kΩ and 360kΩ. VREG1 and VREG2 may be adjusted to minimize idle current for a given output power. Alternative VREG voltages can be used as defined on the application schematic. Supply for bias circuits. 2 Bias control for the second stage. Needs to be divided down from its nominal value of 2.5V using a resistive divider network of 240kΩ and 240kΩ. Alternative VREG voltages can be used as defined on the application schematic. Second stage bias circuit source. For best linearity, decouple with bypassing capacitors of 15pF and 100nF. Connect to ground plane via a 15nH inductor. DC return for the second stage bias circuit. Not currently used. POWER AMPLIFIERS Pin 1 Not currently used. RF output and power supply for the final stage. This is the unmatched collector of the final stage. It requires an output matching network, including a DC blocking capacitor. Same as pin 8. Same as pin 8. Not currently used. Power supply for the first stage and interstage match. Requires a shunt capacitor of 12pF close to the pin for optimum match. Same as pin 12. Not currently used. Not currently used. RF input. Requires a blocking capacitor and shunt inductor to provide 2:1 VSWR. Not currently used. Base bias for first stage. For best linearity, decouple with 15pF and 100nF capacitors. Not currently used. Not currently used. Ground connection. The backside of the package should be soldered to a top side ground pad which is connected to the ground plane with multiple vias. The pad should have a short thermal path to the ground plane. 2-199 RF5176 Preliminary Application Schematic RF IN 100 nF 1.5 nH 2 5.6 pF R6 360 kΩ VREG R8 240 kΩ VCC BIAS 100 nF R5 240 kΩ 20 15 pF 18 17 16 1 15 2 14 3 R7 240 kΩ 19 W = 0.028" L = 0.060" Bias POWER AMPLIFIERS 15 pF 4 12 5 11 15 nH 6 VCC 10 nH 13 7 8 9 12 pF 10 nF 1 µF 10 nF 1 µF 4.7 µF 10 16 nH W = 0.028" L = 0.060" 3.6 pF VCC = 3.4 V VREG = 2.5 V VCC BIAS = 3.4 V 3 pF 15 pF W = 0.028" L = 0.120" 15 pF ER = 4.7 H = 14 mils RF OUT Alternative Biasing Networks for Various VREG Voltages VREG (V) R5 (1ST) kΩ R6 (1ST-GND) kΩ R7 (2ND-GND) kΩ R8 (2ND) kΩ 2.50 2.60 2.70 2.80 2.90 240 240 240 240 220 360 330 300 270 240 240 360 200 220 180 240 380 230 270 240 2-200 Rev A0 010910 RF5176 Preliminary Evaluation Board Schematic (Download Bill of Materials from www.rfmd.com.) J1 RF IN R6 360 kΩ P2 R8 240 kΩ C16 100 nF C7 15 pF 18 17 16 1 15 2 14 3 R7 240 kΩ 19 W = 0.028" L = 0.060" Bias P3 R5 240 kΩ 20 L1 1.5 nH C1 5.6 pF C2 15 pF 12 5 11 6 P1 1 VCC CON1 P2 P2 1 VREG CON1 P3 P3 1 VCCBIAS CON1 7 8 9 2 P4 1 GND CON1 13 4 L3 15 nH L4 10 nH P1 POWER AMPLIFIERS C3 100 nF P1 C4 12 pF C5 10 nF C6 + 1 µF C9 10 nF C10 + 1 µF C11 + 4.7 µF 10 L2 16 nH VCC = 3.4 V VREG = 2.5 V VCC BIAS = 3.4 V ER = 4.7 H = 14 mils C8 15 pF W = 0.028" L = 0.060" C12 3.6 pF C13 3 pF W = 0.028" L = 0.120" 15 pF J2 RF OUT Rev A0 010910 2-201 RF5176 Preliminary Evaluation Board Layout Board Size 2.0" x 2.0" Board Thickness 0.028”, Board Material FR-4, Multi-Layer Ground Plane at 0.014” POWER AMPLIFIERS 2 2-202 Rev A0 010910