RF5117 0 3V, 1.8GHz TO 2.8GHz LINEAR POWER AMPLIFIER Typical Applications • IEEE802.11B WLAN Applications • Commercial and Consumer Systems • IEEE802.11G WLAN Applications • Portable Battery-Powered Equipment • 2.5GHz ISM Band Applications • Spread-Spectrum and MMDS Systems Product Description -A- The RF5117 is a linear, medium-power, high-efficiency amplifier IC designed specifically for battery-powered WLAN applications such as PC cards, mini PCI, and compact flash applications. The device is manufactured on an advanced Gallium Arsenide Heterojunction Bipolar Transistor (HBT) process, and has been designed for use as the final RF amplifier in 2.5GHz WLAN and other spread-spectrum transmitters. The device is provided in a 3mmx3mm, 16-pin, leadless chip carrier with a backside ground. The RF5117 is designed to maintain linearity over a wide range of supply voltage and power output. 0.15 C A 2 PLCS 3.00 SQ. 1.50 TYP 0.80 0.65 12° MAX 2 PLCS 0.15 C B -B1.37 TYP 2 PLCS 0.15 C A -C- 2.75 SQ. 0.10 M C A B 0.60 0.24 TYP Shaded lead is pin 1. 0.30 0.18 1.65 SQ. 1.35 0.50 9 GaAs HBT GaAs MESFET Si Bi-CMOS SiGe HBT Si CMOS InGaP/HBT GaN HEMT SiGe Bi-CMOS SEATING PLANE Dimensions in mm. 0.23 0.13 4 PLCS Si BJT 0.05 0.01 2 PLCS 0.15 C B 0.45 0.00 4 PLCS Optimum Technology Matching® Applied 0.05 C 1.00 0.85 0.55 0.30 Package Style: QFN, 16-Pin, 3x3 Features • Single 3.3V Power Supply NC NC VCC VCC • +30dBm Saturated Output Power 16 15 14 13 • 26dB Small Signal Gain • High Linearity RF IN 1 12 RF OUT • 1800MHz to 2800MHz Frequency Range BIAS GND1 2 11 RF OUT • +17dBm PO, 11G, <3% EVM PWR SEN 3 10 RF OUT Bias 7 8 NC 6 9 NC BIAS GND 2 VREG1 5 VREG2 PWR REF 4 Functional Block Diagram Rev A7 041007 Ordering Information RF5117 RF5117 PCBA 3V, 1.8GHz to 2.8GHz Linear Power Amplifier Fully Assembled Evaluation Board RF Micro Devices, Inc. 7628 Thorndike Road Greensboro, NC 27409, USA Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com 2-573 RF5117 Absolute Maximum Ratings Parameter Supply Voltage Power Control Voltage (VREG) DC Supply Current Input RF Power Operating Ambient Temperature Storage Temperature Moisture sensitivity Parameter Rating Unit -0.5 to +6.0 -0.5 to 3.5 600 +10 -40 to +85 -40 to +150 JEDEC Level 3 VDC V mA dBm °C °C Specification Min. Typ. Max. Refer to “Handling of PSOP and PSSOP Products” on page 16-15 for special handling information. Caution! ESD sensitive device. RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s). Unit Condition T=25 °C, VCC =3.0V, VREG =2.7V, Freq=2450MHz, circuit per evaluation board schematic. Overall Frequency Range Maximum Linear Output Power 1800 to 2800 With 802.11B modulation (11Mbit/s) and meeting 802.11B spectral mask. VCC=3.0V VCC=5.0V 22 27 25 2.5 Linear Efficiency Error Vector Magnitude (EVM) Small Signal Gain Reverse Isolation Second Harmonic 802.11B Adjacent Channel Power Alternate Channel Power Isolation Input Impedance Input VSWR MHz 24 30 35 dBm dBm % % 26 28.5 -35 -38 -32 dB dB dBc dBc -56 45 50 2:1 -52 dBc dB Ω 2.7 3.0 V 0 0.5 V PO =17dBm, EVM increases over 11g, 54MBPS signal input PIN =-7dBm POUT =21dBm, VCC =3.0V POUT =21dBm, VCC =3.0V In “OFF” state, PIN =-5.0dBm With external matching With external matching Power Down VREG “ON” VREG “OFF” 2.1 Voltage supplied to control input; device is “ON” Voltage supplied to control input; device is “OFF” Power Supply Operating Voltage Current Consumption VREG Current (Total) 2-574 3.0 to 5.0 500 200 110 5 10 220 10 15 V mA mA mA mA mA At max output power POUT =21dBm, VCC =3.0V Idle current, VCC =3.0V, VREG =2.7V VCC =3.0V VCC =5.0V Rev A7 041007 RF5117 Pin 1 Function RF IN Description Interface Schematic RF input. Matching network with DC block required, see evaluation board schematic for details. VCC Bond Wire Inductance RF IN BIAS 2 3 BIAS GND1 PWR SEN Ground for first stage bias circuit. Not connected. See pin 5. The PWR SEN and PWR REF pins can be used in conjunction with an external feedback path to provide an RF power control function for the RF5117. The power control function is based on sampling the RF drive to the final stage of the RF5117. RF OUT PWR SEN PWR REF BIAS 4 5 PWR REF VREG1 Same as pin 3. See pin 3. This pin requires a regulated supply to maintain nominal bias current. VREG1 BIAS VREG2 BIAS GND1 6 7 VREG2 BIAS GND2 8 9 10 NC NC RF OUT 11 12 13 RF OUT RF OUT VCC 14 15 16 Pkg Base VCC NC NC GND Rev A7 041007 Same as pin 5. See pin 5. Ground for second stage bias circuit. For best performance connect to ground with a 10nH inductor. Not connected. See pin 5. BIAS GND2 Not connected. RF output and bias for the output stage. The power supply for the output transistor needs to be supplied to this pin. This can be done through a quarter-wave length microstrip line that is RF grounded at the other end, or through an RF inductor that supports the required DC curBIAS rents. Same as pin 10. See pin 10. Same as pin 10. See pin 10. Interstage match and bias for first stage output. Connect interstage matching capacitor to this pad with a short trace. Connect low-frequency bypass capacitors to this pin with a long trace. See evaluation board layout for details. Same as pin 13. See pin 1. RF OUT See pin 1. Not connected. Not connected. Ground connection. The backside of the package should be connected to the ground plane through a short path, i.e., vias under the device will be required. 2-575 RF5117 Theory of Operation and Application Information The RF5117 is a two-stage device with a nominal gain of 26dB in the 2.4GHz to 2.5GHz ISM band. The RF5117 is designed primarily for IEEE802.11B/11G WLAN applications where the available supply voltage and current are limited. This amplifier will operate to (and below) the lowest expected voltage made available by a typical PCMCIA slot in a laptop PC, and will maintain required linearity at decreased supply voltages. The RF5117 requires only a single positive supply of 3.0V nominal (or greater) to operate to full specifications. Power control is provided through two bias control input pins (VREG1 and VREG2), but in most applications these are tied together and used as a single control input. There is some external matching on the input and output of the part, thus allowing the part to be used in other applications outside the 2.4GHz to 2.5GHz ISM band (such as MMDS). Both the input and the output of the device need a series DC-blocking capacitor. In some cases, a capacitor used as a matching component can also serve as the blocking cap. The circuit used on the evaluation board is optimized for 3.0V nominal applications. For best results, the PA circuit layout from the evaluation board should be copied as closely as possible, particularly the ground layout and ground vias. Other configurations may also work, but the design process is much easier and quicker if the layout is copied from the RF5117 evaluation board. Gerber files of our designs can be provided upon request. The RF5117 is not a difficult part to implement, but care in circuit layout and component selection is always advisable when designing circuits to operate at 2.5GHz. The most critical passive components in the circuit are the input, interstage and output matching components (C1, C5, C7, and C11). In these cases, high-Q capacitors suitable for RF applications are used on our evaluation board (a BOM is available on request). High-Q parts are not required in every design, but it is very strongly recommended that the original design be implemented with the same or similar parts used on our evaluation board. Then, less costly components can be substituted in their place, making it easy to test the impact of cheaper components on performance. General RFMD experience has indicated that the slightly higher cost of better quality passive components is more than offset by the significant improvements in production yields in large-volume manufacturing. Using less costly components will typically result in a 1 to 2dB degradation in gain. The interstage matching capacitor, C11, along with the combined inductance of the internal bond wire, the short length of circuit board trace, and the parasitic inductance of this capacitor, tunes the peak of the small-signal gain response. The trace length between C11 and pins 13 and 14 should be kept as short as possible. In practice, VCC and the supply for the output stage bias will be tied to the same supply. It is important to isolate C11 from other RF and low-frequency bypass capacitors on this supply line. This can be accomplished using a suitably long transmission line which is RF shorted on the other end. Ideally the length of this line will be a quarter wavelength, but it only needs to be long enough so that the effects of other supply bypass capacitors on the interstage match are minimized. If board space is a concern, this isolation can also be accomplished with an RF choke inductor or ferrite bead. Additionally, a higher-value capacitor than shown on the application schematic can be used if bypass capacitors must be closer. A Smith Chart can be used to provide initial guidance for value selection and parts placement. Be aware of the self-resonant frequency (SRF) of higher-valued capacitors. The SRF must be above the frequency of operation. The output matching caps are C5 and C7. These are tuned along with the 50Ω transmission line segments TL1 and TL2, as shown on the evaluation board schematic. These segments should be duplicated as closely as possible. Due to variations in FR-4 characteristics and PCB manufacturer process variations, some benefit will be obtained from small adjustments to these transmission line lengths when the evaluation board layout is duplicated on another design. Prior to full rate manufacturing, the board layout of early prototypes should include some additional exposed ground areas around C5 and C7 to optimize this part of the circuit. In order to reduce component count, the output can also be tuned with a single capacitor. A Smith Chart can help determine the desired value and transmission line length, which can be similarly adjusted on the board prior to production. This will result in a slightly lower-bandwidth and more sensitive match, but in most applications the bandwidth is still sufficient. 2-576 Rev A7 041007 RF5117 Power sensing is implemented with the PWR SEN and PWR REF lines. The outputs of these pins are transistor collectors and need to be pulled up to the supply through a resistor. PWR REF provides an output current proportional to the output stage bias current, and PWR SEN provides an output current proportional to the total (RF and bias) current of the output stage. The pull-up resistors convert these currents to voltages, and the voltage difference between these two pins is proportional to the RF current. See the graph, “VREF -VSENSE versus POUT”, for the response of this signal. This difference signal can be fed to a power control circuit elsewhere in the end product, or it can be processed at the PA with additional circuitry and used to adjust the VREG voltage(s) to implement automatic level control. Contact RFMD Sales or Applications Engineering for additional data and guidance in using this feature. The RF5117 has primarily been characterized with a voltage on VREG1 and VREG2 of 2.7VDC. However, the RF5117 will operate from a wide range of control voltages. If you prefer to use a control voltage that is significantly different than 2.7VDC, contact RFMD Sales or Applications Engineering for additional data and guidance. Rev A7 041007 2-577 RF5117 Evaluation Board Schematic 2400MHz to 2483MHz C23 1 µF VCC + C14 1 nF *3 C11 6.8 pF Place C11 as close to chip as possible 50 Ω µstrip J1 RF IN C1 10 pF L3 1.2 nH JOH *2 15 14 1 12 2 11 10 Bias 4 R1 390 Ω C16 1 nF L1 12 nH 13 3 R2 390 Ω C15 1 nF PWR SENSE 16 C10 1 nF JOH Murata C17 2.7 pF C2 1 nF C22 10 µF C12 1 nF Part is Backside Grounded. 5 9 6 7 8 C9 10 pF 50 Ω µstrip C8 10 pF C7 1.5 pF JOH J2 RF OUT *1 TL1 = 149 mil (50 Ω) 5117400B P1 C3 1 nF PS REF Notes: 1. C7 - 149 mils from chip. 2. Pin 2 cut from ground. 3. C11 must be placed as close to chip as possible. * R3 4.3 kΩ VREG1 C13 1 nF VREG2 L2 10 nH P2 P1-1 1 PS REF 1 GND P1-2 2 PWR SENSE 2 GND 3 GND 3 VCC P1-4 4 VREG1 P1-5 5 VREG2 CON5 P2-3 CON3 P3-1 P3 1 VCC CON1 P4 1 GND CON1 2-578 Rev A7 041007 RF5117 Evaluation Board Layout Board Size 1.5” x 2.0” Board Thickness 0.031”, Board Material FR-4, Multi-Layer Rev A7 041007 2-579 RF5117 VCC = 3.0, PIN = -5.0 dBm 10.0 180.0 20.0 9.0 20.0 160.0 15.0 8.0 15.0 140.0 10.0 7.0 10.0 120.0 5.0 6.0 5.0 100.0 0.0 5.0 0.0 80.0 -5.0 4.0 -5.0 60.0 -10.0 3.0 -10.0 -15.0 2.0 40.0 IREG (Total) (mA) 25.0 POUT (dBm) ICC, ICQ (mA) IREG, POUT versus VREG (Typical) VCC = 3.0, PIN = -5.0 dBm 25.0 -15.0 Icq Icq Icc 20.0 -20.0 1.0 -20.0 Pout Pout 0.0 -25.0 1.0 1.5 2.0 2.5 0.0 3.0 -25.0 1.0 1.5 2.0 VREG1 , VREG2 (VDC) * RBW 100 kHz * VBW 30 kHz 802.11B, 5117 proto Ref 30 30 dBm Offset SWT 35 ms 18.8 dB 1 IFOVL 1 RM * AVG 20 10 POUT (dBm) ICQ, ICC, POUT versus VREG (Typical) 200.0 2.5 3.0 VREG1 , VREG2 (VDC) Marker 1 [T1] 22.01 dBm 2.441839744 GHz Delta 2 [T1] -40.55 11.723076923 Delta 3 [T1] -56.56 -23.900000000 dB MHz * RBW 100 kHz * VBW 30 kHz SWT 35 ms 802.11B, 5117 proto Ref 30 dBm 30 Offset A dB MHz LVL 0 Att 40 dB 18.8 dB 1 IFOVL 20 1 RM * AVG 10 Marker 1 [T1] 2.441839744 GHz Delta 2 [T1] -42.31 11.723076923 Delta 3 [T1] -58.92 -23.900000000 dB MHz dB MHz LVL 0 -10 PRN 2 -20 SWP 20 of -10 PRN -20 20 SWP -30 3 -30 -40 3 -40 -50 20 of 20 -50 -60 -60 -70 Center 2 2.442 GHz 5 MHz/ Comment A: 8 MHz int LPF's, Vcc=3.0 Vreg= 2.7, 200 mA Date: 26.SEP.2001 01:10:29 Span 50 MHz -70 Center 2.442 G H z 5 MHz/ Span 50 MHz Comment A: 8 MHz int LPF's, Vcc=Vreg= 2.7, 150 mA Date: 26.SEP.2001 01:11:53 Spectral Plot: VCC =3.0V, VREG1 =VREG2 =2.7VSpectral Plot: VCC =2.7V, VREG1 =VREG2 =2.7V POUT =22.05dBm, PIN =-4.1dBm, ICC ~200mAPOUT =19.05dBm, PIN =-6.8dBm, ICC ~150mA 2-580 Rev A7 041007 RF5117 VREF-VSENSE versus POUT 0.5 log10 (V REF-VSENSE ) 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -15.0 -10.0 -5.0 0.0 5.0 10.0 15.0 20.0 25.0 30.0 POUT Rev A7 041007 2-581 RF5117 EVM versus POUT (11g Tuned PA) VCC = 3.0V, Gain = 23dB VCC = 3.3V, Gain = 23dB 140.0 120 6.0 120.0 6.0 100 5.0 100.0 5.0 80.0 4.0 60.0 3.0 Icc(mA)2.4Vreg Icc(mA)2.5Vreg Icc(mA)2.6Vreg Icc(mA)2.7Vreg EVM%2.4Vreg EVM%2.5Vreg EVM%2.6Vreg EVM%2.7Vreg ICC (mA) 80 60 4.0 3.0 ICC (mA) 7.0 EVM% (added by PA) 140 40 2.0 40.0 20 1.0 20.0 0.0 0.0 0 14 14.5 25 15 15.5 16 16.5 17 17.5 18 15.5 Icc(mA)2.4Vreg Icc(mA)2.5Vreg Icc(mA)2.6Vreg Icc(mA)2.7Vreg EVM%2.4Vreg EVM%2.5Vreg EVM%2.6Vreg EVM%2.7Vreg 16.5 17.0 17.5 POUT (dBm) ICC and Gain for 11b Waveform in 11g Tuned PA Gain versus VREG for 11g Tuned PA 24.5 240 24 230 23.5 220 23 210 22.5 200 22 190 21.5 180 2.0 1.0 0.0 16.0 POUT (dBm) 25 250 7.0 EVM% (added by PA) EVM versus POUT (11g Tuned PA) 18.0 18.5 19.0 24.5 23.5 Gain (dB) Total ICC (mA) Gain (dB) 24 23 22.5 22 21 Gain (3V, Po=22.5dBm) 170 20.5 Gain (3.3V, Po=23dBm) Icc (3V, Po=22.5dBm) Icc (3.3V, Po=23dBm) 160 20 150 2.2 2.4 2.6 2.8 3 3.2 3.4 Gain- (VCC=3V) 21.5 Gain- (VCC=3.3V) 21 2.3 2.4 VREG (V) 2.5 2.6 2.7 2.8 VREG (V) Evaluation Board with 11g Tuning 2-582 Rev A7 041007