RF6100-1 0 3V 900MHZ LINEAR POWER AMPLIFIER MODULE Typical Applications • 3V CDMA/AMPS Cellular Handset • Spread-Spectrum System • 3V CDMA20001/X Cellular Handset Product Description Optimum Technology Matching® Applied 9 Si BJT GaAs HBT GaAs MESFET Si Bi-CMOS SiGe HBT Si CMOS InGaP/HBT GaN HEMT SiGe Bi-CMOS 4.00 ± 0.10 1.40 1.25 4.00 ± 0.10 2.975 0.600 TYP 0.500 TYP 0.450 ± 0.075 3.900 TYP 2.425 2.200 1.800 1.525 1.350 0.950 R0.20 TYP 1 3.549 3.500 3.050 2.650 2.400 TYP 2.200 1.800 1.650 1.350 0.950 0.725 0.125 3.000 TYP 3.200 3.500 TYP 3.900 TYP 0.500 TYP 0.100 TYP 0.000 0.000 0.775 1.000 TYP The RF6100-1 is a high-power, high-efficiency linear amplifier module specifically designed for 3V handheld systems. The device is manufactured on an advanced third generation GaAs HBT process, and was designed for use as the final RF amplifier in 3V IS-95/CDMA 2000 1X/AMPS handheld digital cellular equipment, spreadspectrum systems, and other applications in the 824MHz to 849MHz band. The RF6100-1 has a digital control line for low power applications to lower quiescent current. The device is self-contained with 50Ω input and output that is matched to obtain optimum power, efficiency and linearity. The module is a 4mmx4mm land grid array with backside ground. The RF6100-1 is footprint compatible with industry standard 4mmx4mm CDMA modules, and requires only one decoupling capacitor. 1 Package Style: Module (4mmx4mm) Features • Input/Output Internally Matched@50Ω • 28dBm Linear Output Power • 40% Peak Linear Efficiency • -50dBc ACPR @ 885kHz VREG 1 VMODE 2 GND 3 Bias 10 GND • 29dB Linear Gain 9 GND • 53% AMPS Efficiency 8 RF OUT RF IN 4 7 GND VCC1 5 6 VCC2 Functional Block Diagram Rev A0 031219 Ordering Information RF6100-1 3V 900MHz Linear Power Amplifier Module RF6100-1 PCBA Fully Assembled Evaluation Board RF Micro Devices, Inc. 7628 Thorndike Road Greensboro, NC 27409, USA Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com 2-689 RF6100-1 Absolute Maximum Ratings Parameter Supply Voltage (RF off) Supply Voltage (POUT ≤31dBm) Control Voltage (VREG) Input RF Power Mode Voltage (VMODE) Operating Temperature Storage Temperature Parameter Rating Unit +8.0 +5.2 +4.2 +10 +3.5 -30 to +110 -40 to +150 V V V dBm V °C °C Specification Min. Typ. Max. Caution! ESD sensitive device. RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s). Unit T=25oC Ambient, VCC =3.4V, VREG =2.8V, VMODE =0V, and POUT =28dBm for all parameters (unless otherwise specified). High Power Mode (VMODE Low) Operating Frequency Range Linear Gain Second Harmonics Third Harmonics Maximum Linear Output Linear Efficiency Maximum ICC ACPR @ 885kHz ACPR @ 1.98MHz Input VSWR Stability in Band Stability out of Band Noise Power 824 27 28 35 849 29 -35 -40 40 465 -50 -58 2:1 530 -46 -55 MHz dB dBc dBc % mA dBc dBc 6:1 10:1 -133 dBm/Hz 2-690 No oscillation>-70dBc No damage At 45MHz offset. T=25oC Ambient, VCC =3.4V, VREG =2.8V, VMODE =2.8V, and POUT =18dBm for all parameters (unless otherwise specified). Low Power Mode (VMODE High) Operating Frequency Range Linear Gain Second Harmonics Third Harmonics Maximum Linear Output Maximum ICC ACPR @885kHz ACPR @1.98MHz Input VSWR Output VSWR Stability Condition 824 24 849 26 -35 -40 MHz dB dBc dBc 18 135 -50 -60 2:1 -46 -56 6:1 10:1 mA dBc dBc POUT =16dBm No oscillation>-70dBc No damage Rev A0 031219 RF6100-1 Parameter Specification Min. Typ. Max. Unit T=25oC Ambient, VCC =3.4V, VREG =2.8V, VMODE =0V, and POUT =31dBm for all parameters (unless otherwise specified). FM Mode Operating Frequency Range AMPS Maximum Output Power AMPS Efficiency AMPS Gain AMPS Second Harmonics AMPS Third Harmonics Condition 824 849 MHz dBm % -30 -30 dBc dBc 4.2 100 70 5.5 1000 6 40 5.0 0.5 2.95 V mA mA mA uA uS uS uA V V 2.7 3.0 V 0 2.0 0.5 2.8 V V 47 24 31 53 28 -35 -40 Power Supply Supply Voltage High Gain Idle Current Low Gain Idle Current VREG Current VMODE Current RF Turn On/Off Time DC Turn On/Off Time Total Current (Power Down) VREG Low Voltage VREG High Voltage (Recommended) VREG High Voltage (Operational) VMODE Voltage Rev A0 031219 3.2 3.4 65 55 4.7 250 0.2 0 2.75 2.8 VMODE =low and VREG =2.8V VMODE =high and VREG =2.8V VMODE =high High Gain Mode Low Gain Mode 2-691 RF6100-1 Pin 1 Function VREG 2 VMODE 3 GND 4 5 RF IN VCC1 6 VCC2 7 GND 8 RF OUT 9 GND 10 GND Pkg Base GND 2-692 Description Interface Schematic Regulated voltage supply for amplifier bias. In Power Down mode, both VREG and VMODE need to be LOW (<0.5V). For nominal operation (High Power Mode), VMODE is set LOW. When set HIGH, devices are biased lower to improve efficiency. Ground connection. Connect to package base ground. For best performance, keep traces physically short and connect immediately to ground plane. RF input internally matched to 50Ω. This input is internally AC-coupled. First stage collector supply. A low frequency decoupling capacitor (e.g., 4.7µF) may be required. Output stage collector supply. A low frequency decoupling capacitor (e.g., 4.7µF) is required. Ground connection. Connect to package base ground. For best performance, keep traces physically short and connect immediately to ground plane. RF output internally matched to 50Ω. This output is internally AC-coupled. Ground connection. Connect to package base ground. For best performance, keep traces physically short and connect immediately to ground plane. Ground connection. Connect to package base ground. For best performance, keep traces physically short and connect immediately to ground plane. Ground connection. The backside of the package should be soldered to a top side ground pad which is connected to the ground plane with multiple vias. The pad should have a short thermal path to the ground plane. Rev A0 031219 RF6100-1 Evaluation Board Schematic (Download Bill of Materials from www.rfmd.com.) VREG 1 C3 4.7 µF 2 Bias C4 4.7 µF 50 Ω µstrip VCC1 C2 4.7 µF P1-2 P1-4 3 8 4 7 5 6 GND P2 1 GND 2 VCC1 2 GND 3 GND 3 VREG 4 VCC2 4 GND P2-3 P2-5 J2 RF OUT VCC2 P1 1 GND 5 CON5 Rev A0 031219 9 50 Ω µstrip VMODE J1 RF IN 10 C1 22 µF VMODE 5 CON5 2-693 RF6100-1 PCB Design Requirements PCB Surface Finish The PCB surface finish used for RFMD’s qualification process is electroless nickel, immersion gold. Typical thickness is 3µinch to 8µinch gold over 180µinch nickel. PCB Land Pattern Recommendation PCB land patterns are based on IPC-SM-782 standards when possible. The pad pattern shown has been developed and tested for optimized assembly at RFMD; however, it may require some modifications to address company specific assembly processes. The PCB land pattern has been developed to accommodate lead and package tolerances. 2.55 (mm) A 1.70 (mm) Typ. A A 0.00 A 0.00 0.45 (mm) 0.85 (mm) Typ. 3.60 (mm) 2.35 (mm) A 1.05 (mm) 0.65 (mm) A 2.95 (mm) Typ. 3.40 (mm) Typ. A Metal Land Pattern Pin 1 3.40 (mm) Typ. A A 2.55 (mm) Typ. A A 1.70 (mm) Typ. A 0.85 (mm) Typ. A A 0.00 A A B A 1.70 (mm) Pin 1 3.40 (mm) A = 0.55 (mm) Sq. Typ. B = 2.65 x 3.95 (mm) 0.00 A = 0.40 (mm) Sq. Typ. 3.60 (mm) Typ. PCB Metal Land and Solder Mask Pattern Solder Mask Pattern Figure 1. PCB Metal Land and Solder Mask Pattern (Top View) Thermal Pad and Via Design The PCB metal land pattern has been designed with a thermal pad that matches the exposed die paddle size on the bottom of the device. Thermal vias are required in the PCB layout to effectively conduct heat away from the package. The via pattern has been designed to address thermal, power dissipation and electrical requirements of the device as well as accommodating routing strategies. The via pattern used for the RFMD qualification is based on thru-hole vias with 0.203mm to 0.330mm finished hole size on a 0.5mm to 1.2mm grid pattern with 0.025mm plating on via walls. If micro vias are used in a design, it is suggested that the quantity of vias be increased by a 4:1 ratio to achieve similar results. 2-694 Rev A0 031219