TPD2E009 www.ti.com.............................................................................................................................................................. SLVS953A – JUNE 2009 – REVISED JUNE 2009 2-CHANNEL ESD SOLUTION FOR HIGH-SPEED (6 GBPS) DIFFERENTIAL INTERFACE FEATURES 1 • • • 1 3 D– GND 2 DRY PACKAGE (TOP VIEW) N.C. 1 GND 2 N.C. 3 6 D+ 5 VCC 4 D– W • • D+ IE • DBZ/DRT PACKAGE (TOP VIEW) EV • 0.05-pF Matching Capacitance Between the Differential Signal Pair Single-Pair Differential Lines to Protect the Differential Data and Clock Lines of the LVDS, SATA, Ethernet, or USB High-Speed (HS) Interface Flow-Through Pin Mapping for the High-Speed Lines Ensures Zero Additional Skew Due to Board Layout While Placing ESD-Protection Chip Near the Connector Supports Data Rates in Excess of 6 Gbps ESD Protection Meets or Exceeds IEC61000-4-2 (Level 4) 5-A Peak Pulse Current (8/20 µs Pulse) for VBUS and D+, D–, and ID Lines Industrial Temperature Range: –40°C to 85°C Multiple Space-Saving Package Options PR • N.C. – No internal connection APPLICATIONS • • • • • Notebooks Set-Top Boxes DVD Players Media Players Portable Computers DESCRIPTION/ORDERING INFORMATION The TPD2E009 provides 2 ESD clamp circuits with flow-through pin mapping for ease of board layout. This device has been designed to protect sensitive components which are connected to ultra high-speed data and transmission lines. The TPD2E009 offers protection from stress caused by ESD (electrostatic discharge). This device also offers 5 A (8/20 µs) peak pulse current ratings per IEC 61000-4-5 (lightning) specification. The monolithic silicon technology allows matching between the differential signal pairs. The less than differential 0.05-pF capacitance ensures that the differential signal distortion due to added ESD clamp remains minimal. The 0.7-pF line capacitance is suitable for high-speed data rate (in excess of 6 Gbps). The TPD2E009 conforms to IEC61000-4-2 (Level 4) ESD protection. The DRT (1 mm × 1 mm) package is offered for space-saving portable applications. The industry standard DBZ (2.4 mm × 2.9 mm) package offers additional flexibility in the board layout for the system designer. The TPD2E009 is characterized for operation over ambient air temperature range of –40°C to 85°C. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009, Texas Instruments Incorporated TPD2E009 SLVS953A – JUNE 2009 – REVISED JUNE 2009.............................................................................................................................................................. www.ti.com ORDERING INFORMATION TA PACKAGE –40°C to 85°C (1) (2) (1) (2) ORDERABLE PART NUMBER TOP-SIDE MARKING SON – DRY Tape and reel TPD2E009DRYR PREVIEW SOP – DBZ Tape and reel TPD2E009DBZR NFLR SOT– DRT Tape and reel TPD2E009DRTR 4T Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. CIRCUIT DIAGRAMS DRY Circuit EV IE W VCC PR D– D+ GND DBZ/DRT Circuit D– D+ GND TERMINAL FUNCTIONS TERMINAL (1) 2 NAME DBZ/DRT PIN NO. DRY (1) PIN NO. TYPE D+, D- 1, 2 4, 6 ESD port VCC – 5 Supply GND 3 3 GND DESCRIPTION High-speed ESD clamp, provides ESD protection to the high-speed differential data lines Power supply Ground Product Preview Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPD2E009 TPD2E009 www.ti.com.............................................................................................................................................................. SLVS953A – JUNE 2009 – REVISED JUNE 2009 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) IO voltage tolerance D+, D– pins TA Operating free-air temperature range Tstg Storage temperature range ESD protection (1) MIN MAX 0 6 –40 85 –65 UNIT °C 125 °C IEC 61000-4-2 Contact Discharge D+, D– pins ±8 kV IEC 61000-4-2 Air-Gap Discharge D+, D– pins ±8 kV Peak pulse current (tp = 8/20 µs) D+, D– pins 5 A Peak pulse power (tp = 8/20 µs) D+, D– pins 45 W Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VRWM Reverse stand-off voltage D+,D– pins to ground Vclamp Clamp voltage D+,D– pins to ground, IIO Current from IO port to supply pins VIO = 2.5 V, ID = 8 mA VD Rdyn CIO VBR Diode forward voltage Dynamic resistance IO capacitance Break-down voltage MIN TYP MAX 5.5 IIO = 1 A UNIT V 8 V 0.01 0.1 µA D+,D– pins, lower clamp diode, VIO = 2.5 V, ID = 8 mA 0.6 0.8 0.95 D+,D– pins, upper clamp diode, DRY package VCC = 0 V, ID = –8 mA 0.6 0.8 0.95 D+,D– pins, I=1A D+,D– pins, DBZ Package D+,D– pins, DRT Package V 1 Ω VIO = 2.5 V 0.9 pF VIO = 2.5 V 0.7 pF IIO = 1 mA 7 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPD2E009 V 3 TPD2E009 SLVS953A – JUNE 2009 – REVISED JUNE 2009.............................................................................................................................................................. www.ti.com TYPICAL OPERATING CHARACTERISTICS 10 1.20E-12 TA = 25°C 5 1.10E-12 9.00E-13 Leakage Current (pA) Capacitnace (Farads) 0 1.00E-12 DBZ Package 8.00E-13 DRT Package 7.00E-13 –5 –10 –15 D– –20 D+ –25 –30 6.00E-13 5.00E-13 0.0 VIO = 2.5 V –35 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 –40 Figure 1. IO Capacitance vs IO Voltage 11 55 10 5.0 50 4.5 45 4.0 40 3.5 35 3.0 30 25 Current (A) 2.0 20 1.5 15 1.0 9 8 PPP (W) IPP (A) 60 Current (A) Measured at one IO, the other IO open 2.5 7 6 5 4 3 10 Power (W) 2 5 0.5 0.0 1 0 5 0 10 15 20 25 30 Time (ms) 35 40 45 50 0 0 5 10 15 20 Voltage (V) 25 30 35 40 Figure 4. D+,D– Transmission Line Pulser Plot (100 ns Pulse, 10 ns Rise Time) 100 20 90 10 80 0 70 -10 60 -20 Amplitude (V) Amplitude (V) Figure 3. Peak Pulse Waveforms 50 40 30 -30 -40 -50 20 -60 10 -70 0 -80 -10 -90 -20 -100 0 25 50 75 100 Time (ns) 125 150 175 Figure 5. IEC Clamping Waveforms (8 kV Contact) 4 85 Figure 2. Leakage Current vs Temperature 6.0 5.5 55 25 Temperature (°C) –40 Voltage (V) 200 0 25 50 75 100 Time (ns) 125 150 175 200 Figure 6. IEC Clamping Waveforms (–8 kV Contact) Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPD2E009 TPD2E009 www.ti.com.............................................................................................................................................................. SLVS953A – JUNE 2009 – REVISED JUNE 2009 TYPICAL OPERATING CHARACTERISTICS (continued) Eye Diagrams Figure 7. Eye Diagram With TPD2E009 (3.3 Gbps Data Rate) (3-Pin DBZ Package) Figure 8. Eye Diagram Without TPD2E009 (3.3 Gbps Data Rate) (3-Pin DBZ Package) Figure 9. Eye Diagram With TPD2E009 (5.0 Gbps Data Rate) (3-Pin DBZ Package) Figure 10. Eye Diagram Without TPD2E009 (5.0 Gbps Data Rate) (3-Pin DBZ Package) Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPD2E009 5 TPD2E009 SLVS953A – JUNE 2009 – REVISED JUNE 2009.............................................................................................................................................................. www.ti.com TYPICAL OPERATING CHARACTERISTICS (continued) Figure 11. Eye Diagram With TPD2E009 (6.0 Gbps Data Rate) (3-Pin DBZ Package) 6 Figure 12. Eye Diagram Without TPD2E009 (6.0 Gbps Data Rate) (3-Pin DBZ Package) Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPD2E009 TPD2E009 www.ti.com.............................................................................................................................................................. SLVS953A – JUNE 2009 – REVISED JUNE 2009 APPLICATION INFORMATION Typical Application Figure 13. TPD2E009 in Differential eSATA Interface Figure 13 shows the board layout scheme for the D+/D– lines of a single differential pair. It allows the differential signal pairs couple together right after they touch the ESD ports (pin 1 and pin 2) of the TPD2E009. Designing with High-Speed Differential Signals Layout considerations, such as package selection, trace routing, etc. must be taken into account while designing the ESD clamp circuit for high-speed interface. Difficult routing can lead the designer to use vias or stubs in the board traces, creating significant disruption in the line impedance in the high-speed signal path. Poor package choice can force designer to route differential traces with unequal lengths and add the skew in the signals. It is recommended to closely couple the differential traces to reduce the EMI interference. The TPD2E009 can provide system level ESD protection to the high-speed differential ports (>6 Gbps data rate). The flow-through package offers flexibility for board routing with traces up to 15 mills wide. Figure 14 and Figure 15 show the board layout scheme for the D+/D– lines of a single differential pair. It allows the differential signal pairs couple together right after they touch the ESD ports (pin 1 and pin 2) of the TPD2E009. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPD2E009 7 TPD2E009 SLVS953A – JUNE 2009 – REVISED JUNE 2009.............................................................................................................................................................. www.ti.com 1.27 mm 1.27 mm BOARD LAYOUT FOR DRT PACKAGE TPD2E009DRTR AT eSATA PORT D+ GND D– GND VIA Figure 14. TPD2E009DRTR at eSATA Connector Interface 1.27 mm 1.27 mm BOARD LAYOUT FOR DBZ PACKAGE TPD2E009DBZR AT eSATA PORT D+ GND D– GND VIA Figure 15. TPD2E009DBZR at eSATA Connector Interface 8 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPD2E009 PACKAGE MATERIALS INFORMATION www.ti.com 7-Aug-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) TPD2E009DBZR SOT-23 DBZ 3 3000 180.0 9.2 TPD2E009DRTR SOT DRT 3 3000 180.0 8.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3.18 3.28 1.32 4.0 8.0 Q3 1.16 1.16 0.63 4.0 8.0 Q3 PACKAGE MATERIALS INFORMATION www.ti.com 7-Aug-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPD2E009DBZR TPD2E009DRTR SOT-23 DBZ 3 3000 202.0 201.0 28.0 SOT DRT 3 3000 180.0 180.0 85.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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