CXB1585N Fibre Channel Repeater Description The CXB1585N is a repeater IC with a built-in PLL clock recovery circuit for Fibre Channel 1.06Gbaud. This IC incorporates a port bypass circuit and is suitable for disk array and FC-AL HUB, etc. 24 pin SSOP (Plastic) Features • Conforms to ANSI X3T11 Fibre Channel standard • Single 3.3V power supply • Low power consumption: 330mW (Typ.) • Low jitter • PLL lock detection circuit • Port bypass circuit • Small plastic package (24-pin SSOP) Applications • Fibre channel arbitrated loop 1.0625Gbaud HUB • Disk array Structure Bipolar silicon monolithic IC Pin Configuration TEST1 1 24 VEEG 23 VEEE VCCG 2 TDSEL∗ 3 22 VCCE SDIN 4 21 SDOUT SDIN∗ LKREF∗ 5 20 SDOUT∗ 6 19 TEST2 TDIN TDIN∗ 7 18 LKDT 8 17 TDOUT REFCLK 9 16 TDOUT∗ VEET 10 15 VCCP VEEP 11 14 LPFPOS REXT 12 13 LPFNEG Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E96301-ST CXB1585N REXT LPFNEG LPFPOS TDOUT∗ 1.063GBPS (ECL) TDOUT SDIN∗ 1.063GBPS (ECL) SDIN Block Diagram TDIN TDIN∗ 1.063GBPS (ECL) 0 SDOUT MUX SDOUT∗ 1 S DFF Lock Det 1.063GBPS (ECL) LKDT (TTL) Sig Det Phase Det 1 MUX VCO 0S LKREF∗ (TTL) REFCLK Freq Det 53.125MHZ ÷ 20 TDSEL∗ (TTL) 53.125MHZ (TTL) –2– CXB1585N Absolute Maximum Ratings (VEEE, VEET, VEEG, VEEP = 0V) Item Symbol Min. Typ. Max. Unit Supply voltage VCC –0.3 4 V TTL DC input voltage VI_T –0.5 5.5 V ECL DC input voltage VI_E VCC – 2 VCC V ECL differential input voltage VIS_E –2 2 V TTL output current (High level) IOH_T –20 0 mA TTL output current (Low level) IOL_T 0 20 mA ECL output current IO_E –30 0 mA Operating ambient temperature Ta –55 70 °C Storage temperature Tstg –65 150 °C Recommended Operating Conditions (VEEE, VEET, VEEG, VEEP = 0V) Item Symbol Min. Typ. Max. Unit 3.3 3.465 V 70 °C Supply voltage VCC 3.135 Ambient temperature Ta 0 –3– CXB1585N Pin Description Pin No. Symbol Type Typical pin I/O voltage Equivalent circuit Description VCCG 1, 19 TEST1 TEST2 TTL input 3.3V Test pin. Connect to Vcc. TTL_IN VEEE 2 VCCG Power supply VEET Positive power supply for internal logic gate. — 3.3V VCCG 3 TDSEL∗ TTL input TTL level High; SDOUT outputs the SDIN retimed data. Low; SDOUT outputs TDIN data. TTL_IN VEEE VEET VCCE VCCG ECL_IN 4, 5 SDIN SDIN∗ ECL input VCCE – 1.3V ECL level Serial data input. ECL_IN∗ VEEE VEEG VCCG 6 LKREF∗ TTL input TTL level Low; PLL takes the frequency from REFCLK. TTL_IN VEEE VEET –4– CXB1585N Pin No. Symbol Type Typical pin I/O voltage Equivalent circuit Description VCCE VCCG ECL_IN 7, 8 TDIN TDIN∗ ECL input VCCE – 1.3V ECL level Serial data input. ECL_IN∗ VEEE VEEG VCCG 9 REFCLK TTL input TTL level Reference clock input. This pin is used for the PLL to take the frequency. Input 53.125MHz to this pin. TTL_IN VEET VEET 10 VEET Power supply 0V Negative power supply for REFCLK input. 11 VEEP Power supply 0V Negative power supply for internal PLL. VCCP 12 REXT External parts connection pin — REXT Connects the resistor which determines the VCO center frequency. 4.7kΩ resistor should be connected between this pin and VEEP. VEEP VCCP 13, 14 External LPFNEG parts LPFPOS connection pin LPF_A — Connects the external loop filter. LPF_B VEEP –5– CXB1585N Pin No. 15 Symbol VCCP Type Power supply Typical pin I/O voltage Equivalent circuit Description Positive power supply for PLL. 3.3V VCCE 16, 17 TDOUT∗ TDOUT ECL_OUT ECL output ECL level ECL_OUT∗ Outputs the data input from TDIN via a buffer. VEEE VCCE 18 LKDT TTL output TTL_OUT TTL level VEEE PLL clock detection signal output.Outputs high level when PLL is locked to the serial data;Outputs low level when LKREF is in the low level or the serial data has no signal. The LKDT output may sporadically go high when the PLL starts to lock to the serial data. VCCE 20, 21 SDOUT∗ SDOUT ECL_OUT ECL output ECL level ECL_OUT∗ Outputs the serial data selected by TDSEL∗. VEEE 22 VCCE Power supply — Positive power supply for input/output. 23 VEEE Power supply — Negative power supply for input/output. 24 VEEG Power supply — Negative power supply for internal logic gate. –6– CXB1585N Electrical Characteristics DC Characteristics Item (under the recommended operating conditions) Symbol Min. Typ. Max. Unit Conditions TTL high level input voltage VIH_T 2 5.5 V TTL low level input voltage VIL_T 0 0.8 V TTL high level input current IIH_T 20 µA VIH = VCC TTL low level input current IIL_T –400 µA VIL = 0 TTL high level output voltage VOH_T 2.2 V IOH = –0.4mA TTL low level output voltage VOL_T 0.5 V IOL = 2mA ECL high level input voltage VIH_E VCC – 1.17 VCC – 0.88 V ECL low level input voltage VIL_E VCC – 1.81 VCC – 1.48 V ECL differential input voltage VIS_E 200 1000 mV ECL high level output voltage VOH_E VCC – 1.05 VCC – 0.81 V 50Ω terminated to Vcc – 2V ECL low level output voltage VOL_E VCC – 1.81 VCC – 1.55 V 50Ω terminated to Vcc – 2V ECL output amplitude VOS_E 650 mV 50Ω terminated to Vcc – 2V Current consumption ICC 101 127 mA Output pins open Power consumption PD 333 438 mW Output pins open AC Characteristics Item AC coupling input (under the recommended operating conditions) Symbol Min. Typ. Max. Unit Conditions REFCLK rise time Tir_RC 4.8 ns 0.8 to 2.0V REFCLK fall time Tif_RC 4.8 ns 2.0 to 0.8V TTL output rise time Tor_T 3.5 ns 0.8 to 2.0V, CL = 10pF TTL output fall time Tof_T 3.5 ns 2.0 to 0.8V, CL = 10pF ECL output rise time Tor_E 400 ps 20 to 80%, CL ≤ 2pF ECL output fall time Tof_E 400 ps 20 to 80%, CL ≤ 2pF SDIN data rate SDIN 1000 1062.5 1100 Mbaud REFCKL cycle tolerance Ttol_RC –100 0 100 ppm Jitter tolerance JT 0.7 Ul Deterministic jitter Dj 0.02 0.07 Ul ±K28.5 serial data Random jitter RJ 0.18 0.23 Ul Serial data Bit sync time Tbs 2500 bit FC Idle Pattern Frequency take-in time Tfa 500 µs Loop Damping Capacitor C1 = 0.01µF –7– Refer to the SDIN cycle CXB1585N Electrical Characteristics Measurement Circuit (See “Fig. 3 Power Supply Circuit” regarding the power supply.) II_T Measurement device TTL_IN TTL_OUT VI_T Io_T Vo_T (a) TTL I/O DC characteristics measurement circuit Pulse generator Measurement device TTL_IN Probe TTL_OUT Oscilloscope CL CL = 10pF (including the probe capacitance) (b) TTL I/O AC characteristics measurement circuit II_E A Measurement device ECL_IN ECL_OUT VI_TE 50Ω V VO_E VCCE – 2V (c) ECL I/O DC characteristics measurement circuit VCCE – 2V 50Ω Pulse generator VCCE – 2V Measurement device ECL_IN ECL_OUT ECL_IN∗ ECL_OUT∗ 50Ω Oscilloscope 50Ω 50Ω VCCE – 2V VCCE – 2V 50Ω Transmission Line CL ≤ 2pF (input capacitance of the measurement equipment and floating capacitance) (d) ECL I/O AC characteristics measurement circuit 26.5625MHz Triger Measurement device VCCE – 2V 50Ω SDIN Pulse generator 1.0625GBPS SDIN∗ SOUT SOUT∗ 1.0625GBPS 50Ω VCCE – 2V (e) Jitter characteristics measurement circuit –8– Oscilloscope CXB1585N Notes on Operation 1. Clock synthesizer (PLL) The CXB1585N has a PLL-based clock recovery circuit for recovering the clock from the serial data. This clock recovery circuit requires an external loop filter and an external resistor which determines the VCO center frequency. The external part circuit and recommended constant values are shown in the figure below. The parasitic capacitance attached to the IC pins (Pins 12, 13 and 14) which are used to connect external parts should be kept as small as possible in order to obtain the good PLL characteristics. In addition, capacitor C1 should have a small temperature coefficient to reduce the temperature dependence of the VCO oscillation frequency. CXB1585N 11 LPFPOS 14 VEEP C1 12 LPFNEG 13 REXT R1 R1: 4.7kΩ C1: 0.01µF Fig. 1. External Part Circuit and Recommended Constants –9– CXB1585N 2. ECL input circuit The ECL differential input pins are biased to VBB (VCC – 1.3V) via an 18kΩ resistor in the IC. See the figures below for ECL differential input methods. VCC = 3.3V, VEE = GND VCC = 3.3V, VEE = GND VBB (VCC – 1.3V) 18kΩ 18kΩ 160Ω 160Ω 3.3V ECL output buffer ECL differential input buffer (a) ECL differential signal from 3.3V ECL output buffer VCC VCC = GND, VEE = –4.5V VCC = 3.3V, VEE = GND 220kΩ 330Ω VBB (VCC – 1.3V) 330pF 18kΩ 330pF 18kΩ 330Ω ECL100K output buffer ECL differential input buffer VEE (b) ECL differential signal from ECL 100K output buffer VCC VCC = 3.3V, VEE = GND 220kΩ VBB (VCC – 1.3V) 18kΩ 330pF 50Ω TRANS. LINE 330pF 50Ω 18kΩ 50Ω ECL differential input buffer VTT (VCC – 2V) (c) ECL differential signal from 50Ω transmission line VCC VCC = 3.3V, VEE = GND 220kΩ 330pF 50Ω TRANS. LINE 50Ω 330pF VBB (VCC – 1.3V) 18kΩ 18kΩ VTT (VCC – 2V) ECL differential input buffer (d) ECL single signal from 50Ω transmission line Fig. 2. ECL Input Circuits – 10 – CXB1585N 3. Power supply VCCG VCCT 3.3V 22µF 0.1µF VCCP 0.1µF 22µF 22µF VEEG VEET 0.1µF VEEP Fig. 3. Power Supply Circuit 4. SDIN, SDIN∗ inputs Normally, the VCO performs frequency comparison with the SDIN and SDIN∗ serial data. When there is no input to SDIN and SDIN∗, frequency comparison is executed with REFCLK. However, the frequency may not be compared to REFCLK if the noise and others are detected as a signal for no signal state because the both phases of the ECL differential inputs are internally biased to VBB shown below. As countermeasure to this, connect either of the differential inputs to VCC via a resistor to generate the voltage difference for the both phases. VCC 220kΩ 330pF VBB (VCC – 1.3V) 18kΩ 50Ω TRANS. LINE 330pF 50Ω 18kΩ 50Ω ECL differential input buffer VTT (VCC – 2V) ECL differential signal from 50Ω transmission line Fig. 4. SDIN and SDIN∗ Input Example – 11 – CXB1585N Example of Representative Characteristics Jitter Transfer 5 Jitter Transfer [dB] 0 –5 –10 C1 = 0.01µF, R1 = 4.7kΩ, Ta = 27°C Pattern: Fibre Channel ldle Pattern (Transition Density = 80%) –15 101 102 103 104 105 Modulation Frequency [Hz] 106 107 108 Bit Synchronization Time 4000 C1 = 0.01µF, R1 = 4.7kΩ, Ta = 27°C Pattern: Fibre Channel ldle Pattern (Transition Density = 80%) 3500 Bit Synchronization Time [ns] 3000 2500 2000 1500 1000 500 0 51.5 52 52.5 53 REFCLK [MHZ] – 12 – 53.5 54 CXB1585N [100mV/div] Example of Random jitter measurement (Retimed data 1.0625Gbps) C1 = 0.01µF, R1 = 4.7kΩ, Ta = 27°C SDIN: Fibre Channel ldle Pattern (Transition Density = 80%) RJ = 9.6ps (RMS) [50ps/div] [200mV/div] Eye pattern (Retimed data 1.0625Gbps) C1 = 0.01µF, R1 = 4.7kΩ, Ta = 27°C SDIN: Fibre Channel ldle Pattern (Transition Density = 80%) [200ps/div] – 13 – CXB1585N Package Outline Unit: mm 24PIN SSOP(PLASTIC) + 0.2 1.25 – 0.1 ∗7.8 ± 0.1 24 0.1 13 ∗5.6 ± 0.1 7.6 ± 0.2 A 1 + 0.1 0.22 – 0.05 12 + 0.05 0.15 – 0.02 0.13 M 0.65 0.5 ± 0.2 0.1 ± 0.1 0° to 10° NOTE: “∗” Dimensions do not include mold protrusion. DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE SSOP-24P-L01 LEAD TREATMENT SOLDER/PALLADIUM PLATING EIAJ CODE SSOP024-P-0056 LEAD MATERIAL 42/COPPER ALLOY PACKAGE WEIGHT 0.1g JEDEC CODE – 14 –