CXP82500 CMOS 8-bit Single Chip Microcomputer Description The CXP82500 is a CMOS 8-bit single chip microcomputer of piggyback/evaluator combined type, which is developed for evaluating the function of the CXP82532/82540. Piggyback/ evaluator type 80 pin PQFP (Ceramic) Features • Wide-range instruction system (213 instructions) to cover various types of data — 16-bit operation/multiplication and division/ Boolean bit operation instructions • Minimum instruction cycle 400ns at 10MHz operation • Applicable EPROM LCC type 27C512 (Maximum 40K bytes are available.) • Incorporated RAM capacity 1120 bytes (Including fluorescent display data area) • Peripheral functions — A/D converter 8-bit, 8-channel, successive approximation method (Conversion time of 32µs/10MHz) — Serial interface Incorporated 8-bit, 8-stage FIFO (Auto transfer for 1 to 8 bytes), 1 channel 8-bit clock sync type, 1 channel — Timer 8-bit timer 8-bit timer/counter 19-bit time base timer 16-bit capture timer/counter — Fluorescent display panel controller/driver Maximum 336 segment display possible 1 to 16-digit dynamic display Dimmer function High voltage drive output (40V) On-chip pull-down resistor (Mask option) Hardware key scan function (Maximum 16 × 8 key matrix compatible) — Remote control reception circuit 8-bit pulse measurement counter with on-chip 6-stage FIFO • Interruption 14 factors, 14 vectors, multi-interruption possible • Standby mode Sleep/stop • Package 80-pin ceramic QFP Note) Mask option depends on the type of the CXP82500. Refer to the Products List for details. Structure Silicon gate CMOS IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E93863A78-PS CXP82500 T5 T4 T3 T2 T1 T0 VFDP VDD NC PG0 PG1 PG2 PG3 PE0/EC0/INT0 PE1/EC1/INT1 PE2/IN2 Pin Assignment in Piggyback Mode 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 T6 PE4/RMC 2 63 T7 PE5 3 62 T8/S28 61 T9/S27 PB4/SO0 10 PB6/SI1 PB7/SO1 PC0/KR0 PC1/KR1 PC2/KR2 11 12 13 14 15 16 PC3/KR3 17 PC4/KR4 18 PC5/KR5 19 PC6/KR6 20 VDD 1 32 31 30 5 29 A8 A5 6 28 A9 A4 7 27 A11 A3 8 26 NC A2 9 25 OE A1 10 24 A10 A0 11 23 CE NC 12 22 D7 D0 13 21 D6 14 15 16 17 18 19 20 D1 PB5/SCK1 A6 2 D5 9 3 D4 8 PB3/SI0 4 D3 PB2/SCK0 NC 7 NC PB1/CS0 A15 6 GND PB0/CINT A12 5 D2 4 A7 PE6 PE7/TO A13 1 A14 PE3/INT3 60 T10/S26 59 T11/S25 58 T12/S24 57 T13/S23 56 T14/S22 55 T15/S21 54 S20 53 S19 52 S18 51 S17 50 S16 49 PF7/S15 48 PF6/S14 47 PF5/S13 46 PF4/S12 45 PF3/S11 21 44 PF2/S10 22 43 PF1/S9 PA1/AN1 23 42 PF0/S8 PA2/AN2 24 41 PD7/S7 Note) NC (Pin 73) is always connected to VDD. –2– PD6/S6 PD5/S5 PD4/S4 PD3/S3 PD2/S2 PD1/S1 PD0/S0 VSS XTAL EXTAL RST PA7/AN7 PA6/AN6 PA5/AN5 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 PA4/AN4 PA0/AN0 PA3/AN3 PC7/KR7 CXP82500 T5 T4 T3 T2 T1 T0 VFDP VDD NC PG0 PG1 PG2 PG3 PE0/EC0/INT0 PE2/IN2 PE1/EC1/INT1 Pin Assignment in Evaluator Mode 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 PE4/RMC 2 63 T7 PE5 3 62 T8/S28 PE6 4 61 T9/S27 60 T10/S26 59 T11/S25 58 T12/S24 7 PB2/SCK0 8 PB3/SI0 9 PB4/SO0 10 PB5/SCK1 PB6/SI1 PB7/SO1 PC0/KR0 PC1/KR1 PC2/KR2 11 16 2 1 32 31 30 5 29 A8 A5/D5 6 28 A9 A4/D4 7 27 A11 A3/D3 8 26 NC A2/D2 9 25 HALT A1/D1 10 24 A10 A0/D0 11 23 E/P NC 12 22 I/T RD 13 21 MON 13 15 3 A6/D6 12 14 4 A13 PB1/CS0 A14 5 6 VDD PE7/TO PB0/CINT NC T6 A15 64 A12 1 A7/D7 PE3/INT3 57 T13/S23 56 T14/S22 55 T15/S21 54 S20 53 S19 52 S18 51 S17 50 S16 49 PF7/S15 48 PF6/S14 PC3/KR3 17 PC4/KR4 18 47 PF5/S13 PC5/KR5 19 46 PF4/S12 PC6/KR6 20 RST C1 C2 NC GND SYNC WR 14 15 16 17 18 19 20 45 PF3/S11 PC7/KR7 21 44 PF2/S10 PA0/AN0 22 43 PF1/S9 PA1/AN1 23 42 PF0/S8 PA2/AN2 24 41 PD7/S7 Note) NC (Pin 73) is always connected to VDD. –3– PD6/S6 PD5/S5 PD4/S4 PD3/S3 PD2/S2 PD1/S1 PD0/S0 VSS XTAL EXTAL RST PA7/AN7 PA6/AN6 PA5/AN5 PA4/AN4 PA3/AN3 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 CXP82500 EPROM Read Timing (Ta = –20 to +75°C, Vcc = 4.5 to 5.5V, Vss = 0V reference) Item Symbol Pins Address → Data Input delay time tACC A0 to A15 D0 to D7 Address → Data Hold time tIH A0 to A15 D0 to D7 Min. Max. Unit 120 ns 0 ns 0.8VDD A0 to A15 Address data 0.2VDD tACC tIH 0.8VDD D0 to D7 Input data 0.2VDD Products List Products Option item Mask CXP82532 Package ROM capacitance CXP82540 80-pin plastic QFP 32K bytes 40K bytes Piggyback/evaluator CXP82500-U01Q 80-pin ceramic PQFP 40K bytes Pull-up resistance for reset pin Existent/Non-existent Existent Power-on reset circuit Existent/Non-existent Existent Pull-down resistance for high voltage drive pin Existent/Non-existent Only port for display –4– CXP82500 Piggyback mode/evaluator mode can be switched as shown below. Piggyback mode Evaluator mode Piggyback/evaluator product Pin 1 marking Pin 1 index LCC type EPROM Pin 1 marking Note) CPU Probe Note) Evaluation cap should be connected to CPU probe. Package Outline Unit: mm 80PIN PQFP (CERAMIC) PIN No. 1 INDEX 18.7 16.3 ± 0.2 INDEX 80 65 65 64 PIN No. 1 INDEX 1 64 0.8 ± 0.05 1 80 0.4 ± 0.08 14.22 18.12 ± 0.2 1.27 ± 0.13 12.02 0.7 1.0 0.3 6.0 24 40 9.48 24 41 1.3 ± 0.3 41 25 40 25 0.6 11.66 15.58 ± 0.2 PACKAGE STRUCTURE PACKAGE MATERIAL PQFP-80C-L01 LEAD TREATMENT GOLD PLATING EIAJ CODE AQFP080-C-0000-A LEAD MATERIAL 42 ALLOY PACKAGE WEIGHT 5.7g 9.59 MAX + 0.05 0.15 – 0.02 CERAMIC SONY CODE JEDEC CODE 3.57 ± 0.36 24.7 22.3 ± 0.25 4.5 –5–