ILX115LA 5000-pixel × 3 line CCD Linear Sensor (Color) For the availability of this product, please contact the sales office. Description The ILX115LA is a reduction type CCD linear sensor developed for color DPPC. This sensor reads A3-size documents at a density of 400 DPI (Dot Per Inch). 44 pin SDIP (Cer-DIP) Features • Number of effective pixels: 15000 pixels (5000 pixels × 3) • Pixel size: 14µm × 14µm (14µm pitch) • Distance between line: 84µm (6 lines) • Maximum data rate: 30MHz/color (20MHz/color during clamp circuit usage) • Single 9V power supply • Input Clock Pulse: CMOS 5V drive • Number of output: 6 (2/color) • Package: 44pin SDIP (400mil) Absolute Maximum Ratings • Supply voltage VDD • Operating temperature • Storage temperature 11 –10 to +60 –30 to +80 18 φROG (R) 21 GND 25 φROG (B) 26 VDD 28 φROG (G) Block Diagram V °C °C 8 NC 9 26 VDD NC 20 25 φROG (B) GND 21 NC 22 24 NC 23 NC 16 6 15 3 Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– 8 Output circuit-EVEN (R) Output circuit-ODD (R) Output circuit-EVEN (B) 2 19 E99705-PS VOUT-ODD (R) VOUT-EVEN (R) φCLP SWCLP 27 NC NC 5000 28 φROG (G) 18 5000 17 5000 NC φROG (R) 1 29 φ1 30 NC VOUT-EVEN (B) 16 GND 44 φ2 VOUT-ODD (B) 43 15 Output circuit-ODD (B) Output circuit-ODD (G) 31 NC SWCLP Output circuit-EVEN (G) 39 32 NC NC 14 φ2 29 13 41 NC 34 φ1 33 NC 42 12 VOUT-EVEN (G) VOUT-ODD (G) NC 35 NC G 11 36 NC B 10 37 φ2L R φ2 NC 10 38 NC φCLP 4 39 VREF 7 VDD φ2 6 NC φRS 40 NC φRS CCD register (R) ROG (R) Sensor (R) ROG (R) CCD register (R) 5 CCD register (B) ROG (B) Sensor (B) ROG (B) CCD register (B) 41 VOUT-ODD (G) NC CCD register (G) ROG (G) Sensor (G) ROG (G) CCD register (G) 42 VOUT-EVEN (G) 4 34 3 VDD 37 VOUT-EVEN (R) VREF φ2L 43 VOUT-ODD (B) 1 44 GND 2 1 1 VOUT-ODD (R) 1 VOUT-EVEN (B) φ1 φ1 Pin Configuration (Top View) ILX115LA Pin Description Pin No. Symbol Description Pin No. Symbol Description 1 VOUT-EVEN (B) Signal output (B) 23 NC NC 2 VOUT-ODD (R) Signal output (R) 24 NC NC 3 VOUT-EVEN (R) Signal output (R) 25 φROG (B) Clock pulse input 4 VDD 9V power supply 26 VDD 9V power supply 5 NC NC 27 NC NC 6 φRS Clock pulse input 28 φROG (G) Clock pulse input 7 NC NC 29 φ1 Clock pulse input 8 φCLP Clock pulse input 30 NC NC 9 NC NC 31 NC NC 10 φ2 Clock pulse input 32 NC NC 11 NC NC 33 NC NC 12 NC NC 34 φ1 Clock pulse input 13 NC NC 35 NC NC 14 NC NC 36 NC NC 15 SWCLP Clamp switch 37 φ2L Clock pulse input 16 φ2 Clock pulse input 38 NC NC 17 NC NC 39 VREF Power supply (Clamp) 18 φROG (R) Clock pulse input 40 NC NC 19 NC NC 41 VOUT-ODD (G) Signal output (G) 20 NC NC 42 VOUT-EVEN (G) Signal output (G) 21 GND GND 43 VOUT-ODD (B) Signal output (B) 22 NC NC 44 GND GND Recommended Supply Voltage Item Min. Typ. Max. Unit VDD 8.55 9 9.45 V Clock Characteristics Item Symbol Min. Typ. Max. Unit Input capacity of φ1, φ2 Cφ1, Cφ2 — 1800 — pF Input capacity of φ2L Cφ2L — 60 — pF Input capacity of φRS CφRS — 60 — pF Input capacity of φROG CφROG — 60 — pF Input capacity of φCLP CφCLP — 60 — pF Note) Input capacity of φ1, φ2 is a value gathering respective related pins. –2– ILX115LA Clock Frequency Item Symbol Min. Typ. Max. Unit φ1, φ2, φ2L, φRS fφ1, fφ2, fφ2L, fφRS — 1 15 MHz φCLP fφCLP — 1 10 MHz Input Clock Pulse Voltage Item φ1, φ2, φ2L, φRS, φROG, φCLP pulse voltage Min. Typ. Max. Unit High level 4.75 5.0 5.25 V Low level –0.3 0 0.1 V Mode Description Pin condition Clamp circuit not used Clamp circuit used 8pin φCLP 15pin SWCLP VDD GND φCLP VDD –3– ILX115LA Electrooptical Characteristics (Note 1) Ta = 25°C, VDD = 9V, fφRS = 1MHz, Input clock = 5Vp-p, Clamp circuit used, Light source = 3200K, IR cut filter: CM-500S (t = 1.0mm) Item Sensitivity Symbol Min. Typ. Max. Red RR 5.10 6.80 8.50 Green RG 5.17 6.89 8.61 Blue RB 5.48 7.30 9.13 Unit Remarks V/(lx · s) Note 2 Note 3 Sensitivity nonuniformity PRNU — 5 15 % Saturation output voltage VSAT 1.5 1.8 — V Red SER 0.18 0.26 — Green SEG 0.18 0.26 — Blue SEB 0.16 0.25 — Dark voltage average VDRK — 1.5 3 mV Dark signal nonuniformity DSNU — 1.5 5 mV Image lag IL — 0.02 — % Note 6 Supply current IVDD — 45 60 mA — Total transfer efficiency TTE 92 98 — % — Output impedance ZO — 185 — Ω — Offset level VOS — 4.4 — V Note 7 Saturation exposure lx · s Note 4 Note 5 Notes 1) In accordance with the given electrooptical characteristics, the even black level is defined as the average value of D24, D26 to D72. The odd black level is defined as average value of D23, D25 to D71. 2) For the sensitivity test light is applied with a uniform intensity of illumination. 3) PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 2. VOUT = 500mV (VMAX – VMIN) /2 PRNU = × 100 [%] VAVE Where the 5000 pixels are divided into blocks of 100, even and odd pixels, respectively the maximum output of each block is set to VMAX, the minimum output to VMIN and the average output to VAVE. 4) Saturation exposure is defined as follows. SE = VSAT/R [lx · s] 5) Optical signal accumulated time τint stands at 10ms. 6) VOUT (B)= 500mV (typ.) 7) Vos is defined as indicated below. VOUT indicates VOUT-ODD (R), VOUT-EVEN (R), VOUT-ODD (G), VOUT-EVEN (G), VOUT-ODD (B), VOUT-EVEN (B). VOUT VOS GND –4– VOUT-EVEN (R) VOUT-EVEN (G) VOUT-EVEN (B) VOUT-ODD (R) VOUT-ODD (G) VOUT-ODD (B) 0 D25 D26 D23 D24 D21 D22 D5 D6 D3 D4 D1 D2 1-line output period (5090 pixels) Effective pixels (5000 pixels) ∗1 The transfer pulses (φ1, φ2, φ3) must have more than 2545 cycles. Dummy signal (66 pixels) Dummy signal (24 pixels) D61 D62 Optical black (42 pixels) D63 D64 5 D65 D66 φCLP S1 S2 0 S3 S4 5 S4995 S4996 φRS S4997 S4998 0 S4999 S5000 5 D67 D68 φ2 φ2L D69 D70 0 D71 D72 5 D73 D74 φ1 D75 D76 0 D77 D78 5 D79 D80 φROG D81 D82 1 D83 D84 2 D85 D86 3 D87 D88 2545 D89 –5– D90 Clock Timing Chart 1∗1 ILX115LA ILX115LA Clock Timing Chart 2 t4 t5 φROG t2 t6 φ1 t7 t1 t3 φ2 φ2L Clock Timing Chart 3 t6 t7 φ1 φ2 φ2L t15 t9 t10 t8 φRS t11 t14 t12 φCLP t13 t16 t18 ,, , VOUT t17 –6– ILX115LA Clock Timing Chart 4 Cross point φ1 and φ2 φ1 φ2 5V 2.0V (Min.) 1.5V (Min.) 2.0V (Min.) 0.5V (Min.) 0V Cross point φ1 and φ2L φ1 φ2L 5V 0V Clock Pulse Recommended Timing Item Symbol Min. Typ. Max. Unit φROG, φ1 pulse timing t1 50 100 — ns φROG pulse high level period t2 600 1000 — ns φROG, φ1 pulse timing t3 400 1000 — ns φROG pulse rise time t4 0 10 100 ns φROG pulse fall time t5 0 10 100 ns φ1 pulse fall time /φ2 pulse rise time t6 0 5 10 ns φ1 pulse rise time /φ2 pulse fall time t7 0 5 10 ns φRS pulse rise time t8 0 5 10 ns φRS pulse fall time t9 0 5 10 ns — ns — ns φRS pulse low level period t10 8 φRS, φCLP pulse timing 1 t11 0 200∗1 50∗1 φCLP pulse rise time t12 0 5 10 ns φCLP pulse fall time t13 0 5 10 ns — ns — ns φRS, φCLP pulse timing 2 t14 16 φCLP φ2L pulse timing t15 0 200∗1 70∗1 Signal output delay time for φRS t16 — 12 — ns Signal output delay time for φCLP t17 — 4 — ns Signal output delay time for φ2L t18 — 12 — ns ∗1 These timing is the recommended condition under fφRS = fφCLP = 1MHz. –7– 0.1µF 47µF 16V 37 φ2L 38 NC 39 VREF 40 NC 41 VOUT-ODD (G) VDD 4 VOUT-EVEN (R) VOUT-EVEN (G) 3 VOUT-ODD (R) 2 VOUT-EVEN (B) 1 φCLP 100Ω φCLP 8 NC 9 φ2 φ2 10 NC 11 NC 12 NC 13 NC 14 SWCLP 15 φ2 φ2 16 NC 18 φROG (R) 19 IC1 φROG (R) 100Ω 17 NC 20 21 22 Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. ∗1 Data rate fφRS = 1MHz. φRS NC 7 NC GND VOUT-ODD (R) VOUT-ENEN (B) 100Ω φRS 6 GND VOUT-ODD (B) VOUT-ENEN (R) NC 5 2Ω 36 NC 42 2Ω 35 NC Buffer1 9V 23 24 25 26 27 28 29 30 31 32 33 34 φ1 100Ω NC 100Ω NC 43 2Ω NC NC 44 2Ω IC1 φROG (B) NC 100Ω φ1 φROG (G) φ1 φ1 φROG (G) φ2L NC 3.3µF VOUT-ODD (B) VOUT-ENEN (G) VOUT-ODD (G) VDD Buffer1 φROG (B) Buffer1 NC Buffer1 NC Buffer1 –8– Buffer1 Application Circuit∗1 OUT 5.1kΩ 100Ω 2SC2785 Buffer 1: IN 9V IC1: 74AC04 ILX115LA ILX115LA Example of Representative Characteristics (VDD = 9V, Ta = 25°C) Spectral sensitivity characteristics (Standard characteristics) Relative sensitivity 1.0 0.8 0.6 0.4 0.2 0 400 500 450 550 600 Wavelength [nm] Dark output voltage rate vs. Ambient temperature (Standard characteristics) 10 Output voltage rate Dark output voltage rate 10 1 0.1 –10 0 10 20 30 40 50 1 0.1 60 1 10 5 Ta – Ambient temperature [°C] τ int – Integration time [ms] Offset level vs. Supply voltage (Standard characteristics) Offset level vs. Ambient temperature (Standard characteristics) 10 10 8 8 Vos – Offset level [V] Vos – Offset level [V] 700 Output voltage rate vs. Integration time (Standard characteristics) 100 6 4 6 4 2 2 0 650 8.5 9.0 0 –10 9.5 0 10 20 30 40 Ta – Ambient temperature [°C] VDD – Supply voltage [V] –9– 50 60 ILX115LA Notes of Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates, use boxes treated for prevention of static charges. 2) Notes on Handling CCD Cer-DIP Packages The following points should be observed when handling and installing cer-DIP packages. a) Remain within the following limits when applying a static load to the ceramic portion of the package: (1) Compressive strength: 39N/surface (Do not apply load more than 0.7mm inside the outer perimeter of the glass portion.) (2) Shearing strength: 29N/surface (3) Tensile strength: 29N/surface (4) Torsional strength: 0.9Nm , , , , Upper ceramic layer 39N Lower ceramic layer (1) Low-melting glass 29N 29N 0.9Nm (2) (3) (4) b) In addition, if a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the ceramic portion. Therefore, for installation, either use an elastic load, such as a spring plate, or an adhesive. c) Be aware that any of the following can cause the glass to crack: because the upper and lower ceramic layers are shielded by low-melting glass, (1) Applying repetitive bending stress to the external leads. (2) Applying heat to the external leads for an extended period of time with a soldering iron. (3) Rapid cooling or heating. (4) Applying a load or impact to a limited portion of the low-melting glass with a small-tipped tool such as tweezers. (5) Prying the upper or lower ceramic layers away at a support point of the low-melting glass. Note that the preceding notes should also be observed when removing a component from a board after it has already been soldered. 3) Soldering a) Make sure the package temperature does not exceed 80°C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded 30W soldering iron and solder each pin in less then 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an imaging device, do not use a solder suction equipment. When using an electric desoldering tool, ground the controller. For the control system, use a zero cross type. – 10 – ILX115LA 4) Dust and dirt protection a) Operate in clean environments. b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. 5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. 6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks. – 11 – – 12 – 5.0 ± 0.5 4.0 ± 0.5 ~ V 25.0 Cer-DIP TIN PLATING 42ALLOY 11.5g LS-B15-01(E) PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE MASS DRAWING NUMBER 1.778 H 11.1 ± 0.8 ~ 5.0 No.1 pixel(Blue) A' 44.450 29.0 84.0 70.0(14µmX5000Pixels) 89.0 ± 1.0 44pin SDIP(400mil) A' 0.46 (AT STAND OFF) 10.16 10.0 ± 0.8 4. The notch of the package must not be used for reference of fixing. 3. The thickness of the cover glass is 0.7mm, and the refractive index is 1.5. 2. The height from the bottom to the sensor surface is 2.4 ± 0.3m. 1. The point “A” of the package is the horizontal reference. The two points “A'” of the package are the vertical reference. ~ 5.0 8.4 3.90 2.0 6.68 PACKAGE STRUCTURE A 0.25 Unit: mm 9˚ 4.60 ± 0.5 0˚ to Package Outline ILX115LA