ILX510 5150-pixel CCD Linear Sensor (B/W) For the availability of this product, please contact the sales office. Description The ILX510 is a reduction type CCD linear sensor developed for high resolution copiers. This sensor reads A3-size documents at a density of 400 DPI, and A4-size documents at a density of 600 DPI at high speed. 12 φROG GND 11 VDD φ1-ODD 10 9 8 φ2-ODD CCD analog shift register Read out gate Read out gate CCD analog shift register φ1-EVEN 13 14 φ2-EVEN D75 Pin Configuration (TOP VIEW) S5150 V °C °C S5149 15 –10 to +60 –30 to +80 D94 Absolute Maximum Ratings • Supply voltage VDD • Operating temperature • Storage temperature Block Diagram fROG pulse generator Features • Number of effective pixels: 5150 pixels • Pixel size: 7 µm×7 µm (7 µm pitch) • Signal output phase of two-output simultaneous-output (alternate-output is available) • Ultra high sensitivity/Ultra low lag • Max Data Rate: 40 MHz • Single 12 V power supply • Input Clock Pulse: CMOS 5V drive • Package: 22 pin cer-DIP (400 mil) 20 pin DIP (Cer-DIP) S2 1 D74 VGG 2 S1 22 GND NC 1 21 GND D26 13 φ1-EVEN 6 φLH-ODD 5 φRS-ODD VDD Output amplifer 4 AAA AAA 17 18 AAA AAA Output amplifer 3 φ1-ODD 10 VOUT-ODD 14 φ2-EVEN 2 φ2-ODD 9 VGG 15 NC 22 GND 8 GND 16 NC 20 NC 7 VOUT-EVEN 17 φLH-EVEN φRS-EVEN φLH-ODD 6 19 18 φRS-EVEN VDD φRS-ODD 5 21 19 VDD VDD 4 GND 20 VOUT-EVEN 3 φLH-EVEN D25 VOUT-ODD 5150 VDD 11 12 φROG Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. —1— E94106-TE ILX510 Pin Description Pin No 1 2 3 4 5 6 7 8 9 10 11 Symbol NC VGG VOUT-ODD VDD φRS-ODD φLH-ODD NC GND φ2-ODD φ1-ODD VDD Description NC Output circuit gate bias Signal out (odd pixel) 12 V power supply Clock pulse input (odd pixel) Clock pulse input (odd pixel) NC GND Clock pulse input (odd pixel) Clock pulse input (odd pixel) 12 V power supply Pin No 12 13 14 15 16 17 18 19 20 21 22 Symbol φROG φ1-EVEN φ2-EVEN NC NC φLH-EVEN φRS-EVEN VDD VOUT-EVEN GND GND Description Readout gate clock pulse input Clock pulse input (even pixel) Clock pulse input (even pixel) NC NC Clock pulse input (even pixel) Clock pulse input (even pixel) 12 V power supply Signal out (even pixel) GND GND Recommended Supply Voltage Item VDD Min. 11.4 Typ. 12 Max. 12.6 Unit V Clock Characteristics Item Input capacity of φ1∗, f2∗ Input capacity of φLH∗ Input capacity of φRS∗ Input capacity of φROG Symbol Cφ1, Cφ2 CφLH CφRS CφROG Min. — — — — Typ. 400 10 10 10 Max. — — — — Unit pF pF pF pF ∗It indicates that φ1-ODD, φ1-EVEN as φ1, φ2-ODD, φ2-EVEN as φ2, φLH-ODD, φLH-EVEN as φLH, φRS-ODD, φRS-EVEN as φRS. Clock Frequency Item φ1, φ2, φLH, φRS Data rate Symbol fφ1, fφ2,fφLH,fφRS fφR Min. — — Typ. 1 2 Max. 20 40 Unit MHz MHz High level Low level Min. 4.75 — Typ. 5.0 0 Max. 5.25 0.1 Unit V V Input Clock Pulse Voltage Condition Item φ1, φ2, φLH, φRS, φROG pulse voltage —2— ILX510 Electrooptical Characteristics (Note 1) (Ta = 25 °C, VDD = 12 V, Data rate fφR=2 MHz, Simultaneous output, Input clock =5 Vp-p Light source = 3200 K, IR cut filter CM-500S (t = 1.0 mm) Item Sensitivity 1 Sensitivity 2 Sensitivity nonuniformity Saturation output voltage Saturation exposure Register imbalance Dark voltage average Dark signal nonuniformity Image lag Supply current Total transfer efficiency Output impedance Offset level Dynamic range Symbol R1 R2 PRNU VSAT SE RI VDRK DSNU IL IVDD TTE ZO VOS DR Min. 9 — — 1.0 0.067 — — — — — 92 — — 500 Typ. 12 27.4 4 1.5 0.125 2 0.3 0.6 0.02 30 98 150 6.5 5000 Max. 15 — 10 — — 7 2.0 3.0 — 60 — — — — Unit Remarks V/(lx • s) Note2 V/(lx • s) Note3 % Note4 V Note5 lx • s Note6 % Note7 mV Note8 mV Note9 % Note10 mA — % — Ω — V Note11 — Note12 Note 1) In accordance with the given electrooptical characteristics, the even black level is defined as the average value of D6, D8 to D24. The odd black level is defined as the average value of D5, D7 to D23. 2) For the sensitivity test light is applied with a uniform intensity of illumination. 3) W lamp (2854 K). 4) PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 2. VOUT=500 mV (Typ.) PRNU = (VMAX – VMIN)/2 ×100 (%) VAVE Where the 5150 pixels are divided into blocks of 103, even and odd pixels, respectively. The maximum output of each block is set to VMAX, the minimum output to VMIN and the average output to VAVE. 5) Use below the minimum value of the saturation output voltage. 6) Saturation exposure is defined as follows. SE = VSAT R1 7) RI is defined as indicated below. VOUT=500 mV (Typ.) RI = VODD-AVE – VEVEN-AVE ×100 (%) VODD-AVE + VEVEN-AVE 2 ( ) Where average of odd pixels output is set to VODD-AVE, even pixels to VEVEN-AVE. —3— ILX510 8) Optical signal accumulated time τ int stands at 10 ms. 9) The difference between the maximum and average values of the dark output voltage is calculated for even and odd respectivery. The larger value is defined as the dark signal nonuniformity. Optical signal accumulated time t int stands at 10 ms. 10) VOUT = 500 mV (Typ.) 11) Vos is defined as indicated bellow. VOUT AAAA VOS GND 12) Dynamic range is defined as follows. DR = VSAT VDRK When the optical signal accumulated time is shorter, the dynamic range gets wider because the optical signal accumulated time is in proportion to the dark voltage. —4— —5— AAAAAAA AA A A A AA A A A A AAAAAAA A S1 S2 D73 D74 D71 D72 D69 D70 D27 D28 D25 D26 D23 D24 D5 D6 D3 D4 D1 D2 1-line output period (5244 pixels) Optical black (48 pixels) Dummy signal (74 pixels) S3 S4 Note) The transfer pulses (φ1, φ2, φLH) must have more than 2622 cycles. VOUT-EVEN VOUT-ODD S5145 S5146 φRS-ODD 5 φRS-EVEN 0 S5147 S5148 0 S5149 S5150 5 D75 D76 φ2-ODD φ2-EVEN D77 D78 φ1-ODD 5 φ1-EVEN φLH-ODD 0 φLH-EVEN 1 D79 D80 0 2 D81 D82 5 3 D83 D84 φROG D93 D94 Clock Timing Chart 1 (simultaneous output) ILX510 2622 ILX510 Clock Timing Chart 2 t4 t5 φROG t2 t7 t6 φ1 φLH t1 t3 φ2 Clock Timing Chart 3 t7 t6 φ1 φLH t14 t15 t17 φ2 t16 t11 t10 φRS t9 t8 VOUT-ODD VOUT-EVEN AAAAAAAA AAAAAAAA t12 t13 AAA AAA Clock timing of φ1, φ2, φLH, φRS, and VOUT at odd or even are the same as timing chart 3 in the case of alternate output. —6— ILX510 Clock Timing Chart 4 Cross point φ1 and φ2 φ1 φ2 5V 1.5V (Min.) 1.5V (Min.) 2.0V (Min.) 0.5V (Min.) 0V Cross point φLH and φ2 φ2 5V φLH 0V —7— 0 5 0 5 —8— 0 5 0 5 D73 D70 D71 D69 D28 D26 D27 D25 D24 D23 Dummy signal (74 pixels) AAAAA AAA A AAAAAA A S5148 S5146 S5147 S5145 S4 S2 S3 D74 S1 1-line output period (5244 pixels) Optical black (48 pixels) D72 D5 D3 D1 D93 D84 D82 D83 D80 D81 D78 D79 D76 D77 S5150 D75 S5149 ∗Alternate output is available by making φ1-EVEN, φ2-EVEN, φLH-EVEN, φRS-EVEN delayed to φ1-ODD, φ2-ODD, φLH-ODD, φRS-ODD for half a cycle. Note) The transfer pulses (φ1, φ2, φLH) must have more than 2622 cycles. VOUT-EVEN φRS-EVEN 5 0 VOUT-ODD φRS-ODD φ2-EVEN 5 φ1-EVEN φLH-EVEN 0 φ2-ODD φ1-ODD φLH-ODD 1 D2 0 2 D4 5 3 D6 φROG 2622 D94 Clock Timing Chart 5 (alternate output) ILX510 ILX510 Clock Pulse Recommended Timing φROG, φ1pulse timing φROG pulse high level period φROG, φ1 pulse timing φROG pulse rise time φROG pulse fall time φ1 pulse rise time /φ2 pulse fall time φ1 pulse fall time / φ2 pulse rise time φRS pulse high level period φRS, φLH pulse timing φRS pulse rise time φRS pulse fall time Signal output delay time φ1, φLH pulse low level period/φ2 pulse high level period φ1, φLH pulse high level period/φ2 pulse low level period Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14, t16 t15, t17 (∗) These timing is the recommended condition under fφ1=1 MHz. —9— Min. 50 600 400 0 0 0 0 20 0 0 0 — — 25 25 Typ. 100 1000 1000 5 5 20 20 250∗ 250∗ 10 10 8 8 500∗ 500∗ Max. — — — 10 10 60 60 — — 30 30 — — — — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns —10— 47µF/16V 0.1µF 3 5.1kΩ 100Ω VOUT-ODD 2 1 Tr1 φ RS 5 100Ω φ LH 6 VDD 4 7 8 2Ω 2Ω 12 φ2 9 φ1 IC1 11 13 10 14 15 16 φ 2-ODD 17 18 19 100Ω Tr1 φ 1-EVEN φ 1-ODD VOUT-EVEN φ RS-EVEN φ RS-ODD IC1 φ ROG φ ROG Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party and other right due to same. ∗Data rate fφR = 2 MHz 0.1µF 12V 20 21 GND NC GND VGG VOUT-EVEN VOUT-ODD 22 100Ω 5.1kΩ φ LH-EVEN φ LH-ODD VDD NC NC NC GND φ 2-EVEN VDD Application Circuit ∗ (inphase output) IC1 : 74AC04 Tr1 : 2SC2785 ILX510 ILX510 Example of Representative Characteristics (VDD = 12 V, Ta = 25 °C) Spectral sensitivity characteristics (Standard characteristics) 1.0 Relative sensitivity 0.8 0.6 0.4 0.2 0 400 500 600 700 800 900 1000 WAVELENGTH (nm) MTF of main scanning direction (Standard characteristics) Spatial frequency (cycles/mm) 0 14.3 28.6 42.9 57.1 71.4 0 0.2 0.4 0.6 0.8 1.0 1.0 0.8 MTF 0.6 0.4 0.2 0 Normalized spatial frequency Integration time output voltage characteristics (Standard characteristics) Dark signal output temperature characteristics (Standard characteristics) 10 Output voltage rate Output voltage rate 5 1 0.5 1 0.5 0.1 0.1 0 10 20 30 40 50 60 1 5 τ int-integration time (ms) Ta-Ambient temperture (°C) —11— 10 ILX510 Operational frequency response of supply supply current (Standard characteristics) IVDD-supply current (mA) Ta = 25°C 30 20 10 0 20 40 Data rate føR (MHz) Offset level vs. VDD characteristics (Standard characteristics) Ta = 25°C VOS-Offset level (V) 10 8 6 4 ∆VOS ~ –0.2 ∆VDD 2 0 11.4 12.0 12.6 VDD (V) Offset level vs. Temperature characteristics (Standard characteristics) VOS-Offset level (V) 10 ∆VOS ∆Ta 8 ~ 8 mV/°C 6 4 2 0 10 20 30 40 Ta-Ambient temperature (°C) —12— 50 60 ILX510 Notes of Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates, use boxes treated for prevention of static charges. 2) Notes on Handling CCD Cer-DIP Packages The following points should be observed when handling and installing cer-DIP packages. a) Remain within the following limits when applying static load to the ceramic portion of the package: (1) Compressive strength: 39 N/surface (Do not apply load more than 0.7 mm inside the outer perimeter of the glass portion.) (2) Shearing strength: 29 N/surface (3) Tensile strength: 29 N/surface (4) Torsional strength: 0.9 Nm b) In addition, if a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the ceramic portion. Therefore, for installation, either use an elastic load, such as a spring plate, or an adhesive. Upper ceramic layer 39N Lower ceramic layer (1) 29N Low-melting glass 29N (2) (3) 0.9Nm (4) c) Be aware that any of the following can cause the glass to crack: because the upper and lower ceramic layers are shielded by low-melting glass, (1) Applying repetitive bending stress to the external leads. (2) Applying heat to the external leads for an extended period of time with soldering iron (3) Rapid cooling or heating (4) Rapid cooling or impact to a limited portion of the low-melting glass with a small-tipped tool such as tweezers. (5) Prying the upper or lower ceramic layers away at a support point of the low-melting glass. Note that the preceding notes should also be observed when removing a component from a board after it has already been soldered. 3) Soldering a) Make sure the package temperature does not exceed 80 °C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded 30 W soldering iron and solder each pin in less then 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an imaging device, do not use a solder suction equipment. When using an electric desoldering tool, ground the controller. For the control system, use a zero cross type. —13— ILX510 4) Dust and dirt protection a) Operate in clean environments. b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. 5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. 6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks. —14— ILX510 Package Outline Unit : mm 55.7 ± 0.5 V 12 9.0 10.0 ± 0.5 5.0 ± 0.5 22 No.1 Pixel H 1 54.2 11 (AT STAND OFF) 10.16 36.05 (7µm × 5150Pixels) 11.12 ± 0.5 0.25 0° to 9° 22pin DIP (400mil) 2.54 3.58 4.38 ± 0.5 4.0 ± 0.5 1. The height from the bottom to the sensor surface is 2.38 ± 0.3mm. 0.51 0.3 M PACKAGE STRUCTURE PACKAGE MATERIAL Cer-DIP LEAD TREATMENT TIN PLATING LEAD MATERIAL 42 ALLOY PACKAGE WEIGHT 7.1g —15— 2. The thickness of the cover glass is 0.8mm, and the refractive index is 1.5.