SN75DP130 SLLSE57 – APRIL 2011 www.ti.com DisplayPort™1:1 Re-Driver with Link Training Check for Samples: SN75DP130 FEATURES APPLICATIONS • • • • • 1 2 • • • • • • • • • Supports DP v1.1a and DP v1.2 Signaling Including HBR2 Data Rates to 5.4Gbps Supports HDMI 1.4a with TMDS Clock Frequencies up to 340MHz Glue-Less interface to AMD, Intel, and NVIDIA Graphics Processors Auto-Configuration Through Link Training Output Signal Conditioning with Tunable Voltage Swing and Pre-Emphasis Gain Highly Configurable Input Variable Equalizer Two Device Options Including a Dual Power Supply Configuration for Lowest Power 2kV ESD HBM Protection Temperature Range: 0°C to 85°C 48 Pin 7mm × 7mm QFN Package Notebook PC Desktop PC PC Docking Station PC Standalone Video Card DESCRIPTION The SN75DP130 is a single channel DisplayPort™ (DP) re-driver that regenerates the DP high speed digital link. The device complies with the VESA DisplayPort Standard Version 1.2, and supports a four lane Main Link interface signaling up to HBR2 rates at 5.4Gbps per lane, and supports DP++ Dual-Mode; offering TMDS signaling for DVI and full HDMI Version 1.4a support. The device compensates for PCB related frequency loss and switching related loss to provide the optimum DP electrical performance from source to sink. The Main Link signal inputs feature configurable equalizers with selectable boost settings. At the Main Link output, four primary levels of differential output voltage swing (VOD) and four primary levels of pre-emphasis are available, as well as a secondary level of boost adjustment, programmed through I2C, for fine-tuning the Main Link output. The device can monitor the AUX channel and automatically adjust the output signaling levels and input equalizers in response to Link Training commands. Additionally, the SN75DP130 output signal conditioning and EQ parameters are fully programmable through the I2C interface. The SN75DP130 offers separate AUX and DDC source interfaces that connect to a single AUX sink channel. This minimizes component count when implemented with a graphics processor (GPU) comprising separate DDC and AUX interfaces. For GPUs with combined DDC/AUX, the device can operate as a FET switch to short circuit the AUX channel AC coupling caps while connected to a TMDS sink device. Other sideband circuits such as Hot Plug Detect (HPD) are optimized to reduce external components, providing a seamless connection to Intel, AMD, and NVIDIA graphics processors. The SN75DP130 is optimized for mobile applications, and contains activity detection circuitry on the Main Link input that transitions to a low-power Output Disable mode in the absence of a valid input signal. Other low power modes are supported, including a Standby mode with typical dissipation of ~2mW when no video sink (e.g., monitor) is connected. The device is characterized for an extended operational temperature range from 0°C to 85°C. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DisplayPort is a trademark of VESA Standards Association. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011, Texas Instruments Incorporated SN75DP130 SLLSE57 – APRIL 2011 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. TYPICAL IMPLEMENTATIONS The configuration shown in Figure 1 supports a GPU with unified AUX/DDC interfaces. This circuit provides back current protection into the GPU AUX, HPD, and CAD inputs. DP++ MultiMode Source Side Re-driver; GPU w/ Unified DDC & AUX Outputs; AUX & DDC Internal Mux Utilized; AUX Channel Monitored for Link Training SN75DP130 4 diff MAIN[3:0] HPD_SRC HPD 4 diff OUT[3:0] IN[3:0] DP Connector GPU HPD_SNK CAD_SNK DDC DDC AUXSNKAUXSNK+ AUXSRCAUXSRC+ AUX 1M 3.3V RI2C RI2C 100kW 100kW SCL_CTL SDA_CTL I2C 3.3V Optional I2C interface may be used to fully configure output signal conditioning and EQ settings. 10kW resistors are recommended for RI2C. 100kWresistors shall be placed on the AUXSNK side to ensure proper device internal channel biasing, and to ensure the sink device identifies the source during power down conditions. Figure 1. DP++ Dual-Mode in a Unified AUX/DDC Configuration The configuration shown in Figure 2 supports a GPU with separate DDC and AUX interfaces, and overcomes the need for an external AUX to DDC switch. This circuit provides back current protection into the GPU AUX, HPD, and CAD inputs. DP++ MultiMode Source Side Re-driver; GPU w/ Separate DDC & AUX Outputs; AUX & DDC Internal Mux Utilized; AUX Channel Monitored for Link Training SN75DP130 4 diff IN[3:0] MAIN[3:0] HPD 3.3V RDDC HPD_SRC 4 diff OUT[3:0] DP Connector GPU HPD_SNK CAD_SNK RDDC DDC DDC AUX AUXSRCAUXSRC+ AUXSNKAUXSNK+ 1M 3.3V RI2C I2C RI2C 100kW 100kW SCL_CTL SDA_CTL 3.3V The use of RDDC is optional. The SN75DP130 integrates 60kWpullups and a cable adapter should include 2kWpullup for each line. If it is uncertain if the cable adapter includes 2kW pullup resistance, use 10kWfor RDDC. Optional I2C interface may be used to fully configure output signal conditioning and EQ settings. 10kW resistors are recommended for RI2C. 100kWresistors shall be placed on the AUXSNK side to ensure proper device internal channel biasing, and to ensure the sink device identifies the source during power down conditions. Figure 2. DP++ Dual-Mode in a Split AUX and DDC Configuration 2 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): SN75DP130 SN75DP130 SLLSE57 – APRIL 2011 www.ti.com BLOCK DIAGRAM VCC CAD_SRC CADout CAD_SNK CADin HPD_SNK HPDin ADDR_EQ ADDR_EQ RinHPD HPD_SRC VDDD ~130k HPDout RRST=150k VCC VDDD (VCORE) GND RSTN EN RESET IN VREG EN OUT REN=200k VIterm VBIAS VCC 50 50 50 IN0p EQ IN0n 50 OUT0p DP++ Driver OUT0n VIterm 50 VBIAS 50 50 50 IN1p EQ OUT1p DP++ Driver IN1n OUT1n VIterm 50 VBIAS 50 50 50 IN2p EQ IN2n OUT2p DP++ Driver VIterm 50 OUT2n VBIAS 50 50 IN3p EQ 50 OUT3p DP++ Driver IN3n OUT3n AMPL PRE_EMP OE ADDR_EQ SCL_CTL SDA_CTL HPDout ctrl[3:1] I2C Target CADin HPDin EN ADDR_EQ vcc EQ Control OE CTRL CADout AEQ(Lx) CADin Registers RDDC PRE_EMP CADin RDDC SCL_DDC SDA_DDC DPCD Training Logic AMPL PRE_EMP ctrl2 ctrl1 AUX_SRCp AUX_SRCn AUX_SNKp AUX_SNKn Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): SN75DP130 3 SN75DP130 SLLSE57 – APRIL 2011 www.ti.com NC VCC AUX_SNKn 28 27 EN 30 29 AUX_SNKp AUX_SRCp AUX_SRCn GND 31 SDA_DDC 35 34 33 32 SCL_DDC VCC 36 37 RSTN VCC TERMINAL ASSIGNMENTS 26 25 24 GND IN0p 38 23 OUT0p IN0n 39 22 OUT0n NC 40 21 NC IN1p 41 20 OUT1p 19 OUT1n IN1n 42 NC 43 IN2p SN75DP130SS GND 44 17 OUT2p IN2n 45 16 OUT2n NC 46 15 NC IN3p 47 14 OUT3p IN3n 48 1 13 12 OUT3n 3 4 5 6 7 8 9 10 11 ADDR_EQ SCL_CTL SDA_CTL VCC NC CAD_SRC HPD_SRC CAD_SNK HPD_SNK 2 VDDD_DREG VCC (TOP VIEW) VCC 18 VDDD 28 27 VDDD EN AUX_SNKn 30 29 AUX_SNKp AUX_SRCp AUX_SRCn GND 31 SCL_DDC 35 34 33 32 SDA_DDC VDDD 36 37 RSTN VCC Figure 3. SN75DP130SS Single Supply 26 25 24 GND 41 20 OUT1p IN1n 42 SN75DP130DS 19 OUT1n VDDD 43 (TOP VIEW) 18 GND IN2p 44 17 OUT2p IN2n 45 16 OUT2n NC 46 15 VDDD IN3p 47 14 OUT3p IN3n 48 1 13 12 OUT3n 3 4 5 6 7 8 9 10 11 HPD_SNK 2 VDDD VDDD IN1p CAD_SNK 21 HPD_SRC 40 CAD_SRC OUT0n NC NC 22 VDDD 39 SCL_CTL IN0n SDA_CTL OUT0p ADDR_EQ 23 VDDD_DREG 38 VCC IN0p Figure 4. SN75DP130DS Dual Supply 4 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): SN75DP130 SN75DP130 SLLSE57 – APRIL 2011 www.ti.com PIN FUNCTIONS PIN NAME I/O NO. DESCRIPTION MAIN LINK TERMINALS IN0p, IN0n 38, 39 Input (100Ω diff) DisplayPort Main Link Lane 0 Differential Input IN1p, IN1n 41, 42 IN2p, IN2n 44, 45 IN3p, IN3n 47, 48 OUT0p, OUT0n 23, 22 OUT1p, OUT1n 20, 19 OUT2p, OUT2n 17, 16 DisplayPort Main Link Lane 2 Differential Output OUT3p, OUT3n 14, 13 DisplayPort Main Link Lane 3 Differential Output DisplayPort Main Link Lane 1 Differential Input DisplayPort Main Link Lane 2 Differential Input DisplayPort Main Link Lane 3 Differential Input Output (100Ω diff) DisplayPort Main Link Lane 0 Differential Output DisplayPort Main Link Lane 1 Differential Output AUX CHANNEL AND DDC DATA TERMINALS AUX_SRCp, AUX_SRCn 30, 29 I/O (100Ω diff) Source Side Bidirectional DisplayPort Auxiliary Data Channel. If the AUX_SNK channel is used for monitoring only, these signals are not used and may be left open. AUX_SNKp, AUX_SNKn 28, 27 I/O (100Ω diff) Sink Side Bidirectional DisplayPort Auxiliary Data Channel. SCL_DDC, SDA_DDC 33, 34 I/O Bidirectional I2C Display Data Channel (DDC) for TMDS mode. These signals may be utilized together with AUX_SNK to form a FET switch to short-circuit the AC coupling capacitors during TMDS operation in a DP++ Dual-Mode configuration. These terminals include integrated 60 kΩ pull-up resistors HPD, CAD, and CONTROL TERMINALS HPD_SRC 9 O Hot Plug Detect Output to the DisplayPort Source. HPD_SNK 11 I DisplayPort Hot Plug Detect Input from Sink. This device input is 5V tolerant. Note: Pull this input high during compliance testing or use I2C control interface to go into compliance test mode and control HPD_SNK and HPD_SRC by software. CAD_SRC 8 O DP Cable Adapter Detect Output. This output typically drives the GPU CAD input. CAD_SNK 10 I DisplayPort Cable Adapter Detect Input. This input tolerates a 5V supply with a supply impedance higher than 90kΩ. A device internal zener diode limits the input voltage to 3.3V. An external 1MΩ resistor to GND is recommended. This terminal is used to select DP mode or TMDS mode in a DP++ Dual-Mode application. SCL_CTL, SDA_CTL 4, 5 I/O RSTN 35 I Bidirectional I2C interface to configure the SN75DP130. This interface is active independent of the EN input but inactive when RSTN is low. Active Low Device Reset. This input includes a 150kΩ resistor to the VDDD core supply. An external capacitor to GND is recommended on the RSTN input to provide a power-up delay. This signal is used to place the SN75DP130 into Shutdown mode for the lowest power consumption. When the RSTN input is asserted, all outputs (excluding HPD_SRC and CAD_SRC) are high-impedance, and inputs (excluding HPD_SNK and CAD_SNK) are ignored; all I2C and DPCD registers are reset to their default values. At power up, the RSTN input must not be de-asserted until the VCC and VDDD supplies have reached at least the minimum recommended supply voltage level. EN 26 ADDR_EQ 3 I Device Enable. This input incorporates an internal pullup of 200kΩ. 3-level Input I2C Target Address Select and EQ Configuration Input. If the I2C bus is used, this input setting selects the I2C target address, as described in Table 7. This input also configures the input EQ to the device, as described in Table 5. SUPPLY AND GROUND TERMINALS VDDD VCC SN75DP130DS Digital low voltage core and Main Link supply for SN75DP130DS device option. 6, 12, 15, 21, 25, 32, 37, Nominally 1.1V. 43 SN75DP130SS 1, 6, 12, 25, 32, 36 3.3V Supply SN75DP130DS 1, 36 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): SN75DP130 5 SN75DP130 SLLSE57 – APRIL 2011 www.ti.com PIN FUNCTIONS (continued) PIN NAME I/O NO. VDDD_DREG 7 GND 18, 24, 31, 37, 43, and Exposed Thermal Pad NC SN75DP130SS 15, 21, 37, 43 DESCRIPTION SN75DP130SS: Digital voltage regulator decoupling; install 1µF to GND. SN75DP130DS: Treat same as VDDD; this pin will be most noisy of all VDDD terminals and needs a de-coupling capacitor nearby. Ground. Reference GND connections include the device package exposed thermal pad. No Connect. These terminals may be left unconnected, or connect to GND. SN75DP130DS 7, 40, 47 ORDERING INFORMATION (1) (1) PART NUMBER PART MARKING PACKAGE SN75DP130DSRGZR DP130DS 48-pin QFN reel SN75DP130SSRGZR DP130SS 48-pin QFN reel SN75DP130DSRGZT DP130DS 48-pin QFN small quantity tape SN75DP130SSRGZT DP130SS 48-pin QFN small quantity tape For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) Supply voltage range Voltage range (1) VALUE UNIT VCC –0.3 to 4.0 V VDDD, VDDD_DREG –0.3 to 1.3 V Main link I/O differential voltage –0.3 to 1.3 V HPD_SNK –0.3 to 5.5 V –0.3 to 4 V All other terminals –65 to 150 °C Main Link I/O, AUX_SNK, HPD_SNK, CAD_SNK ±2 kV All Other Terminals ±2 kV ±500 V Storage temperature TS Electrostatic discharge Human Body Model (2) Charged-device model (1) (2) (3) (3) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Tested in accordance with JEDEC Standard 22, Test Method A114-B Tested in accordance with JEDEC Standard 22, Test Method C101-A THERMAL INFORMATION THERMAL METRIC (1) SN75DP130 QFN (48) PINS θJA Junction-to-ambient thermal resistance 35.1 θJCtop Junction-to-case (top) thermal resistance 21.5 θJB Junction-to-board thermal resistance 11.7 ψJT Junction-to-top characterization parameter, high-k board 1.2 ψJB Junction-to-board characterization parameter, high-k board 11.9 θJCbot Junction-to-case (bottom) thermal resistance 6.7 (1) 6 UNITS °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): SN75DP130 SN75DP130 SLLSE57 – APRIL 2011 www.ti.com POWER DISSIPATION TEST CONDITIONS (1) PARAMETER PN Device power under normal operation PSD Standby mode power dissipation PD3 D3 power down mode dissipation POD (1) MIN MAX UNIT 468 828 mW SN75DP130DS; 4 DP Lanes. 172 304 mW 14.4 mW SN75DP130DS; 4 DP Lanes. 7.2 mW SN75DP130SS; 4 DP Lanes. 14.4 mW SN75DP130DS; 4 DP Lanes. 7.2 mW SN75DP130SS; 4 DP Lanes. 54 mW SN75DP130DS; 4 DP Lanes. 46 mW SN75DP130SS; 4 DP Lanes. Shutdown mode power dissipation PSBY TYP SN75DP130SS; 4 DP Lanes. Output disable (squelch) mode current SN75DP130SS; 4 DP Lanes. 126 180 mW SN75DP130DS; 4 DP Lanes. 58 88 mW UNIT Test conditions correspond to Power Supply test conditions in Electrical Characteristics RECOMMENDED OPERATING CONDITIONS VCC Supply voltage VDDD Digital core and Main Link supply voltage TA Operating free-air temperature TCASE Case temperature VIH(HPD) High-level input voltage HPD_SNK VIH VIL MIN NOM MAX 3 3.3 3.6 V 0.97 1.05 1.2 V 85 °C 103.1 °C 1.9 5.5 V High-level input voltage for device control signals 1.9 3.6 V Low-level input voltage for device control signals 0 0.8 V 0.30 1.40 Vpp 5.4 Gbps 200 nF 120 Ω 2 V 0 MAIN LINK TERMINALS VID Peak-to-peak input differential voltage; RBR, HBR, HBR2 dR Data rate CAC AC coupling capacitance (each input and each output line) 75 Rtdiff Differential output termination resistance 80 VOterm Output termination voltage (AC coupled) 0 tSK(in HBR2) Intra-pair skew at the input at 5.4Gbps tSK(in HBR) Intra-pair skew at the input at 2.7Gbps 100 ps tSK(in RBR) Intra-pair skew at the input at 1.62Gbps 300 ps 100 When used as re-driver in DP source 20 When used as receiver equalizer in DP sink 100 ps AUX CHANNEL DATA TERMINALS AUX_SRCp and AUX_SNKp in DP mode VI-DC DC input voltage AUX_SRCn and AUX_SNKn in DP mode AUX_SRCp/n and AUX_SNKp/n in TMDS mode -0.5 0.3 0.4 2.0 3.0 3.6 V -0.5 3.6 1400 mVPP 1.2 Mbps VID Differential input voltage amplitude (DP mode only) 300 dR(AUX) Data rate (before Manchester encoding) 0.8 dR(FAUX) Data rate Fast AUX (300ppm frequency tolerance) tjccin_adj Cycle-to-cycle AUX input jitter adjacent cycle (DP mode only) tjccin Cycle-to-cycle AUX input jitter within one cycle (DP mode only) CAC AUX AC coupling capacitance (DP mode only) VsrcCMM AUX source common mode voltage (only applies to DP mode) CAD = VIL; measured on AUX source and sink before AC coupling caps 1 720 Mbps 0.05 UI 0.1 UI 75 200 nF 0 2000 mV DDC AND I2C TERMINALS VI Input voltage dR Data rate VIH High-level input voltage VIL Low-level input voltage -0.5 3.6 V 100 kbps 0.7VCC V 0.3VCC Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): SN75DP130 V 7 SN75DP130 SLLSE57 – APRIL 2011 www.ti.com RECOMMENDED OPERATING CONDITIONS (continued) MIN NOM MAX UNIT 100 kHz fSCL SCL clock frequency standard I2C mode tw(L) SCL clock low period standard I2C mode 4.7 µs tw(H) SCL clock high period standard I2C mode 4.0 µs Cbus Total capacitive load for each bus line 400 pF POWER SUPPLY ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER (1) ICCDP1HBR2 ICCDP2HBR2 ICCDP4HBR2 TEST CONDITIONS MIN Supply Current 1 DP Lanes Maximum conditions: IN/OUT at 5.4Gbps Supply Current 2 DP Lanes PRBS,VOD = 510mVpp, PE = 6dB; AUX at 1Mbps PRBS, VID = 1000mVpp; EQ = 3dB Typical Conditions: IN/OUT at 5.4Gbps Supply Current 4 DP Lanes PRBS,VOD = 510mVpp, PE = 0dB AUX and I2C Idle; EQ = 3dB TYP 70 mA 70 125 mA 130 230 mA Supply Current 1 DP Lanes ICCDP2HBR Supply Current 2 DP Lanes ICCDP4HBR Supply Current 4 DP Lanes ICCTMDS Supply Current TMDS Mode Main Link at 2.5Gbps PRBS, VID = VOD = 600mVpp; AUX Idle ISD Shutdown supply current Shutdown mode ISBY Standby supply current Standby mode ID3 D3 supply current D3 power down mode IOD Squelch supply current Output disable (Squelch) mode 35 (1) UNIT 40 ICCDP1HBR Main Link at 2.7Gbps PRBS, VOD =510mVpp, PE = 0dB; AUX and I2C Idle; EQ at 3dB fixed gain MAX 40 mA 70 mA 130 mA 170 mA 4 mA 3 4 mA 10 15 mA 50 mA 3 Values are VDDD supply measurements; VCC supply (DS package option) measurements are 5mA (typical) and 8mA (max), with zero current in shutdown and standby modes. MAIN LINK ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER MIN TYP MAX UNIT VOD(L0) 238 340 442 mVPP VOD(L1) 357 510 663 mVPP 484 690 897 mVPP 700 1000 1300 mVPP 420 600 780 mVPP 1.7 3.5 5.3 dB 1.6 2.5 3.5 dB 0.8 3.5 6.0 dB 0 0.25 dB VOD(L2) Output differential voltage swing TEST CONDITIONS VPRE(L0); 675Mbps D10.2 Test Pattern; BOOST=01 VOD(L3) VOD(TMDS) 675Mbps D10.2 Test Pattern; BOOST=01 ΔVOD(L0L1) ΔVOD(L1L2) Output peak-to-peak differential voltage delta ΔVOD(L2L3) ΔVODn = 20×log(VODL(n+1) / VODL(n)) measured in compliance with PHY CTS1.1D15 section 3.2 at test point TP2 using special CTS test board VPRE(L0) All VOD options VPRE(L1) VOD = VOD(L0), VOD(L1), or VOD(L2); BOOST=01 3.5 dB VOD = VOD(L0) or VOD(L1); BOOST=01 6.0 dB VOD = VOD(L0); BOOST=01 9.5 dB 10% dB –10% dB VPRE(L2) Driver output pre-emphasis (default) VPRE(L3) VPRE(BOOST) Output VPRE boost ΔVPRE(L1L0) ΔVPRE(L2L1) Pre-emphasis delta ΔVPRE(L3L2) ΔVConsBit 8 Non-transition bit voltage variation BOOST=10 BOOST=00 Measured in compliance with PHY CTS1.1D15 section 3.3 at test point TP2 using special CTS test board See CTS spec section 3.3.5 Submit Documentation Feedback 2.0 dB 1.6 dB 1.6 dB 30% Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): SN75DP130 SN75DP130 SLLSE57 – APRIL 2011 www.ti.com MAIN LINK ELECTRICAL CHARACTERISTICS (continued) over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN AEQ(HBR) Equalizer gain for RBR/HBR AEQ(HBR2) Equalizer gain for HBR2 AEQ(TMDS) Equalizer gain for TMDS ROUT Driver output impedance RIN Input termination impedance VIterm Input termination voltage VOCM(SS) Steady state output common-mode voltage ΔVOCM(SS) Change in steady state output common-mode voltage between logic levels Tested in compliance to section 3.10 in CTS 1.1a VOCM(PP) Output common-mode noise HBR2 VSQUELCH Squelch threshold voltage Programable via I2C; default at 80mVpp typical ITXSHORT Short circuit current limit Main Link outputs shorted to GND TYP MAX See Table 5 and Table 8 for EQ setting details; Max value represents the typical value for the maximum configurable EQ setting UNIT 9 dB 18 dB 3 dB Ω 50 60 Ω 0 2 V 0 2 V 40 AC coupled; self-biased 50 10 mVPP 20 mVRMS 30 mVRMS 80 mVPP 50 mA MAIN LINK SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN tPD Propagation delay time See Figure 5 tSK(1) Intra-pair output skew tSK(2) Inter-pair output skew Signal input skew = 0ps; dR = 2.7Gbps, VPRE = 0dB, 800mVp-p, D10.2 clock pattern at device input; See Figure 6 Δtjit VOD(L0); VPRE(L0); EQ = 8dB; clean source; minimum input Total peak-to-peak residual jitter and output cabling; 1.62Gbps, 2.7Gbps, and 5.4Gbps PRBS7 data pattern. tsq_enter Squelch entry time Time from active DP signal turned off to ML output off with noise floor minimized tsq_exit Squelch exit time Time from DP signal on to ML output on VOD tF tR TYP MAX 300 UNIT ps 20 ps 100 ps 15 ps 10 120 μs 0 1 μs 100% 80% 0V VOCM 20% 0% VOCM(pp) DVOCM(ss) D+ VIterm 0V to 2V D- 50 W 50 W 50 W 50 W D+ VD+ Receiver VID D- Driver Y 100pF VY Z VD- 100pF VZ VID = VD+ - VD- VOD = VY - VZ VICM = (VD+ + VD-) 2 VOCM = (VY + VZ) 2 Figure 5. Main Link Test Circuit Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): SN75DP130 9 SN75DP130 SLLSE57 – APRIL 2011 www.ti.com tOUTxp(f) tOUTxp(r) tOUTxn(f) tOUTxn(r) OUTxp 50% OUTxn tsk1 = 0.5 x | (tOUTxp(r)-tOUTxn(f)) + (tOUTxp(f)-tOUTxn(r)) | tsk2 OUTyp OUTyn Figure 6. Main Link Skew Measurements HPD/CAD ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT HPD_SRC, CAD_SRC VOH High-level output voltage IOH = 500µA 2.7 3.6 V VOL Low-level output voltage IOH = 500µA 0 0.1 V RoutCAD CAD series output resistance RoutHPD HPD series output resistance ILEAK Leakage current (1) (2) EN=RSTN=VCC; HPD_SNK=CAD_SNK=VCC 150 EN=RSTN=VCC; HPD_SNK=CAD_SNK=VCC 150 Ω Ω VCC= 0V, V(pin) = 1.2V; RSTN 20 VCC= 0V, V(pin) = 3.3V; SCL/SDA_CTL, AUX_SNKp/n 20 VCC= 0V, V(pin) = 3.3V; HPD_SNK 40 VCC= 0V, V(pin) = 3.3V; AUX_SRCp/n 60 μA HPD_SNK IH High-level input current VIH = 1.9V (leakage includes the 130kΩ pull-down resistor) –30 30 µA IL Low-level input current VIL = 0.8V (leakage includes the 130kΩ pull-down resistor) –30 30 µA VTH+ Positive going input threshold voltage RpdHPD HPD input termination to GND VCC=0V IH High-level input current VIH = 1.9V IL Low-level input current VIL = 0.8V VTH+ Positive going input threshold voltage 1.4 100 130 V 160 kΩ –1 1 µA –1 1 µA CAD_SNK (1) (2) 1.4 V A series output resistance of 100kΩ may be added in series to the CAD_SRC output to mimic a cable adapter. Applies to failsafe inputs: RSTN, SDA_CTL, SCL_CTL, SDA_DDC, SCL_DDC, AUX_SNK P/N, AUX_SRC P/N, HPD_SNK HPD/CAD SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS tPD(HPD) Propagation delay HPD_SNK to HPD_SRC tPD(CAD) Propagation delay CAD_SNK to CAD_SRC tT(HPD) HPD logic shut off time 10 VCC = 3.0V; See Figure 8 VCC = 3.0V; See Figure 9 Submit Documentation Feedback MIN TYP MAX UNIT 50 ns 50 ns 400 ms Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): SN75DP130 SN75DP130 SLLSE57 – APRIL 2011 www.ti.com TP HPD_SRC HPD_SNK TP 130 KW 100 KW SN75DP130 Figure 7. HPD Test Circuit VCC HPD_SNK HPD_SNK VCC 50% 50% 0V Sink Hot Plug Detect Timeout t T(HPD) 0V tPD(HPD) VCC VOH HPD_SRC 50% HPD_SRC VOL Device active 50% Low power 0V Figure 8. HPD Timing Diagram 1 Figure 9. HPD Timing Diagram 2 AUX/DDC/I2C ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS VPASS DDC mode passthrough voltage VCAD_SNK = VIH; IO = 100 µA CIO I/O capacitance VIO = 0 V; f(test) = 1 MHz On resistance AUX_SRCn to AUX_SNKn in DP mode VCC = 3.0 V w/ VI =2.85V or VCC = 3.6 V w/ VI = 3.4 V; IO = 5 mA On resistance SCL/SDA_DDC to AUX_SNK in TMDS mode MIN TYP MAX 1.9 UNIT V 10 pF 5 10 Ω IO = 3 mA 15 30 Ω On resistance AUX_SRC to AUX_SNK in TMDS mode IO = 3 mA 10 20 Ω ΔrON On resistance variation with input signal voltage change in DP mode VCC = 3.6 V, IO = 5 mA, VI = 2.6 to 3.4 V, VCC = 3.0 V, IO = 5 mA, VI = 0 to 0.4 V 5 Ω VID(HYS) Differential input hysterisis By design (simulation only) IH High-level input current VI = VCC -5 5 VI = GND; CAD_SNK = VIH -5 5 rON 50 mV µA µA IL Low-level input current VAUX+ Voltage on the Aux+ for PHY-CTS 3.19 1M (5%) pullup to VCC and 100kΩ pulldown to GND on AUX+; VCC = 3.3 V 0 0.4 V VAUX- Voltage on the Aux- for PHY-CTS 3.18 100kΩ pullup to VCC and 1M (5%) pulldown to GND on AUX-; VCC = 3.3 V 2.4 3.6 V |S1122| Differential line insertion loss VID = 400 mV, AC coupled; p-channel biasing 0.3 V and n-channel 3.0V; 360 MHz sine wave; CAD_SNK=VIL 1.6 3 dB RDDC Switcheable pul-lup resistor on DDC at source side (SCL_DDC, SDA_DDC) CAD_SNK = VIH 60 72 kΩ VI = GND; At DDC inputs 80 48 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): SN75DP130 11 SN75DP130 SLLSE57 – APRIL 2011 www.ti.com AUX/DDC/I2C SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS TYP VID = 400 mV, AC coupled; p-channel biasing 0.3V and n-channel 3.0V; See Figure 10 tsk(AUX) Intra-pair skew tPLH(DP) Propagation delay time, low to high tPHL(DP) Propagation delay time, high to low tPLH(DDC) Propagation delay time, low to high tPHL(DDC) Propagation delay time, high to low tPU(AUX) MIN CAD = VIL; 1Mbps pattern;See Figure 11 CAD = VIH; 100kbps pattern VID = 0.1 V, VICMM = 2 V source side (before AC coupling caps) Main Link D3 wakeup time MAX UNIT 400 ps 3 ns 3 ns 50 ns 50 ns 50 µs I2C Refer to the I2C-Bus Specification, Version 2.1 (January 2000); SN75DP130 meets the switching characteristics for standard mode transfers up to 100 kbps. 2 .2V 2.2 V AUX Input 1.8 V 50 % Differential 0V AUX Input t PHL (AUX) 1.8V t PLH(AUX) Differential AUX Output 0 V t sk(AUX ) Figure 10. AUX Skew Measurement Figure 11. AUX Delay Measurement 12 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): SN75DP130 SN75DP130 SLLSE57 – APRIL 2011 www.ti.com TYPICAL CHARACTERISTICS A. Gain represents SN75DP130 design simulation Figure 12. Typical EQ Gain Curves A. DisplayPort output jitter measured at the surface mount pins connected to the main link output channels on the SN75DP130 characterization test board; input jitter generated from test board with variable input trace lengths using 4 mil traces of lengths 2 inches to 22 inches generating the typical input jitter as represented in Table 1. Figure 13. DisplayPort Sink Jitter Performance with Optimal EQ Settings Table 1. Characterization Test Board Trace Lengths Related to Input Jitter INPUT MODE Display Port HBR2 TMDS 3.4 Gbps TRACE LENGTH (inches) TOTAL INPUT JITTER (ps) RECOMMENDED EQ SETTING 2 14.4 8 6 23.1 8 10 38.8 10 14 58.9 10 18 84.8 13 22 13.9 13 2 15.8 6 6 6 21.3 10 33.2 6 14 49.9 13 18 70.5 13 22 91.5 13 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): SN75DP130 13 SN75DP130 SLLSE57 – APRIL 2011 www.ti.com A. DisplayPort output jitter measured at the surface mount pins connected to the main link output channels on the SN75DP130 characterization test board; input jitter generated from test board with variable input trace lengths using 4 mil traces of lengths 2 inches to 22 inches generating the typical input jitter as represented in Table 1. Figure 14. TMDS Sink jitter Performance with Optimal EQ Settings Figure 16. SN75DP130 Output; 10 inch Input Trace; 13dB EQ Setting; DP Sink 14 Figure 15. Main Link Input with 10 inch Trace; DisplayPort Sink Figure 17. Main Link Input with 10 inch Trace; TMDS Sink Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): SN75DP130 SN75DP130 SLLSE57 – APRIL 2011 www.ti.com Figure 18. SN75DP130 Output; 10 inch Input Trace; 13dB EQ Setting; TMDS Sink Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): SN75DP130 15 SN75DP130 SLLSE57 – APRIL 2011 www.ti.com APPLICATION INFORMATION ADDITIONAL TYPICAL IMPLEMENTATIONS Theconfiguration shown in Figure 19 is preferred to avoid very long AUX signal stub lines. Furthermore, this configuration provides isolation between the DP connector and the GPU. DP Only Source Side Re-driver; Buffered AUX Channel (no stub lines); AUX Channel Monitored for Link Training 4 diff MAIN[3:0] SN75DP130 IN[3:0] HPD 4 diff OUT[3:0] HPD_SRC DP Connector GPU HPD_SNK 3.3V RI2C AUXSNKAUXSNK+ RI2C SCLSDA+ SCL_CTL SDA_CTL 100n AUXAUX+ AUXSRCAUXSRC+ 100kW 100n Optional I2C interface may be used to fully configure output signal conditioning and EQ settings. 10kW resistors are recommended for RI2C. 100kW 3.3V 100kWresistors shall be placed on the AUXSNK side to ensure proper device internal channel biasing, and to ensure the sink device identifies the source during power down conditions. CAD_SNK = VIL Figure 19. DP Only Configuration with AUX Pass Through The configuration shown in Figure 20 enables the SN75DP130 in DP++ Dual-Mode with the AUX input only monitoring the AUX channel. Use this setting when AUX stub lines can be kept short and minimum AUX attenuation is desired. For DP v1.1a, the stub length shall not exceed 4cm each, and for DP v1.2 with FAUX support each stub line shall be shorter than 1cm. DP++ MultiMode Source Side Re-driver; GPU w/ Unified DDC & AUX Outputs; AUX Channel Monitored for Link Training SN75DP130 4 diff MAIN[3:0] IN[3:0] HPD 4 diff OUT[3:0] HPD_SRC HPD_SNK CAD CAD_SRC CAD_SNK SCLSDA+ SCL_CTL SDA_CTL DDC AUX AUXSNKAUXSNK+ CAD CAD 1M DP connector GPU 3.3V 100kW CAD Optional I2C interface may be used to fully configure output signal conditioning and EQ settings. 10kW resistors are recommended for RI2C. 100kW Minimize Stub Line Length Figure 20. DP++ Dual-Mode Configuration with AUX Monitor The alternate configuration shown in Figure 21 allows a reduced BOM by eliminating the need for external FET switches while routing AUX and DDC externally, which eliminates any insertion loss cases of AUX is brought through the SN75DP130. For DP v1.2 with FAUX support each stub line shall be shorter than 1cm. 16 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): SN75DP130 SN75DP130 SLLSE57 – APRIL 2011 www.ti.com DP++ MultiMode Source Side Re-driver; AUX Channel AC Capacitors Short Circuited in TMDS Mode by Internal FET; AUX Channel Monitored for Link Training SN75DP130 4 diff MAIN[3:0] HPD IN[3:0] HPD_SRC CAD CAD CAD_SRC 3.3V 4 diff OUT[3:0] HPD_SNK DP connector GPU CAD CAD_SNK I2C required to select this configuration RI2C DDC AUXSNKAUXSNK+ 1M SCL_CTL SDA_CTL AUXSRCAUXSRC+ RI2C SCL SDA 3.3V 100kW AUX I2C interface may be used to fully configure output signal conditioning and EQ settings. 10kW resistors are recommended for RI2C. Option 1: CAD_OUT drives GPU; protects back current to GPU. Option 2: connect CAD signal from board connector to the GPU. 100kW Minimize Stub Line Length Figure 21. Alternate Low-BOM DP++ Dual-Mode Configuration OPERATING MODES OVERVIEW special I2C commands EN or RSTN low Power up Compliance Test Mode HPD_SNK low for >tT(HPD) EN or RSTN low Shutdown Mode Standby Mode D3 Power Down Mode EN and RSTN high HPD_SNK low for >tT(HPD) HPD_SNK high; AUX link enter D3 training started AUX cmd (CAD=0) EN or RSTN low Active Mode CAD=0 DP mode CAD=1 TMDS mode invalid DPCD register entry Exit D3 AUX cmd or CAD high any e st a t DPCD register corrected Output Disable Mode Squelch event Squelch release Figure 22. SN75DP130 Operating Modes Flow Diagram Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): SN75DP130 17 SN75DP130 SLLSE57 – APRIL 2011 www.ti.com Table 2. Description of SN75DP130 Operating Modes MODE CHARACTERISTICS CONDITIONS Shutdown Mode Least amount of power consumption (most circuitry turned off); HPD_SRC reflects HPD_SNK state; all other outputs are high-impedance; if RSTN is high local I2C IF remains active; if RSTN is low local I2C interface is turned off, all other inputs are ignored, and AUX DPCD is reset. (EN=low does not reset DPCD) EN or RSTN is low; Power on default mode Standby Mode Low power consumption (I2C IF is active; AUX monitor is inactive); Main Link outputs are disabled; EN and RSTN are high; HPD_SNK low longer than tT(HPD) Low power consumption (I2C IF is active; AUX monitor active in DP mode); Main Link outputs are disabled; EN and RSTN are high; AUX cmd requested DP sink to enter D3 power saving mode D3 Power Down Mode Data transfer (normal operation); The device is either in TMDS mode (CAD_SNK=high) or DP mode (CAD_SNK=low); Active Mode In DP mode, the AUX monitor is actively monitoring for Link Training; the output signal swing and input equalization setting depend on the Link Training or I2C settings; the AUX SRC channel is active; the AUX SNK and DDC are active unless disabled through I2C IF. At power-up all Main Link outputs are disabled by default. AUX Link Training is necessary to overwrite the DPCD registers to enable Main Link outputs. EN and RSTN are high; HPD_SNK is high; HPD_SNK can also be low for less than tZ(HPD) (e.g., sink interrupt request to source) In TMDS mode the output signal swing is 600mVpp unless this setting is adjusted by overwriting according registers through I2C IF. Transactions on the AUX lines will be ignored. Compliance Test Mode Through I2C registers the device can be forced into ignoring HPD_SNK and CAD_SNK, HPD_SRC and CAD_SRC are programmable; output swing, pre-emphasis and EQ setting are programmable; automatic power down features can be disabled EN and RSTN is high; I2C selects HPD and/or CAD test mode Output Disable Mode DPCD write commands on the AUX bus detected by the SN75DP130 will also write to the local DPCD register. The DPCD register should always be written with a valid entry. If register 101h or 103h is written with a forbidden value, the SN75DP130 disables the Main Link output signals, forcing the DP sink to issue an interrupt. The DP source can now re-train the link using valued DPCD register values. As soon as all DPCD registers contain a valid entry, the SN75DP130 switches back into the appropriate mode of operation. EN and RSTN are high; DPCD register 101h or 103h entry is invalid Table 3. Description of Operating Mode Transitions MODE TRANSITION USE CASE TRANSITION SPECIFICS Shutdown → Standby Activate SN75DP130 EN and RSTN both transitioned high Standby → Active Turn on Main Link (DP sink plugged in) HPD_SNK input asserts high Active → D3 Power Down DP source requests temporary power down for power savings Receive D3 entry command on AUX Active → Output Disable Squelch event; inactive video stream Main Link monitor detects the inactive video stream D3 Power Down → Active Exit temporary power down Receive D3 exit command on AUX, or CAD_SNK input is asserted (high) D3 Power Down → Standby Exit temporary power down (DP sink unplugged) HPD_SNK de-asserted to low for longer than tT(HPD) Active → Standby Turn off Main Link (DP sink unplugged) HPD_SNK de-asserted to low for longer than tT(HPD) Any → Shutdown Turn off SN75DP130 EN or RSTN transitions low Any → Output Disable DPCD register access error condition Invalid DPCD register access Output Disable → Active Squelch released; video stream re-activated Main Link monitor detects active video stream Output Disable → Any DPCD register error condition is corrected Appropriate operating mode is re-entered IMPLEMENTING THE RSTN SIGNAL The SN75DP130 RSTN input gives control over the device reset and to place the device into shut-down mode. When RSTN is low, all DPCD registers are reset to their default values, and all Main Link lanes are disabled. When the RSTN input returns to a high logic level, the device comes out of the Shutdown mode. To turn on the Main Link, it is necessary to either program the DPCD registers through the local I2C interface or to go through a full sequence of Link Training between DP source and DP sink. 18 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): SN75DP130 SN75DP130 SLLSE57 – APRIL 2011 www.ti.com It is critical to reset the digital logic of the SN75DP130 after the VDDD supply is stable (i.e., VDDD has reached the minimum recommended operating voltage). This is achieved by asserting the RSTN input from low to high. A system may provide a control signal to the RSTN signal that transitions low to high after the VDDD supply is stable, or implement an external capacitor connected between RSTN and GND, to allow delaying the RSTN signal during power up. The implementations are shown in Figure 23 and Figure 24. VDDD Open Drain Output RSTN GPO C RSTN R RSTN = 150 kW C Controller SN75DP130 SN75DP130 Figure 23. External Capacitor Controlled RSTN Figure 24. RSTN Input from Active Controller When implementing the external capacitor, the size of the external capacitor depends on the power up ramp of the VDDD supply where a slower ramp-up results in a larger value external capacitor. Refer to the latest reference schematic for the SN75DP130 device and/or consider approximately 200nF capacitor as a reasonable first estimate for the size of the external capacitor. When implementing a RSTN input from an active controller, it is recommended to use an open drain driver if the RSTN input is driven. This protects the RSTN input from damage of an input voltage greater than VDDD. HOT PLUG DETECT (HPD) AND CAD DESCRIPTION The SN75DP130 generates the Hot Plug Detect (HPD_SRC) signal to indicate to the source that a sink has been detected. A low HPD_SNK signal input indicates no sink device is connected. When HPD_SNK is high, the CAD_SNK signal indicates whether a DP sink (CAD_SNK=low) or a TMDS sink (CAD_SNK=high). A sink device can request a source device interrupt by pulling the HPD_SNK signal low for a duration of 0.5ms to 1.0ms. The interrupt passes through the SN75DP130. If the HPD_SNK signal goes low for longer than 2ms, the DP source determines that the sink device is disconnected. To conserve power, the SN75DP130 will go into a power saving Standby mode after the HPD signal went low for a duration of tT(HPD). In the TMDS mode the AUX training logic is disabled and the Main Link transmits with a fixed output voltage swing of 600mVpp; the pre-emphasis level is set to 0dB. Output swing and pre-emphasis level are also adjustable by I2C IF. In TMDS mode all four Main Link output lanes are enabled. Through the local I2C interface it is also possible to force the device to ignore HPD_SNK and CAD_SNK, and control HPD_SRC and CAD_SRC directly. AUX AND DDC CONFIGURATION DETAILS The SN75DP130 offers an AUX source channel (AUX_SRC), AUX sink channel (AUX_SNK), a selectable DDC interface (SDA_DDC/SCL_DDC) for TMDS mode, and a local I2C control interface (SCL_CTL / SDA_CTL). Upon power-up, the SN75DP130 enables the connection between the AUX_SNK to the appropriate source interface based on CAD_SNK. Table 4 describes the switching logic, including the programmability through the local I2C interface. Note that the DDC interface incorporates 60kΩ pull-up resistors on SDA_DDC and SCL_DDC which are turned on when CAD_SNK is high (TMDS mode) but turned off when CAD_SNK is low (DP mode). Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): SN75DP130 19 SN75DP130 SLLSE57 – APRIL 2011 www.ti.com Table 4. AUX and DDC Interface Configurations HPD_SNK I2C REGISTER BIT 04.0 I2C REGISTER BIT 04.1 CAD_SNK AUX_SNK AUX_SRC DDC AUX MONITOR 0 X X X OFF OFF OFF inactive 0 ON ON OFF active 1 ON OFF ON inactive 0 OFF ON OFF active DP sink detected; AUX_SNK disconnected from AUX_SRC; AUX_SNK monitors AUX training 1 ON ON OFF inactive TMDS cable adapter detected; AUX_SNK connects to AUX_SRC and can be used to short AC coupling caps 0 (default; works for Intel, NVIDIA, and AMD) 0 (default) 1 (NVIDIA, AMD special mode) 1 0 0 ON 1 ON 1 no sink detected; low power mode DP sink detected; AUX_SNK connects to AUX_SRC TMDS cable adapter detected; DDC connects to AUX_SNK active DP sink detected; AUX_SNK connects to AUX_SRC inactive TMDS cable adapter detected; AUX_SRC connects to AUX_SNK OFF 1 COMMENT undetermined mode not recommended MAIN LINK EQ CONFIGURATION DETAILS The EQ input stage is self-configuring based on Link Training. A variety of EQ settings are available through external pin configuration to accommodate for different PCB loss and GPU settings, and the I2C interface may be utilized to fully customize EQ configuration lane-by-lane beyond the input pin configurability options, as described in Table 5. Table 5. Main Link EQ Configurations EQ_I2C_ENABLE (reg 05.7) ADDR_EQ VIL CAD_SNK (1) VIL = DP VIH = TMDS VIL LINK TRAINING ON/OFF (reg 04.2) LINK TRAINING AEQ(Lx) (2) LANE 0 to 2 1 (default) AEQ(L0) = 8dB at 2.7GHz AEQ(L1) = 6dB at 2.7GHz AEQ(L2) = 3.5dB at 2.7GHz AEQ(L3) = 0dB at 2.7GHz 0 VIH 0 (default) VIM VIL VIH VIH VIL x 1 0 x 1 0 VIH x 1 1 x VIH 20 AEQ(Lx) = 8dB at 2.7GHz AEQ(Lx) = 8dB at 2.7GHz AEQ(L0) = 15dB at 2.7GHz AEQ(L1) = 13dB at 2.7GHz AEQ(L2) = 10dB at 2.7GHz AEQ(L3) = 6dB at 2.7GHz AEQ(Lx) = 13dB at 2.7GHz same as Lane 0 to 2 3dB at 1.35GHz TMDS mode; fixed EQ DP mode; fixed EQ same as Lane 0 to 2 DP mode; fixed EQ DP mode; fixed EQ 3dB at 1.35GHz TMDS mode; fixed EQ same as Lane 0 to 2 automatic high-range EQ gain based on link training; DP mode 3dB at 1.35GHz TMDS mode; fixed EQ DP mode; fixed EQ same as Lane 0 to 2 AEQ(L1) = 6dB at 2.7GHz AEQ(L1) I2C programmable x DESCRIPTION automatic low-range EQ gain based on link training; DP mode AEQ(Lx) = 0dB at 2.7GHz AEQ(Lx) I2C programmable VIL 0 (1) (2) AEQ(Lx) = 6dB at 2.7GHz LINK TRAINING AEQ(Lx) (2) LANE 3 3dB at 1.35GHz DP mode; EQ fully programmable for each training level; EQ disabled by default DP mode; EQ fully programmable by AEQ(L1) levels; default AEQ(L1) EQ setting at 6dB At 2.7GHz TMDS mode; fixed EQ Setting CAD_TEST_MODE (Reg 17.0) forces the SN75DP130 into a TMDS test mode even if no external CAD signal is present EQ setting is adjusted based on the output pre-emphasis level setting; the EQ setting is indifferent to the level of VOD. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): SN75DP130 SN75DP130 SLLSE57 – APRIL 2011 www.ti.com LINK TRAINING AND DPCD DESCRIPTION The SN75DP130 monitors the auxiliary interface access to DisplayPort Configuration Data (DPCD) registers during Link Training in DP mode to select the output voltage swing VOD, output pre-emphasis, and the EQ setting of the Main Link. The AUX monitor for SN75DP130 supports Link Training in 1Mbps Manchester mode, and is disabled during TMDS mode (CAD_SNK=VIH). The AUX channel is further monitored for the DisplayPort D3 standby command. The DPCD registers monitored by SN75DP130 are listed in Table 6. Bit fields not listed are reserved and values written to reserved fields are ignored. Table 6. DPCD Registers Utilized by the SN75DP130 AUX Monitor ADDRESS 00100h 00101h 00103h NAME LINK_BW_SET LANE_COUNT_SET TRAINING_LANE0_SET DESCRIPTION Bits 7:0 = Link Bandwidth Setting 06h – 1.62Gbps per lane 0Ah – 2.7Gbps per lane (default) 14h – (or any other value) 5.4Gbps per lane Bits 4:0 = Lane Count 0h – All lanes disabled (default) 1h – One lane enabled 2h – Two lanes enabled 4h – Four lanes enabled Note: any other value is invalid and disables all Main Link output lanes Bits 1:0 = Output Voltage VOD Level 00 – Voltage swing level 0 (default) 01 – Voltage swing level 1 10 – Voltage swing level 2 11 – Voltage swing level 3 Bits 4:3 = Pre-emphasis Level 00 – Pre-emphasis level 0 (default) 01 – Pre-emphasis level 1 10 – Pre-emphasis level 2 11 – Pre-emphasis level 3 Note: the following combinations are not allowed for bits [1:0]/[4:3]: 01/11, 10/10, 10/11, 11/01, 11/10, 11/11; setting to any of these invalid combinations disables all Main Link lanes until the register value is changed back to a valid entry 00104h TRAINING_LANE1_SET Sets the VOD and pre-emphasis levels for lane 1 00105h TRAINING_LANE2_SET Sets the VOD and pre-emphasis levels for lane 2 00106h TRAINING_LANE3_SET Sets the VOD and pre-emphasis levels for lane 3 0010F 0110F TRAINING_LANE0_1_SET2 TRAINING_LANE2_3_SET2 Bits 1:0 = Lane 0 Post Cursor 2 00 – IN0 expects post cursor2 level 01 – IN0 expects post cursor2 level 10 – IN0 expects post cursor2 level 11 – IN0 expects post cursor2 level Bits 5:4 = Lane 1 Post Cursor 2 00 – IN1 expects post cursor2 level 01 – IN1 expects post cursor2 level 10 – IN1 expects post cursor2 level 11 – IN1 expects post cursor2 level 0; OUT0 1; OUT0 2; OUT0 3; OUT0 transmits at post cursor 2 level 0 remains at post cursor 2 level 0 remains at post cursor 2 level 0 remains at post cursor 2 level 0 0; OUT1 1; OUT1 2; OUT1 3; OUT1 transmits at post cursor 2 level 0 remains at post cursor 2 level 0 remains at post cursor 2 level 0 remains at post cursor 2 level 0 Bit definition identical to that of TRAINING_LANE_0_1_SET2 but for lanes 2 (IN2/OUT2) and lane 3 (IN3/OUT3) Bits 1:0 = Power Mode 01 – Normal mode (default) 10 – Power down mode; D3 Standby Mode 00600h SET_POWER The Main Link and all analog circuits are shut down and the AUX channel is monitored during the D3 Standby Mode. The device exits D3 Standby Mode by access to this register, when CAD_SNK goes high, or if HPD_SNK goes low for longer than tT(HPD), which indicates that the DP sink was disconnected. Note: setting the register to the invalid combination 0600h[1:0]=00 or 11 is ignored by the device and the device remains in normal mode Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): SN75DP130 21 SN75DP130 SLLSE57 – APRIL 2011 www.ti.com I2C INTERFACE OVERVIEW The SN75DP130 I2C interface is enabled when EN and RSTN are input high. The SCL_CTL and SDA_CTL terminals are used for I2C clock and I2C data respectively. The SN75DP130 I2C interface conforms to the two-wire serial interface defined by the I2C Bus Specification, Version 2.1 (January 2000), and supports the standard mode transfer up to 100 kbps. The device address byte is the first byte received following the START condition from the master device. The 7 bit device address for SN75DP130 is factory preset to 01011xx with the two least significant bits being determined by the ADDR_EQ 3-level control input. Table 7 clarifies the SN75DP130 target address. Table 7. SN75DP130 I2C Target Address Description BIT 7 (MSB) 0 BIT 6 1 Note: ADDR_EQ = LOW: ADDR_EQ = VCC/2: ADDR_EQ = HIGH: SN75DP130 I2C TARGET ADDRESS BIT 5 BIT 4 BIT 3 0 1 1 BIT 2 ADDR1 BIT 1 ADDR0 BIT 0 (W/R) 0/1 ADDR[1:0] = 00: W/R=58/59 ADDR[1:0] = 01: W/R=5A/5B; ADDR[1:0] = 10: W/R=5C/5D The following procedure is followed to write to the SN75DP130 I2C registers: 1. The master initiates a write operation by generating a start condition (S), followed by the SN75DP130 7-bit address and a zero-value "W/R" bit to indicate a write cycle 2. The SN75DP130 acknowledges the address cycle 3. The master presents the sub-address (I2C register within SN75DP130) to be written, consisting of one byte of data, MSB-first 4. The SN75DP130 acknowledges the sub-address cycle 5. The master presents the first byte of data to be written to the I2C register 6. The SN75DP130 acknowledges the byte transfer 7. The master may continue presenting additional bytes of data to be written, with each byte transfer completing with an acknowledge from the SN75DP130 8. The master terminates the write operation by generating a stop condition (P) The following procedure is followed to read the SN75DP130 I2C registers: 1. The master initiates a read operation by generating a start condition (S), followed by the SN75DP130 7-bit address and a one-value "W/R" bit to indicate a read cycle 2. The SN75DP130 acknowledges the address cycle 3. The SN75DP130 transmit the contents of the memory registers MSB-first starting at register 00h. 4. The SN75DP130 will wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master after each byte transfer; the I2C master acknowledges reception of each data byte transfer 5. If an ACK is received, the SN75DP130 transmits the next byte of data 6. The master terminates the read operation by generating a stop condition (P) Note that no sub-addressing is included for the read procedure, and reads start at register offset 00h and continue byte by byte through the registers until the I2C master terminates the read operation. Refer to Table 8 for SN75DP130 local I2C register descriptions. Reads from reserved fields not described return zeros, and writes are ignored. Table 8. SN75DP130 I2C Register Descriptions ADDRESS BIT(S) 1 AUTO_POWERDOWN_DISABLE 0 – The SN75DP130 automatically enters Standby mode based on HPD_SNK (default) 1 – The SN75DP130 will not automatically enter Standby mode RW 0 FORCE_SHUTDOWN_MODE 0 – SN75DP130 is forced to Shutdown mode 1 – Shutdown mode is determined by EN input, normal operation (default) RW 01h (1) 22 ACCESS (1) DESCRIPTION RO = Read Only; RW = Read/Write; WO = Write Only (reads return undetermined values) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): SN75DP130 SN75DP130 SLLSE57 – APRIL 2011 www.ti.com Table 8. SN75DP130 I2C Register Descriptions (continued) ACCESS (1) ADDRESS BIT(S) 02h 7:0 TI_TEST. This field defaults to zero value, and should not be modified. RW 5:4 SQUELCH_SENSITIVITY. Main Link squelch sensitivity is selected by this field, and determines the transitions to and from the Output Disable mode. 00 – Main Link IN0p/n squelch detection threshold set to 40mVpp 01 – Main Link IN0p/n squelch detection threshold set to 80mVpp (default) 10 – Main Link IN0p/n squelch detection threshold set to 160mVpp 11 – Main Link IN0p/n squelch detection threshold set to 250mVpp RW 3 SQUELCH_ENABLE 0 – Main Link IN0p/n squelch detection enabled (default) 1 – Main Link IN0p/n squelch detection disabled RW 3 TI_TEST. This field defaults to zero value, and should not be modified. RW RW 2 LINK_TRAINING_ENABLE 0 – Link Training is disabled. VOD and Pre-emphasis are configured through the I2C register interface; the EQ is fixed when this bit is zero. 1 – Link Training is enabled (default) 03h 04h 1:0 7 6:4 07h 08h 09h 0Ah 0Bh 0Ch AUX_DDC_MUX_CFG. See Table 3 for details on the programming of this field. 00 – AUX_SNK is switched to AUX_SRC for DDC source side based on CAD_SNK (default) 01 – AUX_SNK is switched to AUX_SRC based on the CAD_SNK input, and used to short circuit AC coupling capacitors in the TMDS operating mode. 10 – AUX_SNK is switched to AUX_SRC side based on the HPD_SNK inptu, while the DDC source interface remains disabled. 11 – Undefined operation RW EQ_I2C_ENABLE 0 – EQ settings controlled by device inputs only (default) 1 – EQ settings controlled by I2C register settings RW AEQ_L0_LANE0_SET. This field selects the EQ setting for Lane 0 when I2C_EQ_ENABLE is set, Link Training is enabled, and the Link Training results in Level 0 pre-emphasis. 05h 06h DESCRIPTION 000 – 0dB EQ gain (default) 001 – 1.5dB (HBR); 3.5dB (HBR2) 010 – 3dB (HBR); 6dB (HBR2) 011 – 4dB (HBR); 8dB (HBR2) 100 – 5dB (HBR); 101 – 6dB (HBR); 110 – 7dB (HBR); 111 – 9dB (HBR); 10dB 13dB 15dB 18dB (HBR2) (HBR2) (HBR2) (HBR2) RW 2:0 AEQ_L1_LANE0_SET. Settings are the same as AEQ_L0_LANE0_SET RW 6:4 AEQ_L2_LANE0_SET. Settings are the same as AEQ_L0_LANE0_SET RW 2:0 AEQ_L3_LANE0_SET. Settings are the same as AEQ_L0_LANE0_SET RW 6:4 AEQ_L0_LANE1_SET. Settings are the same as AEQ_L0_LANE0_SET RW 2:0 AEQ_L1_LANE1_SET. Settings are the same as AEQ_L0_LANE0_SET RW 6:4 AEQ_L2_LANE1_SET. Settings are the same as AEQ_L0_LANE0_SET RW 2:0 AEQ_L3_LANE1_SET. Settings are the same as AEQ_L0_LANE0_SET RW 6:4 AEQ_L0_LANE2_SET. Settings are the same as AEQ_L0_LANE0_SET RW 2:0 AEQ_L1_LANE2_SET. Settings are the same as AEQ_L0_LANE0_SET RW 6:4 AEQ_L2_LANE2_SET. Settings are the same as AEQ_L0_LANE0_SET RW 2:0 AEQ_L3_LANE2_SET. Settings are the same as AEQ_L0_LANE0_SET RW 6:4 AEQ_L0_LANE3_SET. Settings are the same as AEQ_L0_LANE0_SET RW 2:0 AEQ_L1_LANE3_SET. Settings are the same as AEQ_L0_LANE0_SET RW 6:4 AEQ_L2_LANE3_SET. Settings are the same as AEQ_L0_LANE0_SET RW 2:0 AEQ_L3_LANE3_SET. Settings are the same as AEQ_L0_LANE0_SET RW Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): SN75DP130 23 SN75DP130 SLLSE57 – APRIL 2011 www.ti.com Table 8. SN75DP130 I2C Register Descriptions (continued) ADDRESS BIT(S) DESCRIPTION ACCESS (1) 4:3 BOOST. Controls the output pre-emphasis amplitude; allows to reduce or increase all pre-emphasis settings by ~10%. Setting this field will impact VOD when pre-emphasis is disabled. This setting also impacts the output in TMDS mode. 00 – Pre-emphasis reduced by ~10%; VOD reduced when pre-emphasis is disabled. 01 – Pre-emphasis nominal (default) 10 – Pre-emphasis increased by ~10%; VOD increased when pre-emphasis is disabled. 11 – Reserved RW TMDS_VOD. Sets the target output swing in TMDS mode. 0 – Low TMDS output swing (default) 1 – High TMDS output swing RW TMDS_VPRE. Controls the output pre-emphasis in TMDS mode 00 – No TMDS pre-emphasis (default) 01 – Low TMDS pre-emphasis 10 – High TMDS pre-emphasis 11 – Reserved RW 3 HPD_TEST_MODE 0 – Normal HPD mode. HPD_SRC reflects the status of HPD_SNK (default) 1 – Test mode. HPD_SNK is pulled high internally, and the HPD_SRC output is driven high and the Main Link is activated, depending on the squelch setting. This mode allows execution of certain tests on SN75DP130 without a connected display sink. RW 1 CAD_OUTPUT_INVERT 0 – CAD_SRC output high means TMDS cable adapter detected (default) 1 – CAD_SRC output low means TMDS cable adapter detected RW 15h 2 1:0 17h CAD_TEST_MODE 17h 0 0 – Normal CAD mode. CAD_SRC reflects the status of CAD_SNK, based on the value of CAD_OUTPUT_INVERT (default) RW 1 – Test mode. CAD_SRC indicates TMDS mode, depending on the value of CAD_OUTPUT_INVERT; CAD_SNK input is ignored. This mode allows execution of certain tests on SN75DP130 without a connected TMDS display sink. 18h – 1Ah 7:0 TI_TEST. These registers shall not be modified. RW 2 7 I2C_SOFT_RESET. Writing a one to this register resets all I C registers to default values. Writing a zero to this register has no effect. Reads from this register return zero. 6 DPCD_RESET. Writing a one to this register resets the DPCD register bits (corresponding to DPCD addresses 103h – 106h, the AEQ_Lx_LANEy_SET bits). Writing a zero to this register has no effect. Reads from this register return zero. 1Bh 1Ch 3:0 DPCD_ADDR_HIGH. This value maps to bits 19:16 of the 20-bit DPCD register address accessed through the DPCD_DATA register. RW 1Dh 7:0 DPCD_ADDR_MID. This value maps to bits 15:8 of the 20-bit DPCD register address accessed through the DPCD_DATA register. RW 1Eh 7:0 DPCD_ADDR_LOW. This value maps to bits 7:0 of the 20-bit DPCD register address accessed through the DPCD_DATA register. RW 1Fh 7:0 DPCD_DATA. This register contains the data to write into or read from the DPCD register addressed by DPCD_ADDR_HIGH, DPCD_ADDR_MID, and DPCD_ADDR_LOW. RW 7:1 DEV_ID_REV. This field identifies the device and revision. 0000000 – SN75DP130 Revision 0 RO BIT_INVERT. The value read from this field is the inverse of that written. Default read value is zero. RW 20h 0 24 WO 21h 7:0 TI_TEST. These registers shall not be modified. RW 22h – 27h 7:0 TI_TEST_RESERVED. These read only registers are reserved for test; writes are ignored. RO Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): SN75DP130 PACKAGE OPTION ADDENDUM www.ti.com 20-May-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) SN75DP130DSRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR SN75DP130DSRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR SN75DP130SSRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR SN75DP130SSRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 18-May-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SN75DP130DSRGZR VQFN RGZ 48 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 SN75DP130DSRGZT VQFN RGZ 48 250 180.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 SN75DP130SSRGZR VQFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 SN75DP130SSRGZT VQFN RGZ 48 250 180.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 18-May-2011 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN75DP130DSRGZR VQFN RGZ 48 2500 346.0 346.0 33.0 SN75DP130DSRGZT VQFN RGZ 48 250 190.5 212.7 31.8 SN75DP130SSRGZR VQFN RGZ 48 2500 346.0 346.0 33.0 SN75DP130SSRGZT VQFN RGZ 48 250 190.5 212.7 31.8 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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