TI TPD12S015YFFR

TPD12S015
www.ti.com
SLLSE19A – DECEMBER 2009 – REVISED JANUARY 2010
2
HDMI COMPANION CHIP WITH STEP-UP DC-DC, I C LEVEL SHIFTER, AND HIGH-SPEED
ESD CLAMPS FOR PORTABLE APPLICATIONS
Check for Samples: TPD12S015
FEATURES
1
•
•
•
•
•
•
•
HDMI 1.3 Data Rate
HDMI High-Speed Differential Signals -3 dB
Bandwidth Exceeds 6.4 Gbps
Excellent Matching Capacitance (0.05 pF) in
Each Differential Signal Pair
Internal Boost Converter to Generate 5 V from
a 2.3- to 5.5-V Battery Voltage
Directionless Level Shifting in the CEC, SDA,
SCL, and HPD Paths
Seamless Type C Connector Routing with
Flow-Through Pin Mapping
IEC 61000-4-2 (Level 4) System Level ESD
Compliance
Very Low Leakage into High-Speed Signal
Lines During Powerdown
Industrial Temperature Range: –40°C to 85°C
•
•
APPLICATIONS
•
•
•
•
•
Smart Phones
Multimedia Phones
Digital Camcorders
Digital Still Cameras
Portable Game Consoles
YFF PACKAGE
(TOP VIEW)
1
2
3
YFF PACKAGE PIN MAPPING
4
A
1
2
3
4
LS_OE
VCCA
D2+
D2–
D1+
A
B
SCL_A
CEC_A
GND
B
C
SDA_A
HPD_A
GND
D1–
D
CT_CP_HPD
GND
CEC_B
D0+
C
E
FB
GND
SCL_B
D0–
D
F
5VOUT
SW
SDA_B
CLK+
E
G
PGND
VBAT
HPD_B
CLK–
F
G
For package dimensions, see the
Mechanical Drawing at the end of this
document.
DESCRIPTION/ORDERING INFORMATION
The TPD12S015 is an integrated HDMI ESD solution. The device pin mapping matches the HDMI Type C
connector with four differential pairs. This device offers eight low-capacitance ESD clamps, allowing HDMI 1.3
data rates. The integrated ESD clamps and resistors provide good matching between each differential signal
pair, which allows an advantage over discrete ESD clamp solutions where variations between ESD clamps
degrade the differential signal quality.
The TPD12S015 provides a regulated 5 V output (5VOUT) for sourcing the HDMI power line. The regulated 5 V
output supplies up to 55 mA to the HDMI receiver. The control of 5VOUT and the hot plug detect (HPD) circuitry
is independent of the LS_OE control signal and is controlled by the CT_CP_HPD pin. This independent control
enables the detection scheme (5VOUT + HPD) to be active before enabling the HDMI link.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2010, Texas Instruments Incorporated
TPD12S015
SLLSE19A – DECEMBER 2009 – REVISED JANUARY 2010
www.ti.com
There are three non-inverting bi-directional translation circuits for the SDA, SCL, and CEC lines. Each have a
common power rail (VCCA) on the A side from 1.1 V to 3.6V . On the B side, the SCL_B and SDA_B each have
an internal 1.75 kΩ pullup connected to the regulated 5 V rail (5VOUT). The SCL and SDA pins meet the I2C
specification and drive up to 750 pF loads. The CEC_B pin has an internal 27 kΩ pullup to an internal 3.3 V
supply.
The HPD_B port has a glitch filter to avoid false detection due to the bouncing while inserting the HDMI plug.
The TPD12S015 provides IEC61000-4-2 (Level 4) ESD protection. This device is offered in a space-saving 1.6
mm × 2.8 mm wafer-level chip scale package [WCSP (YFF)] with 0.4-mm pitch.
ORDERING INFORMATION
TA
PACKAGE
–40°C to 85°C
(1)
(2)
(3)
WCSP – YFF
(1) (2)
ORDERABLE PART NUMBER
Tape and reel
TOP-SIDE MARKING
TPD12S015YFFR
PN015
TPD12S015YFFRB (3)
PN015
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
The TPD12S015YFFRB is the YFF package with back-side coating.
SYSTEM-LEVEL BLOCK DIAGRAM
Battery
HDMI-TPD12S015-Configuration A
vbat
TPD12S015
O
VBAT
Power Supplies
VBAT
I
SW
I
LHDMI-VBAT
1 µH
HDMI Connector
Connecto
+5V
I
FB
O
5VOUT(+5v)
VCCA
P
PMIC
VBAT
CHDMI-VBAT
2.2µF
5V DC-DC
Regulator
VCCA
I
O
V1V8
CHDMI-VCCA
0.1µF
GND
A
CT_CP_HPD
I
CT_CP_HPD
LS_OE
I
LS_OE
3.3V LDO
CHDMI-5v
4.7 µH
Vdac_out
Control Lines
HDMI Sink side
O
uC
HDMI Source side
HDMI Sideband
P
vdds_1p8
O
GPIO_HDMICT_CP_HPD
O
GPIO_HDMI-LS_OE
SCL
IO
IO
SCL_B
SCL_A
IO
DDC-SC
IO
hdmi_scl
SDA
IO
IO
SDA_B
SDA_A
IO
DDC-SDA
IO
hdmi_sda
CEC
IO
IO
CEC_B
CEC_A
IO
CEC
IO
hdmi_cec
HPD
O
I
HPD_B
HPD_A
O
HPD
I
hdmi_hpd
CLK-
I
CLK-
O
hdmi_clkm
CLk+
I
CLK+
O
hdmi_clkp
DATA 0-
I
DATA0-
O
hdmi_data0m
DATA 0+
I
DATA0+
O
hdmi_data0p
DATA 1-
I
DATA1-
O
hdmi_data1m
DATA 1+
I
DATA1+
O
hdmi_data1p
DATA 2-
I
DATA2-
O
hdmi_data2m
DATA 2+
I
DATA2+
O
hdmi_data2p
HDMI PHY
I
I
I
I
I
I
I
vdda_hdmi_vdac
P
vssa_hdmi_vdac
GND
I
+5V
K
L
C
+
K
L
C
0
D
+
0
D
1
D
+
1
D
2
D
+
2
D
TMDS signal
2
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TPD12S015
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SLLSE19A – DECEMBER 2009 – REVISED JANUARY 2010
CIRCUIT BLOCK DIAGRAM
VBAT
FB (IEC)
SW
CT_CP_HPD
5VOUT (IEC)
5V
DC/DC
470k
PGND
D0+, D0D1+, D1D2+, D2CLK+, CLK8
(IEC) HDMI
ESD Clamp
(x8)
LS_OE_INTERNAL
5VOUT
VCCA
3.3V
(Internal )
LDO
470k
HPD_B (IEC)
11k
LS_OE
VCCA
HPD_A
CT_CP_HPD VCCA
3.3V (Internal)
10k
26k±15%
CEC_B (IEC)
CEC_A
5VOUT
VCCA
1.75k
10k
ERC
SCL_B (IEC)
SCL_A
5VOUT
VCCA
1.75k
10k
ERC
SDA_B (IEC)
SDA_A
LS_OE_INTERNAL
PGND
PGND
GND
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TPD12S015
SLLSE19A – DECEMBER 2009 – REVISED JANUARY 2010
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TERMINAL FUNCTIONS
TERMINAL
4
TYPE
DESCRIPTION
F1
Pwr O
DC/DC output. The 5-V power pin can supply 55 mA regulated current to the HDMI
receiver. Separate DC/DC converter control pin CT_CP_HPD disables the DC/DC
converter when operating at low-power mode.
CEC_A
B2
I/O
System-side CEC bus I/O. This pin is bi-directional and referenced to VCCA.
CEC_B
D3
I/O
HDMI-side CEC bus I/O. This pin is bi-directional and referenced to the 3.3-V internal
supply.
CLK–, CLK+
G4, F4
ESD
High-speed ESD clamp: provides ESD protection to the high-speed HDMI differential
data lines
CT_CP_HPD
D1
Ctrl
DC/DC Enable. Enables the DC/DC converter and HPD circuitry when CT_CP_HPD =
H. The CT_CP_HPD is referenced to VCCA.
D0–, D0+,
D1– , D1+,
D2–, D2+
E4, D4,
C4, B4,
A4, A3
ESD
High-speed ESD clamp: provides ESD protection to the high-speed HDMI differential
data lines
FB
E1
I
Feedback input. This pin is a feedback control pin for the DC/DC converter. It must be
connected to 5VOUT.
GND
B3, C3,
D2, E2
–
Device ground
HPD_A
C2
O
System-side output for the hot plug detect. This pin is unidirectional and is referenced to
VCCA.
HPD_B
G3
I
HDMI-side input for the hot plug detect. This pin is unidirectional and is referenced to
5VOUT.
LS_OE
A1
Ctrl
PGND
G1
–
DC/DC converter ground. This pin should be tied externally to the system GND plane.
See board layout in applications section.
SCL_A
B1
I/O
System-side input/output for I2C bus. This pin is bi-directional and referenced to VCCA.
SCL_B
E3
I/O
HDMI-side input/output for I2C bus. This pin is bi-directional and referenced to 5VOUT.
SDA_A
C1
I/O
System-side input/output for I2C bus. This pin is bi-directional and referenced to VCCA.
SDA_B
F3
I/O
HDMI-side input/output for I2C bus. This pin is bi-directional and referenced to 5VOUT.
SW
F2
I
VBAT
G2
Supply
Battery supply. This voltage is typically 2.3 V to 5.5 V
VCCA
A2
Supply
System-side supply. this voltage is typically 1.2 V to 3.3 V from the core microcontroller.
NAME
NO.
5VOUT
Level shifter enable. This pin is referenced to VCCA. Enables level shifters and LDO
when OE = H.
Switch input. This pin is the inductor input for the DC/DC converter.
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SLLSE19A – DECEMBER 2009 – REVISED JANUARY 2010
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
MIN
VCCA
Supply voltage range
VBAT
Supply voltage range
VI
Input voltage range
Voltage range applied to any output in the
high-impedance or power-off state (2)
VO
V
6.5
SCL_A, SDA_A, CEC_A , CT_CP_HPD,
LS_OE
–0.3
4.0
SCL_B, SDA_B, CEC_B, D, CLK
–0.3
6.0
SCL_A, SDA_A, CEC_A, HPD_A
–0.3
4.0
SCL_B, SDA_B, CEC_B
–0.3
6.0
–0.3
VCCA + 0.3
Voltage range applied to any output in the high or SCL_A, SDA_A, CEC_A, HPD_A
low state (2)
SCL_B, SDA_B, CEC_B
Input clamp current
VI < 0
IOK
Output clamp current
VO < 0
IOUTMAX
Continuous current through 5VOUT or GND
Tstg
Storage temperature range
(2)
UNIT
4.0
–0.3
IIK
(1)
MAX
–0.5
–65
V
V
6.0
–50
mA
–50
mA
±100
mA
150
°C
Stresses above these ratings may cause permanent damage. Exposure to "absolute maximum conditions" for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
over recommended operating free-air temperature range (unless otherwise noted)
SUPPLY
VCCA
Supply voltage
VBAT
Supply voltage
VIH
MAX
UNIT
1.1
3.6
V
2.3
5.5
V
0.7*VCCA
VCCA
1
VCCA
0.7*5VOUT
5VOUT
0.7*3.3V
(internal)
3.3V
(internal)
2.4
5VOUT
–0.5
0.082*VCCA
CT_CP_HPD, LS_OE
–0.5
0.4
SCL_B, SDA_B
–0.5
0.3*5VOUT
–0.5
0.3*V3P3
0
0.8
–0.5
0.065*VCCA
SCL_A, SDA_A,
CEC_A
VCCA = 1.1 V to 3.6 V
CT_CP_HPD, LS_OE
High-level input voltage
SCL_B, SDA_B
CEC_B
5VOUT = 5.0 V
HPD_B
VIL
SCL_A, SDA_A,
CEC_A
Low-level input voltage
CEC_B
VCCA = 1.1 V to 3.6 V
5VOUT = 5.0 V
HPD_B
VILC
Low-level input voltage
(contention)
SCL_A, SDA_A,
CEC_A
VCCA = 1.1 V to 3.6 V
VOL –
VILC
Delta between VOL and VILC
SCL_A, SDA_A,
CEC_A
VCCA = 1.1 V to 3.6 V
TA
Operating free-air temperature
MIN
TYP
0.1*VCC
V
V
85
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V
A
–40
Copyright © 2009–2010, Texas Instruments Incorporated
V
°C
5
TPD12S015
SLLSE19A – DECEMBER 2009 – REVISED JANUARY 2010
www.ti.com
ESD RATINGS
PARAMETER
PINS
TYP
UNIT
kV
Human Body Model JESD22 A114-B
ALL
2.5
Charged Device Model JESD22 C101
ALL
1000
V
IEC 61000-4-2 Contact Discharge
Dx, CLKx, x_B, 5VOUT, FB
±8
kV
Human Body Model
Dx, CLKx, x_B, 5VOUT, FB
±15
kV
ELECTRICAL CHARACTERISTICS
ICC
PARAMETER
ICCA
Standby
PIN
TEST CONDITIONS
VCCA
MIN
TYP
I/O = High
Active
ICCB
MAX
UNIT
2
µA
15
Standby
VBAT
CT_CP_HPD=L, LS_OE=L, HPD_B=L
2
µA
DC/DC and HPD active
CT_CP_HPD=H, LS_OE=L, HPD_B=L
30
50
DC/DC, HPD, DDC, CEC active
CT_CP_HPD=H LS_OE=H, HPD_B=L,
I/O =H
225
300
High-Speed ESD Lines: Dx, CLK
TYP
MAX
UNIT
IOFF
Current from IO port to supply
pins
PARAMETER
VCC = 0 V, VIO = 3.3 V
TEST CONDITIONS
MIN
0.01
0.5
µA
VDL
Diode forward voltage
ID = 8 mA,
Lower clamp diode
0.85
1.0
RDYN
Dynamic resistance
I=1A
D, CLK
CIO
IO capacitance
VIO = 2.5 V
D, CLK
VBR
Break-down voltage
IIO = 1mA
1.3
9
V
Ω
1
pF
12
V
MAX
UNIT
5.5
V
DC-DC Converter
PARAMETER
TEST CONDITIONS
MIN
TYP
VBAT
Input voltage range
2.3
5VOUT
Total DC output voltage
Includes voltage references, DC load / line
regulations, process and temperature
4.9
5
5.13
V
TOVA
Total output voltage accuracy
Includes voltage references, DC load / line
regulations, transient load / line regulations,
ripple, process and temperature
4.8
5
5.3
V
VO_Ripple
Output voltage ripple, loaded
IO = 65 mA
20
mV
(p-p)
F_clk
Internal operating frequency
VBAT = 2.3 V to 5.5 V
tstart
Startup time
From CT_CP_HPD input to 5 V power output
90% point
IO
Output current
VBAT = 2.3 V to 5.5 V
Reverse leakage current VO
CT_CP_HPD= L, VO = 5.5 V
Leakage current from battery to
VO
CT_CP_HPD= L
VBATUV
Under voltage lockout threshold Falling
VOVC
Input overvoltage threshold
6
3.5
MHz
300
55
µs
mA
2.5
µA
5
µA
2
V
Rising
2.1
V
Falling
5.9
V
Rising
6.0
Line transient response
VBAT = 3.6 V, a pulse of 217Hz 600 mVp-p
square wave, IO = 20/65 mA
±25
Load transient response
VBAT = 3.6 V, IO = 5 to 65 mA, pulse of 10 µs, tr
= tf = 0.1 µs
50
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mVpk
mVpk
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SLLSE19A – DECEMBER 2009 – REVISED JANUARY 2010
DC-DC Converter (continued)
PARAMETER
TEST CONDITIONS
TYP
MAX
UNIT
30
50
µA
VBAT = 2.3 V to 5.5 V, IO = 0 mA, CT_CP_HPD
Low
2
µA
IDD(system off) Power supply current from
VBAT, VCCA =0V
VCCA = 0 V
5
µA
I_inrush
(startup)
Inrush current, average over
T_startup time
VBAT = 2.3 V to 5.5 V, IO = 65 mA
100
mA
TSD
Thermal shutdown
Increasing junction temperature
140
°C
Thermal shutdown hysteresis
Decreasing junction temperature
20
Short circuit current limit from
output
5Ω short to GND
IDD (idle)
Power supply current from VBAT IO = 0 mA
to DC/DC, enabled, unloaded
IDD (disabled)
Power supply current from
VBAT, DC/DC Disabled,
Unloaded
ISC
MIN
°C
500
mA
Passive Components
PARAMETER
TYP
UNIT
1
µH
Input capacitor, 0603 footprint
4.7
µF
Output capacitor, 0603 footprint
4.7
µF
Input capacitor, 0402 footprint
0.1
µF
LIN
External inductor, 0805 footprint
CIN
COUT
CVCCA
Voltage Level Shifter: SCL, SDA Lines (x_A/x_B Ports)
TA = –40°C to 85°C unless otherwise specified
VCCA
MIN
VOHA
PARAMETER
IOH = –20 mA, VI = VIH
TEST CONDITIONS
1.1 V to 3.6 V
VCCA × 0.8
VOLA
IOL = 20 mA,
1.1 V to 3.6 V
VOHB
IOH = –20 mA, VI = VIH
VOLB
IOL = 3 mA,
VI = VIL
TYP
UNIT
V
VCCA × 0.17
V
5VOUT × 0.9
V
VI = VIL
0.4
ΔVT
hysteresi
s
SDx_A (VT+ – VT–)
1.1 V to 3.6 V
40
SDx_B (VT+ – VT–)
1.1 V to 3.6 V
400
RPU
(Internal pullup)
SCL_A,
SDA_A,
Internal pullup connected to
VCCA rail
10
SCL_B,
SDA_B,
Internal pullup connected to
5 V rail
1.75
IPULLUPAC Transient boosted
pullup current (rise
time accelerator)
SCL_B,
SDA_B,
Internal pullup connected to
5 V rail
15
IOFF
A port
VCCA = 0 V, VI or VO = 0 to 3.6 V
B port
5VOUT = 0 V, VI or VO = 0 to 5.5 V
B port
A port
IOZ
MAX
V
mV
kΩ
mA
0V
±5
0 V to 3.6 V
±5
VO = VCCO or GND
1.1 V to 3.6 V
±5
VI = VCCI or GND
1.1 V to 3.6 V
±5
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mA
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Voltage Level Shifter: CEC Lines (x_A/x_B Ports)
TA = –40°C to 85°C unless otherwise specified
VCCA
MIN
VOHA
PARAMETER
IOH = –20
mA,
TEST CONDITIONS
VI = VIH
1.1 V to 3.6 V
VCCA × 0.8
VOLA
IOL = 20
mA,
VI = VIL
1.1 V to 3.6 V
VOHB
IOH = –20
mA,
VI = VIH
VOLB
IOL = 3 mA,
VI = VIL
TYP
VCCA × 0.17
V
0.4
1.1 V to 3.6 V
40
CEC_B (VT+ – VT–)
1.1 V to 3.6 V
300
RPU
(Internal pullup)
IOZ
CEC_A
Internal pullup connected to
VCCA rail
10
CEC_B
Internal pullup connected to
internal 3.3 V rail
26
VCCA = 0 V, VI or VO = 0 to 3.6 V
B port
5VOUT = 0 V, VI or VO = 0 to 5.5 V
B port
A port
V
V3P3 × 0.9
CEC_A (VT+ – VT–)
A port
UNIT
V
ΔVT
hysteresi
s
IOFF
MAX
V
mV
kΩ
0V
±5
0 V to 3.6 V
±1.8
VO = VCCO or GND
1.1 V to 3.6 V
±5
VI = VCCI or GND
1.1 V to 3.6 V
±5
mA
mA
Voltage Level Shifter: HPD Line (x_A/x_B Ports)
TA = –40°C to 85°C unless otherwise specified
VCCA
MIN
VOHA
PARAMETER
IOH = –3
mA,
TEST CONDITIONS
VI = VIH
1.1 V to 3.6 V
VCCA × 0.7
VOLA
IOL = 3
mA,
VI = VIL
1.1 V to 3.6 V
VCCA ×0.17
1.1 V to 3.6 V
700
ΔVT
HPD_B (VT+ – VT–)
hysteresi
s
TYP
MAX
UNIT
V
V
mV
RPD
(Internal pulldown)
HPD_B,
Internal pulldown connected
to GND
IOFF
A port
VO = VCCO or GND
IOZ
A port
VI = VCCI or GND
11
kΩ
0V
±5
mA
3.6 V
±5
mA
LS_OE, CT_CP_HPD
TA = –40°C to 85°C unless otherwise specified
PARAMETER
II
TEST CONDITIONS
VI = VCCA or GND
VCCA
MIN
TYP
1.1 V to 3.6 V
MAX
UNIT
±12
mA
I/O Capacitance
TA = –40°C to 85°C unless otherwise specified
TYP
MAX
UNIT
CI
PARAMETER
Control inputs
VI = 1.89 V or GND
1.1 V to 3.6 V
7.1
8.5
pF
CIO
A port
VO = 1.89 V or GND
1.1 V to 3.6 V
8.3
9.5
pF
B port
VO = 5.0 V or GND
1.1 V to 3.6 V
15
16.5
pF
8
TEST CONDITIONS
VCCA
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SLLSE19A – DECEMBER 2009 – REVISED JANUARY 2010
SWITCHING CHARACTERISTICS
PARAMETER
CL
MAX
UNIT
Bus load capacitance (B side)
TEST CONDITIONS
MIN
TYP
750
pF
Bus load capacitance (A side)
15
Voltage Level Shifter: SCL, SDA Lines (x_A & x_B ports); VCCA = 1.2V
VCCA = 1.2 V
tPHL
PARAMETER
PINS
TEST CONDITIONS
Propagation delay
A to B
DDC Channels Enabled
MIN
Propagation delay
A to B
DDC Channels Enabled
tr
fMAX
A port fall time
A Port
B port fall time
B Port
452
A port rise time
A Port
B port rise time
B Port
Maximum switching frequency
ns
178
DDC Channels Enabled
138
ns
83
DDC Channels Enabled
194
ns
92
DDC Channels Enabled
UNIT
ns
335
B to A
tf
MAX
344
B to A
tPLH
TYP
400
kHz
Voltage Level Shifter: CEC Line (x_A & x_B ports); VCCA = 1.2V
VCCA = 1.2 V
tPLH
PARAMETER
PINS
TEST CONDITIONS
Propagation delay
A to B
CEC Channels Enabled
MIN
tf
tr
13
B to A
0.266
A Port
B port fall time
B Port
A port rise time
A Port
B port rise time
B Port
CEC Channels Enabled
ms
140
ns
96
CEC Channels Enabled
UNIT
ns
337
A to B
A port fall time
MAX
445
B to A
tPLH
TYP
202
ns
15
ms
Voltage Level Shifter: HPD Line (x_A & x_B ports); VCCA = 1.2V
VCCA = 1.2 V
tPLH
PARAMETER
PINS
TEST CONDITIONS
Propagation delay
B to A
CEC Channels Enabled
tPLH
MIN
TYP
MAX
10
B to A
UNIT
ms
9
tf
A port fall time
A Port
CEC Channels Enabled
0.67
ns
tr
A port rise time
A Port
CEC Channels Enabled
0.74
ns
Voltage Level Shifter: SCL, SDA Lines (x_A & x_B ports); VCCA = 1.5V
VCCA = 1.5 V
tPLH
tPLH
PARAMETER
PINS
TEST CONDITIONS
Propagation delay
A to B
DDC Channels Enabled
MIN
TYP
MAX
B to A
265
A to B
438
B to A
169
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UNIT
335
ns
9
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Voltage Level Shifter: SCL, SDA Lines (x_A & x_B ports); VCCA = 1.5V (continued)
VCCA = 1.5 V
PARAMETER
tf
tr
fMAX
PINS
TEST CONDITIONS
A port fall time
A Port
DDC Channels Enabled
B port fall time
B Port
A port rise time
A Port
B port rise time
B Port
Maximum switching frequency
MIN
TYP
MAX
110
ns
83
DDC Channels Enabled
190
ns
92
DDC Channels Enabled
UNIT
400
kHz
Voltage Level Shifter: CEC Line (x_A & x_B ports); VCCA = 1.5V
VCCA = 1.5 V
tPLH
PARAMETER
PINS
TEST CONDITIONS
Propagation delay
A to B
CEC Channels Enabled
MIN
tf
tr
13
B to A
0.264
A Port
B port fall time
B Port
A port rise time
A Port
B port rise time
B Port
CEC Channels Enabled
ms
110
ns
96
CEC Channels Enabled
UNIT
ns
267
A to B
A port fall time
MAX
437
B to A
tPLH
TYP
202
ns
15
ms
Voltage Level Shifter: HPD Line (x_A & x_B ports); VCCA = 1.5V
VCCA = 1.5 V
tPLH
PARAMETER
PINS
TEST CONDITIONS
Propagation delay
B to A
CEC Channels Enabled
tPLH
MIN
TYP
MAX
10
B to A
UNIT
ms
9
tf
A port fall time
A Port
CEC Channels Enabled
0.47
ns
tr
A port rise time
A Port
CEC Channels Enabled
0.51
ns
Voltage Level Shifter: SCL, SDA Lines (x_A & x_B ports); VCCA = 1.8V
VCCA = 1.8 V
tPLH
PARAMETER
PINS
TEST CONDITIONS
Propagation delay
A to B
DDC Channels Enabled
tPLH
MIN
B to A
229
A to B
431
tr
fMAX
10
A port fall time
A Port
B port fall time
B Port
A port rise time
A Port
B port rise time
B Port
Maximum switching frequency
MAX
UNIT
334
B to A
tf
TYP
ns
169
DDC Channels Enabled
94
83
DDC Channels Enabled
191
92
DDC Channels Enabled
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400
ns
ns
kHz
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Voltage Level Shifter: CEC Line (x_A & x_B ports); VCCA = 1.8V
VCCA = 1.8 V
tPLH
PARAMETER
PINS
TEST CONDITIONS
Propagation delay
A to B
CEC Channels Enabled
tPLH
tf
tr
MIN
TYP
B to A
231
A to B
13
B to A
0.26
A port fall time
A Port
B port fall time
B Port
A port rise time
A Port
B port rise time
B Port
MAX
441
CEC Channels Enabled
ns
ms
94
ns
96
CEC Channels Enabled
UNIT
201
ns
15
ms
Voltage Level Shifter: HPD Line (x_A & x_B ports); VCCA = 1.8V
VCCA = 1.8 V
tPLH
PARAMETER
PINS
TEST CONDITIONS
Propagation delay
B to A
CEC Channels Enabled
tPLH
MIN
TYP
MAX
10
B to A
UNIT
ms
9
tf
A port fall time
A Port
CEC Channels Enabled
0.41
ns
tr
A port rise time
A Port
CEC Channels Enabled
0.45
ns
Voltage Level Shifter: SCL, SDA Lines (x_A & x_B ports); VCCA = 2.5V
VCCA = 2.5 V
tPLH
PARAMETER
PINS
TEST CONDITIONS
Propagation delay
A to B
DDC Channels Enabled
tPLH
MIN
182
A to B
423
tr
fMAX
A port fall time
A Port
B port fall time
B Port
A port rise time
A Port
B port rise time
B Port
Maximum switching frequency
MAX
UNIT
330
B to A
B to A
tf
TYP
ns
166
DDC Channels Enabled
79
ns
83
DDC Channels Enabled
188
ns
92
DDC Channels Enabled
400
kHz
Voltage Level Shifter: CEC Line (x_A & x_B ports); VCCA = 2.5V
VCCA = 2.5 V
tPLH
PARAMETER
PINS
TEST CONDITIONS
Propagation delay
A to B
CEC Channels Enabled
B to A
tPLH
tf
tr
MIN
TYP
184
A to B
13
B to A
0.255
A port fall time
A Port
B port fall time
B Port
A port rise time
A Port
B port rise time
B Port
MAX
454
CEC Channels Enabled
79
96
CEC Channels Enabled
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ns
ms
ns
194
ns
15
ms
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UNIT
11
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Voltage Level Shifter: HPD Line (x_A & x_B ports); VCCA = 2.5V
VCCA = 2.5 V
tPLH
PARAMETER
PINS
TEST CONDITIONS
Propagation delay
B to A
CEC Channels Enabled
tPLH
MIN
TYP
MAX
10
B to A
UNIT
ms
9
tf
A port fall time
A Port
CEC Channels Enabled
0.37
ns
tr
A port rise time
A Port
CEC Channels Enabled
0.39
ns
Voltage Level Shifter: SCL, SDA Lines (x_A & x_B ports); VCCA = 3.3V
VCCA = 3.3 V
tPLH
PARAMETER
PINS
TEST CONDITIONS
Propagation delay
A to B
DDC channels enabled
tPLH
MIN
B to A
158
A to B
421
tr
fMAX
A port fall time
A Port
B port fall time
B Port
A port rise time
A Port
B port rise time
B Port
Maximum switching frequency
MAX
UNIT
323
B to A
tf
TYP
ns
162
DDC channels enabled
71
ns
84
DDC channels enabled
188
ns
92
DDC channels enabled
400
kHz
Voltage Level Shifter: CEC Line (x_A & x_B ports); VCCA = 3.3V
VCCA = 3.3 V
tPLH
PARAMETER
PINS
TEST CONDITIONS
Propagation delay
A to B
CEC channels enabled
MIN
tf
tr
13
B to A
0.251
A Port
B port fall time
B Port
A port rise time
A Port
B port rise time
B Port
CEC channels enabled
ms
71
ns
96
CEC channels enabled
UNIT
ns
160
A to B
A port fall time
MAX
450
B to A
tPLH
TYP
194
ns
15
ms
Voltage Level Shifter: HPD Line (x_A & x_B ports); VCCA = 3.3V
VCCA = 3.3 V
tPLH
PARAMETER
PINS
TEST CONDITIONS
Propagation delay
B to A
CEC channels enabled
tPLH
B to A
MIN
TYP
10
9
MAX
UNIT
ms
tf
A port fall time
A Port
CEC channels enabled
0.35
ns
tr
A port rise time
A Port
CEC channels enabled
0.37
ns
12
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APPLICATION INFORMATION
DDC/CEC Level Shift Circuit Operation
The TPD12S015 enables DDC translation from VCCA (system side) voltage levels to 5V (HDMI cable side)
voltage levels without degradation of system performance. The TPD12S015 contains two bidirectional open-drain
buffers specifically designed to support up-translation/down-translation between the low voltage, VCCA side
DDC-bus and the 5V DDC-bus. The port B I/Os are over-voltage tolerant to 5.5 V even when the device is
unpowered. After powerup and with the LS_OE and CT_CP_HPD pins high, a low level on port A (below
approximately VILC = 0.08*VCCA V) turns the corresponding port B driver (either SDA or SCL) on and drives port
B down to VOLB V. When port A rises above approximately 0.10*VCCA V, the port B pulldown driver is turned off
and the internal pullup resistor pulls the pin high. When port B falls first and goes below 0.3*5VOUT, a CMOS
hysteresis input buffer detects the falling edge, turns on the port A driver, and pulls port A down to approximately
VOLA = 0.16*VCCA V. The port B pulldown is not enabled unless the port A voltage goes below VILC. If the port A
low voltage goes below VILC, the port B pulldown driver is enabled until port A rises above (VILC + ΔVT-HYSTA),
then port B, if not externally driven LOW, will continue to rise being pulled up by the internal pullup resistor.
VCCA
5VOUT
IACCEL CMP2
RPUA
RPUB
CMP1
150 mV
Glitch
Filter
700 mV
ACCEL
Port B
Port A
DDC Lines Only
300 mV
Figure 1. DDC/CEC Level Shifter Block Diagram
DDC/CEC Level Shifter Operational Notes for VCCA = 1.8 V
•
•
•
•
•
•
•
•
The threshold of CMP1 is ~150mV +/- the 40mV of total hysteresis.
The comparator will trip for a falling waveform at ~130mV
The comparator will trip for a rising waveform at ~170mV
To be recognized as a zero, the level at Port A must first go below 130mV (VILC in spec) and then stay below
170mV (VILA in spec)
To be recognized as a one, the level at A must first go above 170mV and then stay above 130mV
VILC is set to 110mV in Electrical Characteristics Table to give some margin to the 130mV
VILA is set to 140mV in the Electrical Characteristics Table to give some margin to the 170mV
VIHA is set to 70% of VCCA to be consistent with standard CMOS levels
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Figure 2. DDC/CEC Level Shifter Operation (B to A Direction)
Rise-Time Accelerators
The HDMI cable side of the DDC lines incorporates rise-time accelerators to support the high capacitive load on
the HDMI cable side. The rise time accelerator boosts the cable side DDC signal independent of which side of
the bus is releasing the signal.
Remark
Ground offset between the TPD12S015 ground and the ground of devices on port A of the TPD12S015 must be
avoided. The reason for this cautionary remark is that a CMOS/NMOS open-drain capable of sinking 3 mA of
current at 0.4 V will have an output resistance of 133 ohms or less (R = E / I). Such a driver will share enough
current with the port A output pull-down of the TPD12S015 to be seen as a LOW as long as the ground offset is
zero. If the ground offset is greater than 0 V, then the driver resistance must be less. Since VILC can be as low
as 90 mV at cold temperatures and the low end of the current distribution, the maximum ground offset should not
exceed 50 mV. Bus repeaters that use an output offset are not interoperable with the port A of the TPD12S015
as their output LOW levels will not be recognized by the TPD12S015 as a LOW. If the TPD12S015 is placed in
an application where the VIL of port A of the TPD12S015 does not go below its VILC it will pull port B LOW
initially when port A input transitions LOW but the port B will return HIGH, so it will not reproduce the port A input
on port B. Such applications should be avoided. Port B is interoperable with all I2C bus slaves, masters and
repeaters.
CEC Level Shift Operation
The CEC level shift function operates in the same manner as the DDC lines except that the CEC line does not
need the rise time accelerator function.
Internal Pullup Resistor
The TPD12S015 has incorporated all the required pullup and pulldown resistors at the interface pins. The system
is designed to work properly with no external pullup resistors on the DDC, CEC, and HPD lines. For proper
system operation no external resistors should be placed at the A and B ports. If there is internal pullups at the
host processor, they should be disabled.
14
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Power-Save Mode
The TPD12S015 integrates a power save mode to improve efficiency at light load. In power save mode the
converter only operates when the output voltage trips below a set threshold voltage. It ramps up the output
voltage with several pulses and goes into power save mode once the output voltage exceeds the set threshold
voltage. The PFM mode is left and PWM mode entered in case the output current can not longer be supported in
PFM mode.
Under-Voltage Lockout
The under voltage lockout circuit prevents the DC/DC converter from malfunctioning at low input voltages and
from excessive discharge of the battery. It disables the output stage of the converter once the falling VIN trips the
under-voltage lockout threshold VBATUV. The under-voltage lockout threshold VBATUV for falling VIN is typically
2.0V. The device starts operation once the rising VIN trips under-voltage lockout threshold VBATUV again at typical
2.1 V.
Enable
The DC/DC converter is enabled when the CT_CP_HPD is set to high. At first, the internal reference is activated
and the internal analog circuits are settled. Afterwards, the soft start is activated and the output voltage is
ramped up. The output voltage reaches its nominal value in typically 250 ms after the device has been enabled.
The CT_CP_HPD input can be used to control power sequencing in a system with various DC/DC converters.
The CT_CP_HPD pin can be connected to the output of another converter, to drive the EN pin high and getting a
sequencing of supply rails. With CT_CP_HPD = GND, the dc/dc enters shutdown mode.
Soft Start
The DC/DC converter has an internal soft start circuit that controls the ramp up of the output voltage. The output
voltage reaches its nominal value within tStart of typically 250 ms after CT_CP_HPD pin has been pulled to high
level. The output voltage ramps up from 5% to its nominal value within tRamp of 300 ms. This limits the inrush
current in the converter during start up and prevents possible input voltage drops when a battery or high
impedance power source is used. During soft start, the switch current limit is reduced to 300 mA until the output
voltage reaches VIN. Once the output voltage trips this threshold, the device operates with its nominal current
limit ILIMF.
Inductor Selection
To make sure that the TPD12S015 devices can operate, an inductor must be connected between pin VBAT and
pin L. A boost converter normally requires two main passive components for storing energy during the
conversion. A boost inductor and a storage capacitor at the output are required. To select the boost inductor, it is
recommended to keep the possible peak inductor current below the current limit threshold of the power switch in
the chosen configuration. The highest peak current through the inductor and the switch depends on the output
load, the input (VBAT), and the output voltage (5VOUT). Estimation of the maximum average inductor current can
be done using Equation 1.
IL _ MAX » IOUT ´
VOUT
h ´ VIN
(1)
For example, for an output current of 55 mA at 5VOUT, approx 150 mA of average current flows through the
inductor at a minimum input voltage of 2.3 V.
The second parameter for choosing the inductor is the desired current ripple in the inductor. Normally, it is
advisable to work with a ripple of less than 20% of the average inductor current. A smaller ripple reduces the
magnetic hysteresis losses in the inductor, as well as output voltage ripple and EMI. But in the same way,
regulation time at load changes rises. In addition, a larger inductor increases the total system size and cost. With
these parameters, it is possible to calculate the value of the minimum inductance by using Equation 2.
L M IN »
V IN ´ (V O U T - V IN )
D IL ´ f ´ V O U T
(2)
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Parameter f is the switching frequency and ΔIL is the ripple current in the inductor, i.e., 20% x IL. With this
calculated value and the calculated currents, it is possible to choose a suitable inductor. In typical applications a
1.0 mH inductance is recommended. The device has been optimized to operate with inductance values between
1.0 mH and 1.3 mH. It is recommended that an inductance value of at least 1.0 mH is used, even if Equation 2
yields something lower. Care has to be taken that load transients and losses in the circuit can lead to higher
currents as estimated in Equation 3. Also, the losses in the inductor caused by magnetic hysteresis losses and
copper losses are a major parameter for total circuit efficiency.
With the chosen inductance value, the peak current for the inductor in steady state operation can be calculated.
Equation 3 shows how to calculate the peak current I.
IL ( peak ) =
where
VIN ´ D
IOUT
+
2 ´ f ´ L (1 - D )´h
D=
(3)
VOUT - VIN
VOUT
This would be the critical value for the current rating for selecting the inductor. It also needs to be taken into
account that load transients and error conditions may cause higher inductor currents.
Input Capacitor
Because of the nature of the boost converter having a pulsating input current, a low ESR input capacitor is
required to prevent large voltage transients that can cause misbehavior of the device or interferences with other
circuits in the system. At least 1.2 uF input capacitor is recommended to improve transient behavior of the
regulator and EMI behavior of the total power supply circuit. It is recommended to place a ceramic capacitor as
close as possible to the VIN and GND pins and better to use a 4.7 uF capacitor, in order to improve the input
noise filtering.
Output Capacitor
For the output capacitor, it is recommended to use small ceramic capacitors placed as close as possible to the
VOUT and GND pins of the IC. If, for any reason, the application requires the use of large capacitors which can
not be placed close to the IC, using a smaller ceramic capacitor in parallel to the large one is recommended.
This small capacitor should be placed as close as possible to the VOUT and GND pins of the IC. To get an
estimate of the recommended minimum output capacitance, Equation 4 can be used.
C min =
IOUT ´ (VOUT - VIN )
f ´ DV ´ VOUT
(4)
Parameter f is the switching frequency and ΔV is the maximum allowed ripple. With a chosen ripple voltage of 10
mV, a minimum effective capacitance of 2.7 mF is needed. The total ripple is larger due to the ESR of the output
capacitor. This additional component of the ripple can be calculated using ΔVESR = IOUT x RESR
A capacitor with a value in the range of the calculated minimum should be used. This is required to maintain
control loop stability. There are no additional requirements regarding minimum ESR. There is no upper limit for
the output capacitance value. Larger capacitors cause lower output voltage ripple as well as lower output voltage
drop during load transients.
Note that ceramic capacitors have a DC Bias effect, which will have a strong influence on the final effective
capacitance needed. Therefore the right capacitor value has to be chosen very carefully. Package size and
voltage rating in combination with material are responsible for differences between the rated capacitor value and
the effective capacitance. The minimum effective capacitance value should be 1.2 uF but preferred value is
about 4.7 uF
16
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Table 1. Passive Components: Recommended Minimum Effective Values
COMPONENT
MIN
TARGET
MAX
UNIT
mF
CIN
1.2
4.7
6.5
COUT
1.2
4.7
10
mF
LIN
0.7
1
1.3
mH
VCCA
402
Cvcca
GND
Layer 1
Layer 2
5VOUT
603
Cout
SW
PGND
402
Cin
805
Lin
VBAT
Figure 3. Board Layout (DC-DC Components) (Top View)
List of components:
• LIN = MURATA LQM21PN1R0MC0 or LIN = Toko MDT2010-CN1R0
• CIN = MURATA GRM188R60J225ME19 (2.2 mF, 6.3 V, 0603, X5R) or MURATA GRM188R60J475ME19 (4.7
mF, 6.3 V, 0603, X5R)
• COUT = MURATA GRM188R60J475ME19 (4.7 mF, 6.3 V, 0603, X5R)
• CVCCA = MURATA GRM155R60J104MA01 (0.1 mF, 6.3 V, 0402, X5R)
TPD12S015 EVM Layout
The TPD12S015 EVM has been designed for HDMI functional testing and includes both HDMI A-type and HDMI
C-type connectors. Board jumpers enable and disable the dc-dc and level shifting circuitry. There are two supply
terminals (VCCA and VBAT) and one GND terminal at the edge of the board. High speed lines were kept on top
and bottom layers and matched for 50 Ω line to GND. All the high speed lines are matched to minimize the skew.
The board has three test fixtures for testing the TPD12S015 in the following environments:
• The top segment enables system designers to test the TPD12S015 using the HDMI Class A connector
• The middle segment enables the system designers to test to test the TPD12S015 using the HDMI Class C
connector
• The bottom segment enables the system designers to test signal integrity and eye pattern using differential
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probe.
Top Segment
Middle Segment
Bottom Segment
Figure 4. TPD12S015 EVM Top and Bottom View
The EVM board has 6 layers. The signal stack up is described below:
18
BOARD LAYER
DESCRIPTION
Layer 1
High-speed signal
layer
Layer 2
Ground plane
Layer 3
Control signal
layer
Layer 4
Control signal
layer
Layer 5
Power plane
Layer 6
High-speed signal
layer
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Figure 5. Layer 1: High-Speed Signal layer
Figure 6. Layer 6: High-Speed Signal layer
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TYPICAL CHARACTERISTICS
75
5.5
65
ICCB Current (mA)
5.4
ICC_5VOUT
5VOUT
5.3
60
5.2
55
5.1
50
5.0
45
4.9
40
4.8
35
4.7
30
4.6
25
4.5
20
4.4
15
4.3
10
4.2
5
4.1
0
5VOUT Voltage (V)
70
4.0
0 1
2 3 4
5 6 7
8 9 10 11 12 13 14 15 16 17 18 19 20
Time (us)
Figure 7. Load Transient Response
5.040
VBAT
5VOUT (20mA)
5VOUT (60mA)
4.1
VBAT Voltage (V)
4.0
5.020
5.000
3.9
4.980
3.8
4.960
3.7
4.940
3.6
4.920
3.5
4.900
3.4
4.880
3.3
4.860
3.2
4.840
3.1
4.820
3.0
0
500
5VOUT Voltage (V)
4.2
4.800
1000 1500 2000 2500 3000 3500 4000 4500 5000
Time (us)
Figure 8. Line Transient Response
20
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TYPICAL CHARACTERISTICS (continued)
6.0
VCCA = VIH = 2.5V, VBAT = 3.6V
5.5
5.0
4.5
4.0
Voltage (V)
3.5
3.0
2.5
2.0
CT_CP_HPD
VCCB (55mA)
VCCB (65mA)
1.5
1.0
0.5
0.0
-0.5
-1.0
-50
0
50
100
150
200
250
300
Time (us)
Figure 9. tSTART
6
VCCA = VIH = 2.5 V, VBAT = 3.6 V
5
CT_CP_HPD
5VOUT (55mA)
5VOUT (65mA)
Voltage (V)
4
3
2
1
0
-1
0
500
1000
1500
2000
2500
3000
3500
4000
Time (us)
Figure 10. DC/DC Startup and Shutdown
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21
TPD12S015
SLLSE19A – DECEMBER 2009 – REVISED JANUARY 2010
www.ti.com
TYPICAL CHARACTERISTICS (continued)
90
80
70
60
Amplitude (V)
50
40
30
20
10
0
-10
-20
-30
0
20
40
60
80
100
120
Time (ns)
140
160
180
200
Figure 11. IEC Clamping Waveforms 8 kV Contact (IEC ESD Pins)
30
20
10
0
Amplitude (V)
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
20
40
60
80
100 120
Time (ns)
140
160
180
200
Figure 12. IEC Clamping Waveforms -8 kV Contact (IEC ESD Pins)
22
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TPD12S015
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SLLSE19A – DECEMBER 2009 – REVISED JANUARY 2010
TYPICAL CHARACTERISTICS (continued)
0
Closest signals D2+ to D2Farthest signals D2+ to CLK+
D2+ to D2D2+ to CLK+
-20
S21 (dB)
-40
-60
-80
-100
Tested with typical
operating voltage
-120
1.00E+04
1.00E+05
1.00E+06
1.00E+07
1.00E+08
1.00E+09
1.00E+10
Frequency (Hz)
Figure 13. Channel-to-Channel Crosstalk
1.00000
S21
-1.00000
Insertion Loss (dB)
-3.00000
-5.00000
-7.00000
-9.00000
-11.00000
-13.00000
-15.00000
1.000E+07
1.000E+08
1.000E+09
1.000E+10
Frequency (Hz)
Figure 14. Insertion Loss Data Line to GND
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SLLSE19A – DECEMBER 2009 – REVISED JANUARY 2010
www.ti.com
TYPICAL CHARACTERISTICS (continued)
Figure 15. Eye Diagram Performance on a Test Board for the D+, D- Lines at 2.5 Gbps
Figure 16. Eye Diagram Performance on a Test Board for the D+, D- Lines at 3.3 Gbps
PARAMETER MEASUREMENT INFORMATION
VCCI
VCCO
DUT
IN
OUT
Input
24
CL
PIN
CL
DDC, CEC (A side)
750 pF
DDC, CEC, HPD (B
side)
15 pF
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1 MW
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TPD12S015
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SLLSE19A – DECEMBER 2009 – REVISED JANUARY 2010
VCC
Input
50%
50%
0V
Output
70%
30%
70%
30%
tf
VCC
VOL
tr
A.
RT termination resistance should be equal to ZOUT of pulse generators.
B.
CL includes probe and jig capacitance.
C.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate
≥ 1 V/ns.
D.
The outputs are measured one at a time, with one transition per measurement.
E.
tPLH and tPHL are the same as tpd.
Figure 17. Test Circuit and Voltage Waveforms
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25
PACKAGE OPTION ADDENDUM
www.ti.com
15-Feb-2010
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TPD12S015YFFR
ACTIVE
DSBGA
YFF
28
3000 Green (RoHS &
no Sb/Br)
TPD12S015YFFRB
PREVIEW
DSBGA
YFF
28
3000
TBD
Lead/Ball Finish
SNAGCU
Call TI
MSL Peak Temp (3)
Level-1-260C-UNLIM
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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