TI SN74GTLPH306

SN74GTLPH306
8-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
SCES284E – OCTOBER 1999 – REVISED AUGUST 2001
D
D
D
D
D
D
D
D
D
D
D
DGV, DW, OR PW PACKAGE
(TOP VIEW)
TI-OPC Circuitry Limits Ringing on
Unevenly Loaded Backplanes
OEC Circuitry Improves Signal Integrity
and Reduces Electromagnetic Interference
Bidirectional Interface Between GTLP
Signal Levels and LVTTL Logic Levels
LVTTL Interfaces Are 5-V Tolerant
Medium-Drive GTLP Outputs (50 mA)
LVTTL Outputs (–24 mA/24 mA)
GTLP Rise and Fall Times Designed for
Optimal Data-Transfer Rate and Signal
Integrity in Distributed Loads
Ioff and Power-Up 3-State Support Hot
Insertion
Bus Hold on A-Port Data Inputs
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
OE
VCC
A1
A2
A3
A4
GND
A5
A6
A7
A8
GND
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
DIR
VREF
B1
B2
B3
B4
GND
B5
B6
B7
B8
GND
description
The SN74GTLPH306 is a medium-drive, 8-bit bus transceiver that provides LVTTL-to-GTLP and
GTLP-to-LVTTL signal-level translation. The device provides a high-speed interface between cards operating
at LVTTL logic levels and a backplane operating at GTLP signal levels. High-speed (about three times faster
than standard LVTTL or TTL) backplane operation is a direct result of GTLP’s reduced output swing (<1 V),
reduced input threshold levels, improved differential input, OEC circuitry, and TI-OPC circuitry. Improved
GTLP OEC and TI-OPC circuits minimize bus-settling time and have been designed and tested using several
backplane models. The medium drive allows incident-wave switching in heavily loaded backplanes with
equivalent load impedance down to 19 Ω.
GTLP is the Texas Instruments (TI) derivative of the Gunning Transceiver Logic (GTL) JEDEC standard
JESD 8-3. The ac specification of the SN74GTLPH306 is given only at the preferred higher-noise-margin GTLP,
but the user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTLP
(VTT = 1.5 V and VREF = 1 V) signal levels.
Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels,
but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. VREF is the B-port differential input
reference voltage.
This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the device when it is powered down. The
power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
OEC, TI, and TI-OPC are trademarks of Texas Instruments.
Copyright  2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
SN74GTLPH306
8-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
SCES284E – OCTOBER 1999 – REVISED AUGUST 2001
description (continued)
This GTLP device features TI-OPC circuitry, which actively limits overshoot caused by improperly terminated
backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This improves
signal integrity, which allows adequate noise margin to be maintained at higher frequencies.
Active bus-hold circuitry holds unused or undriven LVTTL data inputs at a valid logic state. Use of pullup or
pulldown resistors with the bus-hold circuitry is not recommended.
When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, the output-enable (OE) input should be tied to VCC
through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of
the driver.
ORDERING INFORMATION
TOP-SIDE
MARKING
Tube
SN74GTLPH306DW
Tape and reel
SN74GTLPH306DWR
TSSOP – PW
Tape and reel
SN74GTLPH306PWR
GH306
TVSOP – DGV
Tape and reel
SN74GTLPH306DGVR
GH306
SOIC – DW
–40°C
40°C to 85°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
GTLPH306
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
functional description
The SN74GTLPH306 is an 8-bit bus transceiver and is designed for asynchronous communication between
data buses. The device transmits data from the A port to the B port or from the B port to the A port, depending
on the logic level at the direction-control (DIR) input. OE can be used to disable the device so the buses are
effectively isolated. Data polarity is noninverting.
For A-to-B data flow, when OE is low and DIR is high, the B outputs take on the logic value of the A inputs. When
OE is high, the outputs are in the high-impedance state.
The data flow for B to A is similar to A to B, except OE and DIR are low.
FUNCTION TABLE
INPUTS
2
OUTPUT
MODE
X
Z
Isolation
L
L
B data to A port
L
H
A data to B port
OE
DIR
H
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SN74GTLPH306
8-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
SCES284E – OCTOBER 1999 – REVISED AUGUST 2001
logic diagram (positive logic)
24
DIR
1
OE
A1
22
3
B1
23
VREF
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI (see Note 1): A port and control inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
B port and VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1): A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Current into any output in the low state, IO: A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
Current into any A port output in the high state, IO (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance, θJA (see Note 3): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
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SN74GTLPH306
8-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
SCES284E – OCTOBER 1999 – REVISED AUGUST 2001
recommended operating conditions (see Notes 4 through 7)
VCC
Supply voltage
VTT
Termination voltage
VREF
Reference voltage
VI
Input voltage
VIH
High level input voltage
High-level
VIL
Low level input voltage
Low-level
IIK
IOH
Input clamp current
Low level output current
Low-level
∆t/∆v
Input transition rise or fall rate
∆t/∆VCC
TA
Power-up ramp rate
NOM
MAX
UNIT
3.3
3.45
V
GTL
1.14
1.2
1.26
GTLP
1.35
1.5
1.65
GTL
0.74
0.8
0.87
GTLP
0.87
1
1.1
VCC
VTT
5.5
B port
Except B port
B port
Except B port
VREF+0.05
2
B port
V
V
V
V
VREF–0.05
0.8
V
–18
mA
A port
–24
mA
A port
24
B port
50
Except B port
High-level output current
IOL
MIN
3.15
Outputs enabled
10
–40
ns/V
µs/V
20
Operating free-air temperature
mA
85
°C
NOTES: 4. All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
5. Proper connection sequence for use of the B-port I/O precharge feature is GND and BIAS VCC = 3.3 V first, I/O second, and
VCC = 3.3 V last, because the BIAS VCC precharge circuitry is disabled when any VCC pin is connected. The control and VREF inputs
can be connected anytime, but normally are connected during the I/O stage. If B-port precharge is not required, any connection
sequence is acceptable, but generally, GND is connected first.
6. VTT and RTT can be adjusted to accommodate backplane impedances if the dc recommended IOL ratings are not exceeded.
7. VREF can be adjusted to optimize noise margins, but normally is two-thirds VTT. TI-OPC circuitry is enabled in the A-to-B direction
and is activated when VTT > 0.7 V above VREF. If operated in the A-to-B direction, VREF should be set to within 0.6 V of VTT to
minimize current drain.
4
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SN74GTLPH306
8-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
SCES284E – OCTOBER 1999 – REVISED AUGUST 2001
electrical characteristics over recommended operating free-air temperature range for GTLP
(unless otherwise noted)
PARAMETER
VIK
VOH
A port
TEST CONDITIONS
VCC = 3.15 V,
VCC = 3.15 V to 3.45 V,
II = –18 mA
IOH = –100 µA
VCC = 3
3.15
15 V
IOH = –12 mA
IOH = –24 mA
VCC = 3.15 V to 3.45 V,
A port
VOL
B port
A-port and
control inputs
II‡
VCC = 3
3.15
15 V
VCC = 3
3.15
15 V
VCC = 3.45 V
B port
IBHL§
IBHH¶
A port
IBHLO#
IBHHO||
A port
ICC
A port
A port
A or B port
Ciio
TYP†
Control inputs
MAX
UNIT
–1.2
V
VCC–0.2
2.4
V
2
IOL = 100 µA
IOL = 12 mA
0.2
IOL = 24 mA
IOL = 40 mA
0.5
IOL = 50 mA
VI = 0 or VCC
0.55
VI = 5.5 V
VI = 0 to 1.5 V
±20
0.4
V
0.4
±5
µA
µ
±5
75
µA
–75
µA
500
µA
VCC = 3.15 V,
VCC = 3.15 V,
VI = 0.8 V
VI = 2 V
VCC = 3.45 V,
VCC = 3.45 V,
VI = 0 to VCC
VI = 0 to VCC
VCC = 3.45 V, IO = 0,
VI (A-port or control input) = VCC or GND,
VI (B port) = VTT or GND
Outputs high
20
Outputs low
20
Outputs disabled
20
µA
–500
VCC = 3.45 V, One A-port or control input at VCC – 0.6 V,
Other A-port or control inputs at VCC or GND
∆ICCk
Ci
MIN
mA
1.5
mA
pF
4.5
5
A port
VI = 3.15 V or 0
VO = 3.15 V or 0
7.5
9
B port
VO = 1.5 V or 0
7.5
9
pF
† All typical values are at VCC = 3.3 V, TA = 25°C.
‡ For I/O ports, the parameter II includes the off-state output leakage current.
§ The bus-hold circuit can sink at least the minimum low sustaining current at VILmax. IBHL should be measured after lowering VIN to GND and
then raising it to VILmax.
¶ The bus-hold circuit can source at least the minimum high sustaining current at VIHmin. IBHH should be measured after raising VIN to VCC and
then lowering it to VIHmin.
# An external driver must source at least IBHLO to switch this node from low to high.
|| An external driver must sink at least IBHHO to switch this node from high to low.
k This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
hot-insertion specifications for A port over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
Ioff
IOZPU
VCC = 0,
VCC = 0 to 1.5 V,
VI or VO = 0 to 5.5 V
VO = 0.5 V to 3 V,
IOZPD
VCC = 1.5 V to 0,
VO = 0.5 V to 3 V,
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MIN
MAX
UNIT
10
µA
OE = 0
±30
µA
OE = 0
±30
µA
5
SN74GTLPH306
8-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
SCES284E – OCTOBER 1999 – REVISED AUGUST 2001
hot-insertion specifications for B port over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
Ioff
IOZPU
VCC = 0,
VCC = 0 to 1.5 V,
VI or VO = 0 to 1.5 V
VO = 0.5 V to 1.5 V,
IOZPD
VCC = 1.5 V to 0,
VO = 0.5 V to 1.5 V,
MIN
MAX
UNIT
10
µA
OE = 0
±30
µA
OE = 0
±30
µA
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, VTT = 1.5 V and VREF = 1 V for GTLP (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A
B
OE
B
ten
tdis
TYP†
MAX
1
7.5
1
7.5
1
8
1
8
UNIT
ns
ns
tr
tf
Rise time, B outputs (20% to 80%)
2.2
ns
Fall time, B outputs (80% to 20%)
2.1
ns
tr
tf
Rise time, A outputs (10% to 90%)
4.1
ns
Fall time, A outputs (90% to 10%)
tPLH
tPHL
ten
tdis
3.3
B
A
OE
A
† All typical values are at VCC = 3.3 V, TA = 25°C.
6
MIN
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ns
1
7
1
7
1
8
1
8
ns
ns
SN74GTLPH306
8-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
SCES284E – OCTOBER 1999 – REVISED AUGUST 2001
PARAMETER MEASUREMENT INFORMATION
1.5 V
6V
500 Ω
From Output
Under Test
S1
Open
GND
CL = 50 pF
(see Note A)
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
500 Ω
25 Ω
From Output
Under Test
CL = 30 pF
(see Note A)
S1
Open
6V
GND
LOAD CIRCUIT FOR A OUTPUTS
Test
Point
LOAD CIRCUIT FOR B OUTPUTS
3V
1.5 V
Input
1.5 V
0V
tPLH
tPHL
VOH
1V
Output
1V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(A port to B port)
1V
0V
tPLH
1.5 V
1.5 V
0V
Output
Waveform 1
S1 at 6 V
(see Note B)
tPHL
tPLZ
3V
1.5 V
VOL + 0.3 V
VOL
tPHZ
tPZH
VOH
Output
1.5 V
tPZL
1.5 V
1V
Input
3V
Output
Control
1.5 V
VOL
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(B port to A port)
1.5 V
VOH
VOH – 0.3 V
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
(A port)
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≈ 10 MHz, ZO = 50 Ω, tr ≈ 2 ns, tf ≈ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
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SN74GTLPH306
8-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
SCES284E – OCTOBER 1999 – REVISED AUGUST 2001
DISTRIBUTED-LOAD BACKPLANE SWITCHING CHARACTERISTICS
The preceding switching characteristics table shows the switching characteristics of the device into a lumped load
(Figure 1). However, the designer’s backplane application probably is a distributed load. The physical representation
is shown in Figure 2. This backplane, or distributed load, can be approximated closely to a resistor inductance
capacitance (RLC) circuit, as shown in Figure 3. This device has been designed for optimum performance in this RLC
circuit. The following switching characteristics table shows the switching characteristics of the device into the RLC
load, to help the designer better understand the performance of the GTLP device in this typical backplane. See
www.ti.com/sc/gtlp for more information.
38 Ω
.25”
ZO = 70 Ω
2”
Conn.
1”
Conn.
Conn.
1”
1”
2”
38 Ω
1.5 V
1.5 V
.25”
1.5 V
19 Ω
Conn.
From Output
Under Test
1”
LL = 19 nH
Test
Point
CL = 9 pF
Rcvr
Rcvr
Rcvr
Slot 2
Slot 9
Slot 10
Drvr
Slot 1
Figure 2. Medium-Drive Test Backplane
Figure 3. Medium-Drive RLC Network
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, VTT = 1.5 V and VREF = 1 V for GTLP (see Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A
B
OE
B
ten
tdis
tr
tf
3.6
4.1
4.4
4.6
UNIT
ns
ns
Rise time, B outputs (20% to 80%)
1.2
ns
Fall time, B outputs (80% to 20%)
2.2
ns
† All typical values are at VCC = 3.3 V, TA = 25°C. All values are derived from TI-SPICE models.
8
TYP†
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MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
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MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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