TI TLC5951DAPR

TLC5951
www.ti.com
SBVS127B – MARCH 2009 – REVISED DECEMBER 2009
24-Channel, 12-Bit PWM LED Driver with 7-Bit Dot Correction
and 3-Group, 8-Bit Global Brightness Control
Check for Samples: TLC5951
FEATURES
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24-Channel Constant-Current Sink Output
Current Capability: 40 mA
Selectable Grayscale (GS) Control with PWM:
12-Bit (4096 Step), 10-Bit (1024 Step), 8-Bit
(256 Step)
Three Independent Grayscale Clocks for Three
Color Groups
Dot Correction (DC): 7-Bit (128 Step)
Global Brightness Control (BC) for Each Color
Group: 8-Bit (256 Step)
Auto Display Repeat Function
Independent Data Port for GS and BC/DC Data
Communication Path Between Each Data Port
LED Power-Supply Voltage up to 15 V
VCC = 3.0 V to 5.5 V
Constant-Current Accuracy:
– Channel-to-Channel = ±1.5%
– Device-to-Device = ±3%
CMOS Logic Level I/O
Data Transfer Rate: 30 MHz
33-MHz Grayscale Control Clock
Continuous Base LED Open Detection (LOD)
Continuous Base LED Short Detection (LSD)
Thermal Shutdown (TSD) with Auto Restart
Grouped Delay to Prevent Inrush Current
Operating Air Temperature: –40°C to +85°C
Packages: HTSSOP-38, QFN-40
APPLICATIONS
•
•
Full-Color LED Displays
LED Signboards
DESCRIPTION
The TLC5951 is a 24-channel, constant-current sink
driver. Each channel has an individually-adjustable,
4096-step, pulse width modulation (PWM) grayscale
(GS) brightness control and 128 step constant-current
dot correction (DC). The dot correction adjusts
brightness deviation between channels and other
LED drivers. The output channels are grouped into
three groups of eight channels. Each channel group
has a 256-step global brightness control (BC) function
and an individual grayscale clock input.
VLED
OUTR0/G0/B0
GSSIN
¼
¼
¼
¼
¼
¼
OUTR7/G7/B7
GSSIN
GSSCK
OUTR0/G0/B0
GSSOUT
DCSCK
VCC
XBLNK
GSCKR
GSCKR
GSCKG
GSCKG
GCCKB
TLC5951
IC1
VCC
XBLNK
GSCKR
VCC
GSCKG
GND
GSCKB
GSCKB
IREF
IREF
RIREF
FLAGS
READ
DCSOUT
DCSIN
DCSCK
XBLNK
GSSOUT
GSLAT
DCSOUT
DCSIN
DCSCK
OUTR7/G7/B7
GSSCK
GSLAT
DCSIN
¼
GSSIN
GSSCK
GSLAT
Controller
¼
VCC
TLC5951
ICn
GND
RIREF
7
Typical Application Circuit (Multiple Daisy-Chained TLC5951s)
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments, Incorporated.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
TLC5951
SBVS127B – MARCH 2009 – REVISED DECEMBER 2009
www.ti.com
DESCRIPTION (CONTINUED)
GS, DC, and BC data are accessible via a serial interface port. DC and BC can be programmed via a dedicated
serial interface port.
The TLC5951 has three error detection circuits for LED open detection (LOD), LED short detection (LSD), and
thermal error flag (TEF). LOD detects a broken or disconnected LED while LSD detects a shorted LED. TEF
indicates an over-temperature condition.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Table 1. ORDERING INFORMATION (1)
PRODUCT
PACKAGE-LEAD
TLC5951
HTSSOP-38 PowerPAD™
TLC5951
(1)
ORDERING NUMBER
TRANSPORT MEDIA,
QUANTITY
TLC5951DAPR
Tape and Reel, 2000
6 mm × 6 mm QFN-40
TLC5951DAP
Tube, 40
TLC5951RHAR
Tape and Reel, 2500
TLC5951RHAT
Tape and Reel, 250
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
(2)
Over operating free-air temperature range, unless otherwise noted.
PARAMETER
VCC
Supply voltage
VCC
IOUT
Output current (dc)
VIN
Input voltage range
VOUT
Output voltage range
TJ(max)
Operation junction temperature
TSTG
Storage temperature
ESD rating
(1)
(2)
2
TLC5951
UNIT
–0.3 to +6.0
V
OUTR0 to R7, OUTG0 to G7, OUTB0 to B7
50
mA
GSSIN, GSSCK, GSLAT, GSCKR, GSCKG,
GSCKB, DCSIN, DCSCK, XBLNK, IREF
–0.3 to VCC + 0.3
V
GSSOUT, DCSOUT
–0.3 to VCC + 0.3
V
–0.3 to +16
V
OUTR0 to 7, OUTG0 to 7, OUTB0 to 7
+150
°C
–55 to +150
°C
Human body model (HBM)
2000
V
Charged device model (CDM)
500
V
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
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SBVS127B – MARCH 2009 – REVISED DECEMBER 2009
DISSIPATION RATINGS
PACKAGE
DERATING FACTOR
ABOVE TA = +25°C
TA < +25°C
POWER RATING
TA = +70°C
POWER RATING
TA = +85°C
POWER RATING
HTSSOP-38 with
PowerPAD soldered (1)
38.8 mW/°C
4845 mW
3101 mW
2519 mW
HTSSOP-38 with
PowerPAD not soldered (2)
19.9 mW/°C
2490 mW
1594 mW
1295 mW
QFN-40 (3)
26.7 mW/°C
3342 mW
2139 mW
1738 mW
(1)
(2)
(3)
With PowerPAD soldered onto copper area on printed circuit board (PCB); 2-oz. copper. For more information, see SLMA002 (available
for download at www.ti.com).
With PowerPAD not soldered onto copper area on PCB.
The package thermal impedance is calculated in accordance with JESD51-5.
RECOMMENDED OPERATING CONDITIONS
At TA = –40°C to +85°C, unless otherwise noted.
TLC5951
PARAMETER
MIN
NOM
MAX
UNIT
DC CHARACTERISTICS: VCC = 3 V to 5.5 V
VCC
Supply voltage
3.0
OUTR0-OUTR7, OUTG0-OUTG7,
OUTB0-OUTB7
5.5
V
15
V
V
VO
Voltage applied to output
VIH
High level input voltage
0.7 × VCC
VCC
VIL
Low level input voltage
GND
0.3 × VCC
IOH
High level output current
GSSOUT, DCSOUT
–1
mA
IOL
Low level output current
GSSOUT, DCSOUT
1
mA
IOLC
Constant output sink current
OUTR0-OUTR7, OUTG0-OUTG7,
OUTB0-OUTB7
40
mA
TA
Operating free-air
temperature
–40
+85
°C
TJ
Operating junction
temperature
–40
+125
°C
V
AC CHARACTERISTICS, VCC = 3V to 5.5V
fCLK
(SCK)
fCLK
Data shift clock frequency
GSSCK, DCSCK
30
MHz
Grayscale clock frequency
GSCKR, GSCKG, GSCKB
33
MHz
(GSCKR/G/B)
TWH0/TWL0
GSSCK, DCSCK
10
ns
GSLAT
30
ns
TWL2
XBLNK
30
ns
TSU0
GSSIN – GSSCK↑, DCSIN – DCSCK↑
TSU1
XBLNK↑ – GSCKR↑, GSCKG↑, or GSCKB↑
TSU2
GSLAT↑ – GSSCK↑
TWH1/TWL1
Pulse duration
5
ns
10
ns
150
ns
GSLAT↑ for GS data – GSCKR↑, GSCKG↑,
or GSCKB↑ when display timing reset mode
is disabled
40
ns
TSU4
GSLAT↑ for GS data – GSCKR↑, GSCKG↑,
or GSCKB↑ when display timing reset mode
is enabled
100
ns
TH0
GSSIN – GSSCK↑, DCSIN – DCSCK↑
5
ns
GSLAT↑ – GSSCK↑
35
ns
GSLAT↓ – GSSCK↑
5
ns
TSU3
TH1
Setup time
Hold time
TH2
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TLC5951
SBVS127B – MARCH 2009 – REVISED DECEMBER 2009
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ELECTRICAL CHARACTERISTICS
At TA = –40°C to +85°C, VCC = 3 V to 5.5 V, and VLED = 5 V, unless otherwise noted. Typical values are at TA = +25°C and
VCC = 3.3 V.
TLC5951
PARAMETER
TEST CONDITIONS
VOH
High level output voltage
At GSSOUT, DCSOUT, IOH = –1 mA
VOL
Low level output voltage
At GSSOUT, DCSOUT, IOL = 1 mA
Input current
At GSSCK, GSLAT, DCSIN, DCSCK, GSCKR/G/B with VI = VCC,
At GSSIN, GSSCK, GSLAT, DCSIN, XBLNK, DCSCK,
GSCKR/G/B with VI = GND
II
MIN
TYP
VCC – 0.4
–1
MAX
UNIT
VCC
V
0.4
V
1
μA
ICC1
GSSIN, GSSCK, GSLAT, DCSIN, DCSCK = low, XBLNK = low,
GSCKR/G/B = low, VOUTRn/Gn/Bn = 1 V, BCR/G/B = FFh,
DCRn/Gn/Bn = 7Fh with DC high adjustment range,
RIREF = 24 kΩ (IOUTRn/Gn/Bn = 2 mA target)
1
3
mA
ICC2
GSSIN, GSSCK, GSLAT, DCSIN, DCSCK = low, XBLNK = low,
GSCKR/G/B = low, VOUTRn/Gn/Bn = 1 V, BCR/G/B = FFh,
DCRn/Gn/Bn = 7Fh with DC high adjustment range,
RIREF = 2.4 kΩ (IOUTRn/Gn/Bn = 20 mA target)
6
10
mA
ICC3
GSSIN, GSSCK, GSLAT, DCSIN, DCSCK = low, XBLNK = high,
GSCKR/G/B = 33 MHz, VOUTRn/Gn/Bn = 1 V,
GSRn/Gn/Bn = FFFh, BCR/G/B = FFh,
DCRn/Gn/Bn = 7Fh with DC high adjustment range,
RIREF = 2.4 kΩ (IOUTRn/Gn/Bn = 20 mA target), auto repeat on
12
27
mA
ICC4
GSSIN, GSSCK, GSLAT, DCSIN, DCSCK = low, XBLNK = high,
GSCKR/G/B = 33 MHz, VOUTRn/Gn/Bn = 1 V,
GSRn/Gn/Bn = FFFh, BCR/G/B = FFh,
DCRn/Gn/Bn = 7Fh with DC high adjustment range,
RIREF = 1.2 kΩ (IOUTRn/Gn/Bn = 40 mA target), auto repeat on
21
55
mA
IOLC
Constant output current
At OUTR0-OUTR7, OUTG0-OUTG7, OUTB0-OUTB7,
All OUTRn/Gn/Bn = on, BCR/G/B = FFh,
DCRn/Gn/Bn = 7Fh with DC high adjustment range,
VOUTRn/Gn/Bn = 1 V, VOUTfix = 1 V,
RIREF = 1.2 kΩ (IOUTRn/Gn/Bn = 40 mA target)
40
45
mA
IOLKG
Leakage output current
At OUTR0-OUTR7, OUTG0-OUTG7 and OUTB0-OUTB7,
XBLNK = low, VOUTRn/Gn/Bn = VOUTfix = 15 V, RIREF = 1.2 kΩ
0.1
μA
ΔIOLC
Constant-current error (1)
(channel-to-channel in
same color group)
At OUTR0-OUTR7, OUTG0-OUTG7 and OUTB0-OUTB7,
All OUTRn/Gn/Bn = on, BCR/G/B = FFh,
DCRn/Gn/Bn = 7Fh with DC high adjustment range,
VOUTRn/Gn/Bn = 1 V, VOUTfix = 1 V,
RIREF = 1.2 kΩ (IOUTRn/Gn/Bn = 40 mA target)
±4
%
Supply current
(1)
35
±1.5
The deviation of each output in the same color group from the average of the same color group (OUTR0-OUTR7, OUTG0-OUTG7, or
OUTB0-OUTB7) constant current. The deviation is calculated by the formula (X = R, G, or B; n = 0-7):
D (%) =
IOUTXn (N = 0-7)
(IOUTX0 + IOUTX1 + ... + IOUTX6 + IOUTX7)
-1
´ 100
8
4
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TLC5951
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SBVS127B – MARCH 2009 – REVISED DECEMBER 2009
ELECTRICAL CHARACTERISTICS (continued)
At TA = –40°C to +85°C, VCC = 3 V to 5.5 V, and VLED = 5 V, unless otherwise noted. Typical values are at TA = +25°C and
VCC = 3.3 V.
TLC5951
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
±1
±3
%
ΔIOLC1
Constant current error (2)
(color group to color
group in same device)
At OUTR0-OUTR7, OUTG0-OUTG7 and OUTB0-OUTB7,
All OUTRn/Gn/Bn = on, BCR/G/B = FFh,
DCRn/Gn/Bn = 7Fh with DC high adjustment range,
VOUTRn/Gn/Bn = 1 V, VOUTfix = 1 V,
RIREF = 1.2 kΩ (IOUTRn/Gn/Bn = 40 mA target)
ΔIOLC2
Constant current error (3)
(device to device)
At OUTR0-OUTR7, OUTG0-OUTG7 and OUTB0-OUTB7,
All OUTRn/Gn/Bn = on, BCR/G/B = FFh,
DCRn/Gn/Bn = 7Fh with DC high adjustment range,
VOUTRn/Gn/Bn = 1 V, VOUTfix = 1 V,
RIREF = 1.2 kΩ (IOUTRn/Gn/Bn = 40 mA target)
±1
±6
%
At OUTR0-OUTR7, OUTG0-OUTG7 and OUTB0-OUTB7,
All OUTRn/Gn/Bn = on, BCR/G/B = FFh,
DCRn/Gn/Bn = 7Fh with DC high adjustment range,
VOUTRn/Gn/Bn = 1 V, VOUTfix = 1 V,
RIREF = 1.2 kΩ (IOUTRn/Gn/Bn = 40 mA target)
±0.5
±2
%/V
At OUTR0-OUTR7, OUTG0-OUTG7 and OUTB0-OUTB7,
All OUTRn/Gn/Bn = on, BCR/G/B = FFh,
DCRn/Gn/Bn = 7Fh with DC high adjustment range,
VOUTRn/Gn/Bn = 1 V, VOUTfix = 1 V,
RIREF = 1.2 kΩ (IOUTRn/Gn/Bn = 40 mA target)
±1
±3
%/V
ΔIOLC3
Line regulation
(4)
(5)
ΔIOLC4
Load regulation
TTEF
Thermal error flag
threshold (6)
Junction temperature
150
163
175
°C
THYS
Thermal error flag
hysteresis (6)
Junction temperature
5
10
20
°C
VLOD
LED open detection
threshold
All OUTRn/Gn/Bn = on
0.20
0.25
0.30
V
VLSD
LED short detection
threshold
All OUTRn/Gn/Bn = on
2.4
2.5
2.6
V
VIREF
Reference voltage output
RIREF = 1.2 kΩ
1.17
1.20
1.23
V
RPDWN
Pull-down resistor
At XBLNK, GSSIN
250
500
750
kΩ
(2)
The deviation of each color group in the same device from the average of all constant current. The deviation is calculated by the formula
(X = R, G, or B):
(IOUTX0 + IOUTX1 + ... + IOUTX6 + IOUTX7)
8
D (%) =
-1
´ 100
(IOUTR0+¼+IOUTR7 + IOUTG0+¼+IOUTG7 + IOUTB0+¼+IOUTB7)
24
(3)
The deviation of the all constant-current average from the ideal constant-current value. The deviation is calculated by the formula:
(IOUTR0+¼+IOUTR7 + IOUTG0+¼+IOUTG7 + IOUTB0+¼+IOUTB7)
- (Ideal Output Current)
24
D (%) =
´ 100
Ideal Output Current
Ideal current is calculated by the following equation:
IOUT(IDEAL, mA) = 40 ´
(4)
Line regulation is calculated by the following equation (X = R, G, or B; n = 0-7):
D (%/V) =
(5)
(IOUTXn at VCC = 5.5 V) - (IOUTXn at VCC = 3.0 V)
(IOUTXn at VCC = 3.0 V)
´
100
5.5 V - 3 V
Load regulation is calculated by the following equation (X = R, G, or B; n = 0-7):
D (%/V) =
(6)
1.20
RIREF (W)
(IOUTXn at VOUTXn = 3 V) - (IOUTXn at VOUTXn = 1 V)
(IOUTXn at VOUTXn = 1 V)
´
100
3V-1V
Not tested; specified by design.
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TLC5951
SBVS127B – MARCH 2009 – REVISED DECEMBER 2009
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SWITCHING CHARACTERISTICS
At TA = –40°C to +85°C, VCC = 3 V to 5.5 V, CL = 15 pF, RL = 100 Ω, RIREF = 1.2 kΩ, and VLED = 5.0 V, unless otherwise
noted. Typical values are at TA = +25°C and VCC = 3.3 V.
PARAMETER
tR0
TEST CONDITIONS
MIN
GSSOUT, DCSOUT
Rise time
tR1
OUTR0-OUTR7, OUTG0-OUTG7, OUTB0-OUTB7,
with BCR/G/B = FFh and DCRn/Gn/Bn = 7Fh with DC high adjustment
range
TYP MAX UNIT
6
15
ns
10
30
ns
tF0
GSSOUT, DCSOUT
6
15
ns
tF1
OUTR0-OUTR7, OUTG0-OUTG7, OUTB0-OUTB7,
with BCR/G/B = FFh and DCRn/Gn/Bn = 7Fh with DC high adjustment
range
10
30
ns
tD0
GSSCK↑ to GSSOUT, DCSCK↑ to DCSOUT
15
25
ns
tD1
GSLAT↑ to GSSOUT
50
100
ns
tD2
XBLNK↓ to OUTR0/G0/B0, OUTR4/G4/B4 off
20
40
ns
tD3
GSCKR/G/B↑ to OUTR0/G0/B0, OUTR4/G4/B4 on,
with BCR/G/B = FFh and DCRn/Gn/Bn = 7Fh with DC high adjustment
range
5
18
40
ns
tD4
GSCKR/G/B↑ to OUTR1/G1/B1, OUTR5/G5/B5 on,
with BCR/G/B = FFh and DCRn/Gn/Bn = 7Fh with DC high adjustment
range
20
42
73
ns
GSCKR/G/B↑ to OUTR2/G2/B2, OUTR6/G6/B6 on,
with BCR/G/B = FFh and DCRn/Gn/Bn = 7Fh with DC high adjustment
range
35
66
106
ns
tD6
GSCKR/G/B↑ to OUTR3/G3/B3, OUTR7/G7/B7 on,
with BCR/G/B = FFh and DCRn/Gn/Bn = 7Fh with DC high adjustment
range
50
90
140
ns
tD7
Internal latch pulse generation delay from DCSCK
3
5
7
ms
tD8
GSLAT↑ to IOUTRn/Gn/Bn changing by dot correction control
(control data are 0Ch → 72h or 72h → 0Ch with DC high adjustment
range), BCR/G/B = FFh
30
50
ns
tD9
GSLAT↑ to IOUTRn/Gn/Bn changing by global brightness control
(control data are 19h ≥ E6h or E6h ≥ 19h with DCRn/Gn/Bn = 7Fh with
DC high adjustment range)
100
300
ns
5
ns
Fall time
tD5
Propagation delay
tON_ERR
(1)
6
Output on-time error (1)
tOUT_ON – TGSCKR/G/B, GSDATA = 001h, GSCKR/G/B = 33 MHz,
with BCR/G/B = FFh and DCRn/Gn/Bn = 7Fh with DC high adjustment
range
–15
Output on-time error (tON_ERR) is calculated by the formula tON_ERR (ns) = tOUT_ON – TGSCKR/G/B. tOUT_ON indicates the actual on-time of
the constant current driver. TGSCKR is the period of GSCKR, TGSCKG is the period of GSCKG, and TGSCKB is the period of GSCKB.
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SBVS127B – MARCH 2009 – REVISED DECEMBER 2009
FUNCTIONAL BLOCK DIAGRAM
VCC
33rd GSCKR/G/B After XBLNK
Goes High or Internal Blank Signal
VCC
(1)
LOD/LSD Data Latch for R/G/B
216
48
LSB
MSB
GSSIN
288-Bit Common Shift Register
0
GSSOUT
287
288
Lower 216
GSSCK
LSB
MSB
Grayscale Data Latch
(12 Bits x 24 Channels)
Latch
Select
GSLAT
0
Higher 17
LSB
DCSIN
287
MSB
216-Bit DC/BC/FC/UD Shift Register
0
215
Lower 199
216
288
DCSCK
DCSOUT
LSB
MSB
Dot Correction (7-Bit x 24-Channels)/
Brightness Control (8-Bit x 3 Group)/
Function Control (7-Bit)/User-Defined (17-Bit) Data Latch
Auto Latch
Pulse Gen
0
215
216
216
TMGRST
3
GSCKR
GS Counter
for RED
GSCKG
Lower 198
96
12
DSPRPT/PWMMODE
12-Bit PWM
Timing Control
GS Counter
for GREEN
12
3
96
3
12-Bit PWM
Timing Control
96
GSCKB
8
GS Counter
for BLUE
3
3
8
12
12-Bit PWM
Timing Control
8
195
XBLNK
4-Grouped
Switch Delay
Reference
Current
Control
IREF
4-Grouped
Switch Delay
4-Grouped
Switch Delay
8
8
8
8
8
24
8
171
8-Bit Brightness
Control
8-Bit Brightness
Control
8-Bit Brightness
Control
24-Channel Constant-Current Driver with 7-Bit Dot Correction
GND
Thermal
Detection
48
GND
LED Open Detection (LOD)/LED Short Detection (LSD)
¼
¼
¼
OUTR0 ¼ OUTR7 OUTG0 ¼ OUTG7 OUTB0 ¼ OUTB7
(1) The internal blank signal is generated when GSLAT is input for GS data with display timing reset enabling. Furthermore, the signal is
generated at the 4096th GSCK when auto repeat mode is enabled. XBLNK can be connected to VCC when the display timing reset or auto
repeat is enabled.
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TLC5951
SBVS127B – MARCH 2009 – REVISED DECEMBER 2009
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PIN CONFIGURATIONS
DAP PACKAGE
HTSSOP-38 PowerPAD
(TOP VIEW)
IREF
GSCKB
6
33
GND
OUTG0
7
32
OUTR0
8
31
OUTR3
2
29
GSCKG
OUTB3
3
28
GSLAT
(1)
4
27
GSSCK
OUTG7
GSSOUT
5
26
GSSIN
OUTR7
DCSOUT
6
(1)
7
OUTG5
OUTR2
14
25
OUTR5
OUTB2
15
24
OUTB5
OUTG3
16
23
OUTG4
OUTR3
17
22
OUTR4
OUTB3
18
21
OUTB4
GSSOUT
19
20
DCSOUT
IREF
20
26
21
GND
13
10
19
OUTG2
OUTG4
18
OUTB6
OUTR7
27
OUTG7
12
VCC
17
OUTB1
XBLNK
22
16
OUTR6
23
9
OUTB7
28
DCSCK
8
OUTG6
11
DCSIN
OUTB4
15
OUTR1
25
24
OUTR4
14
OUTG6
OUTB6
29
OUTR6
OUTB7
NC
Thermal Pad
(Bottom Side)
13
30
NC
12
Thermal Pad
(Bottom Side)
GSCKR
OUTR5
10
30
OUTG5
OUTG1
1
11
9
OUTG3
OUTB5
OUTB0
GSCKB
34
31
5
OUTG0
GSCKR
OUTR0
VCC
32
35
33
4
OUTB0
GSCKG
OUTG1
XBLNK
34
36
35
3
OUTR1
GSLAT
OUTB1
DCSCK
36
37
37
2
OUTG2
GSSCK
OUTR2
DCSIN
38
38
39
1
OUTB2
GSSIN
40
RHA PACKAGE
6 mm × 6 mm QFN-40
(TOP VIEW)
(1) NC = no connection.
8
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SBVS127B – MARCH 2009 – REVISED DECEMBER 2009
TERMINAL FUNCTIONS
TERMINAL
NO.
NAME
DAP
RHA
I/O
DESCRIPTION
GSSIN
1
26
I
Serial data input for the 288-bit common shift register for grayscale (GS), dot
correction (DC), global brightness control (BC), and function control (FC) data.
GSSIN is connected to the LSB of the 288-bit common shift register. This pin is
internally pulled to GND with a 500-kΩ resistor.
GSSCK
2
27
I
Serial data shift clock for the 288-bit common shift register for GS/DC/BC/FC data.
Data present on GSSIN are shifted into the LSB of the shift register with the rising
edge of GSSCK. Data in the shift register are shifted toward the MSB at each
rising edge of GSSCK. The MSB data of the shift register appear on GSSOUT.
GSLAT
3
28
I
Data in the 288-bit common shift register are copied to the GS data latch or to the
DC/BC/FC data latch at the rising edge of GSLAT. The level of GSLAT at the last
GSSCK before the GSLAT rising edge determines which of the two latches the
data are transferred into. When GSLAT is low at the last GSSCK rising edge, all
288 bits in the common shift register are copied to the GS data latch. When
GSLAT is high at the last GSSCK rising edge, bits 0-198 are copied to the
DC/BC/FC data latch and bits 199-215 are copied to the 216-bit DC/BC/FC/UD
shift register. The GSLAT rising edge for a DC/BC/FC/UD data write must be input
more than 7 ms after a data write through the DCSIN pin.
GSSOUT
19
5
O
Serial data output of the 288-bit common shift register. LED open detection (LOD),
LED short detection (LSD), thermal error flag (TEF), and 199-bit data in the
DC/BC/FC data latch can be read via GSSOUT. GSSOUT is connected to the
MSB of the shift register. Data are clocked out at the rising edge of GSSCK.
DCSIN
38
25
I
Serial data input for the 216-bit DC/BC/FC/UD shift register. DCSIN is connected
to the LSB of the shift register.
DCSCK
37
24
I
Serial data shift clock for the 216-bit DC/BC/FC/UD shift register. Data present on
DCSIN are shifted into the LSB of the shift register with the DCSCK rising edge.
Data in the shift register are shifted toward the MSB at each DCSCK rising edge.
The MSB data of the register appear on DCSOUT. The 216-bit data in the shift
register are automatically copied to DC/BC/FC/UD data latch 3 ms to 7 ms after
the DCSCK rising edge is not input.
DCSOUT
20
6
O
Serial data output of the 216-bit shift register. DCSOUT is connected to the MSB of
the shift register. Data are clocked out at the rising edge of DCSCK.
GSCKR
5
30
I
Reference clock for the GS pulse width modulation (PWM) control for the RED
LED output group. When XBLNK is high, each GSCKR rising edge increments the
RED LED GS counter for PWM control.
GSCKG
4
29
I
Reference clock for the GS PWM control for the GREEN LED output group. When
XBLNK is high, each GSCKR rising edge increments the GREEN LED GS counter
for PWM control.
GSCKB
6
31
I
Reference clock for the GS PWM control for the BLUE LED output group. When
XBLNK is high, each GSCKR rising edge increments the BLUE LED GS counter
for PWM control.
When XBLNK is low, all constant-current outputs (OUTR0-OUTR7,
OUTG0-OUTG7, OUTB0-OUTB7) are forced off. The grayscale counters for each
color group are reset to '0', and the grayscale PWM timing controller is initialized.
When XBLNK is high, all constant current outputs are controlled by the grayscale
PWM timing controller for each color LED. This pin is internally pulled to GND with
a 500 kΩ resistor.
XBLNK
36
23
I
IREF
34
21
I/O
A resistor connected between IREF and GND sets the maximum current for all
constant current outputs.
O
Constant-current outputs for the RED LED group. These outputs are controlled
with the GSCKR clock signal.
The RED LED group is divided into four subgroups: OUTR0/OUTR4,
OUTR1/OUTR5, OUTR2/OUTR6, and OUTR3/OUTR7.
Each paired output turns on/off with 24 ns (typ) time delay between other paired
outputs. Multiple outputs can be tied together to increase the constant current
capability. Different voltages can be applied to each output.
OUTR0OUTR7
8, 11, 14,
17, 22, 25,
28, 31
2, 9, 12, 15,
18, 33, 36,
39
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TERMINAL FUNCTIONS (continued)
TERMINAL
NO.
NAME
OUTG0OUTG7
DAP
7, 10, 13,
16, 23, 26,
29, 32
RHA
1, 10, 13,
16, 19, 32,
35, 38
I/O
DESCRIPTION
O
Constant-current outputs for the GREEN LED group. These outputs are controlled
with the GSCKG clock signal.
The GREEN LED group is divided into four subgroups: OUTG0/OUTG4,
OUTG1/OUTG5, OUTG2/OUTG6, and OUTG3/OUTG7.
Each paired output turns on/off with 24 ns (typ) time delay between other paired
outputs. Multiple outputs can be tied together to increase the constant current
capability. Different voltages can be applied to each output.
9, 12, 15,
18, 21, 24,
27, 30
3, 8, 11, 14,
17, 34, 37,
40
O
Constant current outputs for the BLUE LED group. These outputs are controlled
with the GSCKB clock signal.
The BLUE LED group is divided into four subgroups: OUTB0/OUTB4,
OUTB1/OUTB5, OUTB2/OUTB6, and OUTB3/OUTB7.
Each paired output turns on/off with 24 ns (typ) time delay between other paired
outputs. Multiple outputs can be tied together to increase the constant current
capability. Different voltages can be applied to each output.
VCC
35
22
—
Power supply
GND
33
20
—
Power ground
NC
—
4, 7
—
No internal connection
OUTB0OUTB7
10
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SBVS127B – MARCH 2009 – REVISED DECEMBER 2009
PARAMETER MEASUREMENT INFORMATION
PIN EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
VCC
VCC
INPUT
INPUT
GND
GND
Figure 1. GSSCK, GSLAT, DCSIN, DCSCK, GSCKR,
GSCKG, GSCKB
Figure 2. GSSIN, XBLNK
VCC
OUTn
SOUT
GND
GND
Figure 3. GSSOUT, DCSOUT
Figure 4. OUTR0/G0/B0 Through OUTR7/G7/B7
TEST CIRCUITS
(2) CL includes measurement probe and jig capacitance.
(3) X = R, G, or B; n = 0-7.
(4) CL includes measurement probe and jig capacitance.
RL
VCC
VCC
OUTXn
IREF
RIREF
VCC
(2)
(1)
VLED
GND
SOUT
VCC
CL
GND
Figure 5. Rise Time and Fall Time Test Circuit for
OUTRn/Gn/Bn
CL
(1)
Figure 6. Rise Time and Fall Time Test Circuit for
GSSOUT and DCSOUT
VCC OUTR0
¼
VCC
IREF
(1)
¼
RIREF
OUTXn
GND OUTB7
VOUTfix
VOUTRn/Gn/Bn
(1) X = R, G, or B; n = 0-7.
Figure 7. Constant-Current Test Circuit for OUTRn/Gn/Bn
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TIMING DIAGRAMS
TWH0, TWL0, TWH1, TWL1, TWL2:
VCC
INPUT
50%
GND
TWH
TWL
TSU0, TSU1, TSU2, TSU3, TSU4, TH0, TH1, TH2:
VCC
CLOCK
(1)
INPUT
50%
GND
TSU
TH
VCC
DATA/CONTROL
(1)
INPUT
50%
GND
(2) Input pulse rise and fall time is 1 ns to 3 ns.
Figure 8. Input Timing
tR0, tR1, tF0, tF1, tD0, tD1, tD2, tD3, tD4, tD5, tD6, tD7, tD8, tD9:
VCC
(1)
INPUT
50%
GND
tD
VOH or VOUTRn/Gn/BnH
90%
OUTPUT
50%
10%
VOL or VOUTRn/Gn/BnL
tR or tF
(3) Input pulse rise and fall time is 1 ns to 3 ns.
Figure 9. Output Timing
12
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SBVS127B – MARCH 2009 – REVISED DECEMBER 2009
TIMING DIAGRAMS (continued)
GSR0
0A
GSSIN
GSB7
11B
GSB7
10B
GSB7
9B
GSB7
8B
GSR0
3B
GSB7
7B
GSR0
2B
TH0
GSB7
11C
GSB7
10C
GSB7
9C
GSB7
8C
GSB7
7C
GSB7
6C
GSB7
5C
1
2
3
4
5
6
7
GSB7
4C
GSB7
3C
TWH0
fCLK (SCLK)
TSU0
GSR0
0B
GSR0
1B
TSU2
GSSCK
1
2
3
4
5
285
286
287
288
TWL0
TH1
TWH1
GSLAT
TSU3, TSU4
XBLNK
fCLK (GSCKR/G/B)
TWL2
Shift Register Data Are Transferred to GS Data Latch
TSU1
GSCKR
(GSCKG)
(GSCKB)
Grayscale Data Latch
(Internal)
Dot Correction/
Brightness Control Function
Control Data Latch (Internal)
Previous Data
Latest Data
GSB7
10B
GSB7
9B
GSB7
8B
GSB7
7B
GSR0
3B
GSR0
2B
GSR0
1B
GSR0
0B
DCR0
Bit 0
GSB7
11C
GSB7
10C
GSB7
9C
GSB7
8C
GSB7
7C
GSB7
9C
GSB7
8C
GSB7
7C
Common Shift Register
Bit 1 (Internal)
DCR0
Bit 0
GSB7
11B
GSB7
10B
GSB7
9B
GSB7
8B
GSR0
4B
GSR0
3B
GSR0
2B
GSR0
1B
DCR0
Bit 1
DCR0
0B
GSB7
11C
GSB7
10C
GSB7
9C
GSB7
8C
GSB7
7C
GSB7
9C
GSB7
8C
LOD
B6A
LOD
B5A
LOD
B4A
LOD
B3A
LOD
B2A
DCR0
1A
DCR0
0A
GSR0
11B
GSR0
10B
LOD
B6B
LOD
B5B
LOD
B4B
LOD
B3B
LOD
B2B
LOD
B1B
LOD
B0B
LOD
G7B
LOD
G6B
LOD
B6A
LOD
B5A
LOD
B4A
LOD
B3A
DCR0
1A
DCR0
0A
GSB7
11B
LOD
B7B
¼
¼
¼
Common Shift Register
Bit 286 (Internal)
¼
GSB7
11B
¼
Common Shift Register
Bit 0 (Internal)
tD0
LOD
B7A
GSSOUT
tR0/tF0
OUTR0, OUTR4
(OUTG0, OUTG4)
(OUTB0, OUTB4)
OFF
OUTR1, OUTR5
(OUTG1, OUTG5)
(OUTB1, OUTB5)
OFF
OUTR2, OUTR6
(OUTG2, OUTG6)
(OUTB2, OUTB6)
OFF
OUTR3, OUTR7
(OUTG3, OUTG7)
(OUTB3, OUTB7)
OFF
ON
(VOUTRnH)
DCR0
3A
DCR0
2A
LOD
B6B
LOD
B5B
LOD
B4B
SID Data Are Transferred to
288-Bit Common Shift Register
LOD
B3B
LOD
B2B
LOD
B1B
LOD
B0B
LOD
G7B
tD2
ON
(VOUTRnL)
tF1
tD3
ON
ON
tR1
tD4
ON
ON
tD5
ON
ON
tD6
Figure 10. Grayscale Data Write Timing
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TIMING DIAGRAMS (continued)
GSR0
0A
GSSIN
NO
VAL71
NO
VAL70
NO
VAL69
NO
VAL68
NO
VAL67
DCR0
3B
DCR0
2B
DCR0
1B
TH0
TWH0
fCLK (SCLK)
TSU0
DCR0
0B
TH1
NO
VAL71
NO
VAL70
NO
VAL69
NO
VAL68
NO
VAL67
NO
VAL66
NO
VAL65
NO
VAL64
NO
VAL63
1
2
3
4
5
6
7
8
9
TSU2
GSSCK
1
2
3
4
5
285
286
287
TWL0
288
TWL1
GSLAT
TH2
XBLNK
fCLK (GSCKR/G/B)
TWL2
Shift Register Data Are Transferred
to DC/BC/FC/UD Data Latch
TSU1
GSCKR
(GSCKG)
(GSCKB)
Grayscale Data Latch
(Internal)
Dot Correction/
Brightness Control Function
Control Data Latch (Internal)
Previous Data
Latest Data
NO
VAL71
NO
VAL70
NO
VAL69
NO
VAL68
NO
VAL67
DCR0
3B
DCR0
2B
DCR0
1B
DCR0
0B
NO
VAL71
NO
VAL70
NO
VAL69
NO
VAL68
NO
VAL67
NO
VAL66
NO
VAL65
NO
VAL64
Common Shift Register
Bit 1 (Internal)
DCR0
1A
DCR0
0A
NO
VAL71
NO
VAL70
NO
VAL69
NO
VAL68
DCR0
4B
DCR0
3B
DCR0
2B
DCR0
1B
DCR0
0B
NO
VAL71
NO
VAL70
NO
VAL69
NO
VAL68
NO
VAL67
NO
VAL66
NO
VAL65
NO
VAL70
NO
VAL69
NO
VAL68
NO
VAL67
NO
VAL66
NO
VAL65
DCR0
1A
DCR0
0A
NO
VAL71
NO
VAL70
NO
VAL69
NO
VAL68
NO
VAL67
NO
VAL66
NO
VAL65
NO
VAL64
NO
VAL63
NO
VAL62
NO
VAL68
NO
VAL67
NO
VAL66
DCR0
1A
DCR0
0A
NO
VAL71
¼
¼
¼
Common Shift Register
Bit 286 (Internal)
¼
DCR0
0A
¼
Common Shift Register
Bit 0 (Internal)
tD0
NO
VAL71
GSSOUT
NO
NO
VAL70 VAL69
tR0/tF0
OUTR0, OUTR4
(OUTG0, OUTG4)
(OUTB0, OUTB4)
OFF
OUTR1, OUTR5
(OUTG1, OUTG5)
(OUTB1, OUTB5)
OFF
OUTR2, OUTR6
(OUTG2, OUTG6)
(OUTB2, OUTB6)
OFF
OUTR3, OUTR7
(OUTG3, OUTG7)
(OUTB3, OUTB7)
OFF
ON
NO
VAL70
SID Data Are Not Transferred to
288-Bit Common Shift Register
(VOUTRnH)
(VOUTRnL)
DCR0
2A
NO
VAL69
NO
VAL68
NO
VAL67
NO
VAL66
NO
VAL65
NO
VAL64
NO
VAL63
tD2
ON
tD3
ON
ON
tD4
ON
ON
tD5
ON
ON
tD6
tD8, tD9
Figure 11. Dot Correction/Global Brightness Control/Function Control/User-Defined
Data Write Timing from GS Data Path
14
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TIMING DIAGRAMS (continued)
DCR0
0A
DCSIN
USER
16B
USER
15B
USER
13B
USER
14B
DCR0
3B
USER
12B
DCR0
2B
DCR0
0B
DCR0
1B
USER
16C
USER
15C
USER
14C
USER
13C
USER
12C
USER
11C
USER
10C
TH0
TSU0
TWH0
DCSCK
1
2
3
4
5
213
214
215
TWL0
216
tD7
Auto Generated
Latch Pulse
(Internal)
Grayscale
Data Latch
(Internal)
DC/BC/FC/UD
Data Latch
(Internal)
Previous Data
Latest Data
tD0
USER
16A
DCSOUT
USER
15A
USER
14A
USER
13A
USER
12A
USER DCR0
3A
11A
DCR0
2A
DCR0
1A
USER
16B
DCR0
0A
USER
15B
USER
13B
USER
14B
USER
12B
USER
11B
USER
10B
USER
9B
tR0/tF0
Figure 12. Dot Correction/Global Brightness Control/Function Control
Data Write Timing from DC Data Path
GSSIN
GSR0
0B
GSR0
1B
287
288
TSU2
GSB7
11C
GSB7
10C
GSB7
9C
GSB7
8C
GSB7
7C
1
2
3
4
5
GSB6
0C
46
GSG6
11C
47
GSG5
1C
GSG6
10C
48
49
93
GSR5
11C
GSG5
0C
94
95
96
GSR0
0C
GSR0
1C
286
287
288
GSSCK
TH1 TWH1
GSLAT
GS Data Latch
(Internal)
Previous Data
Latest Data
DC/BC/FC/UC
Data Latch
(Internal)
GSR0
2B
GSR0
1B
GSR0
0B
DCR0
0
GSB7
11C
GSB7
10C
GSB7
9C
GSB7
8C
GSB6
2C
GSB6
1C
GSB6
0C
GSG5
2C
GSG5
1C
GSG5
0C
GSR0
2C
GSR0
1C
GSR0
0C
Common Shift
Register Bit 1
(Internal)
GSR0
3B
GSR0
2B
GSR0
1B
DCR0
1
DCR0
0
GSB7
11C
GSB7
10C
GSB7
9C
GSB6
3C
GSB6
2C
GSB6
1C
GSG5
3C
GSG5
2C
GSG5
1C
GSR0
3C
GSR0
2C
GSR0
1C
GSB7
11B
GSB7
10B
LOD
B6B
LOD
B5B
LOD
B4B
LOD
B3B
LOD
B2B
LSD
B0B
TEF
Reserved
FUNC
1
FUNC
0
BCB
6
DCR
0
GSB7
11C
GSB7
10C
GSB7
11B
LOD
B7B
LOD
B6B
LOD
B5B
LOD
B4B
LOD
B3B
LSD
R1B
LSD
R0B
TEF
FUNC
2
FUNC
1
FUNC
0
DCR
1
DCR
0
GSB7
11C
¼
GSSOUT
(Common Shift
Register Bit 287)
¼
Common Shift
Register Bit 286
(Internal)
¼
Common Shift
Register Bit 0
(Internal)
tD1
Figure 13. Status Information Data Read Timing
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TYPICAL CHARACTERISTICS
At TA = +25°C and VCC = 3.3 V, unless otherwise noted.
REFERENCE RESISTOR vs OUTPUT CURRENT
POWER DISSIPATION vs TEMPERATURE
6000
Power Dissipation Rate (mW)
RIREF, Reference Resistor (kW)
100
24000
10
9600
4800
3200
2400
1920
1600
0
20
10
TLC5951DAP, Soldered
4000
TLC5951RHA
3000
2000
TLC5951DAP, Not Soldered
1000
1200
1371
1
5000
0
40
30
-40
-20
Maximum Output Current (mA)
IO = 30 mA
IO = 20 mA
20
15
IO = 10 mA
IO = 5 mA
43
Output Current (mA)
Output Current (mA)
44
25
10
TA = +85°C
42
41
40
TA = +25°C
39
TA = -40°C
38
37
IO = 2 mA
5
IOLCMax = 40 mA, VCC = +3.3 V, BCX = FFh
DCXn = 7Fh with High Adjustment Range
36
0
35
0
0.5
1.0
1.5
2.5
2.0
0
3.0
0.5
Output Voltage (V)
IO = 30 mA
25
IO = 20 mA
20
15
IO = 10 mA
10
3.0
44
IO = 5 mA
43
Output Current (mA)
Output Current (mA)
30
2.5
OUTPUT CURRENT vs OUTPUT VOLTAGE
TA = +25°C, VCC = +5 V, BCX = FFh
DCXn = 7Fh with High Adjustment Range
35
2.0
45
IO = 40 mA
40
1.5
Figure 17.
OUTPUT CURRENT vs OUTPUT VOLTAGE
45
1.0
Output Voltage (V)
Figure 16.
TA = +85°C
42
41
40
TA = +25°C
39
TA = -40°C
38
37
IO = 2 mA
5
IOLCMax = 40 mA, VCC = +5 V, BCX = FFh
DCXn = 7Fh with High Adjustment Range
36
0
35
0
0.5
1.0
1.5
2.0
2.5
3.0
0
Output Voltage (V)
0.5
1.0
1.5
2.0
2.5
3.0
Output Voltage (V)
Figure 18.
16
100
80
OUTPUT CURRENT vs OUTPUT VOLTAGE
TA = +25°C, VCC = +3.3 V, BCX = FFh
DCXn = 7Fh with High Adjustment Range
30
60
45
IO = 40 mA
35
40
Figure 15.
OUTPUT CURRENT vs OUTPUT VOLTAGE
40
20
Free-Air Temperature (°C)
Figure 14.
45
0
Figure 19.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C and VCC = 3.3 V, unless otherwise noted.
CONSTANT-CURRENT ERROR
vs AMBIENT TEMPERATURE
(Channel-to-Channel, RED Color)
4
4
IOLCMax = 40 mA
DCRn = 7Fh with High Adjustment Range
BCR = FFh
3
2
2
1
1
0
-1
-2
0
-1
-2
VCC = 3.3 V
-3
-4
IOLCMax = 40 mA
DCGn = 7Fh with High Adjustment Range
BCG = FFh
3
DIOLC (%)
DIOLC (%)
CONSTANT-CURRENT ERROR
vs AMBIENT TEMPERATURE
(Channel-to-Channel, GREEN Color)
-40
-20
20
0
VCC = 3.3 V
-3
VCC = 5 V
40
60
80
-4
100
VCC = 5 V
-40
-20
4
CONSTANT-CURRENT ERROR
vs AMBIENT TEMPERATURE
(Channel-to-Channel, BLUE Color)
CONSTANT-CURRENT ERROR vs OUTPUT
(Channel-to-Channel, RED Color)
4
100
IOLCMax = 2 mA to 40 mA Set By RIREF
TA = +25°C
DCRn = 7Fh with High Adjustment Range
BCR = FFh
3
2
1
1
DIOLC (%)
DIOLC (%)
80
Figure 21.
0
-1
-2
0
-1
-2
VCC = 3.3 V
-3
-40
-20
20
0
VCC = 3.3 V
-3
VCC = 5 V
40
60
80
-4
100
VCC = 5 V
0
10
20
Ambient Temperature (°)
30
Figure 23.
CONSTANT-CURRENT ERROR vs OUTPUT
(Channel-to-Channel, GREEN Color)
CONSTANT-CURRENT ERROR vs OUTPUT
(Channel-to-Channel, BLUE Color)
4
4
IOLCMax = 2 mA to 40 mA Set By RIREF
TA = +25°C
DCGn = 7Fh with High Adjustment Range
BCG = FFh
2
IOLCMax = 2 mA to 40 mA Set By RIREF
TA = +25°C
DCBn = 7Fh with High Adjustment Range
BCB = FFh
3
2
DIOLC (%)
1
0
-1
-2
1
0
-1
-2
VCC = 3.3 V
-3
-4
40
Output Current (mA)
Figure 22.
3
DIOLC (%)
60
Figure 20.
2
-4
40
Ambient Temperature (°)
IOLCMax = 40 mA
DCBn = 7Fh with High Adjustment Range
BCB = FFh
3
20
0
Ambient Temperature (°)
0
10
VCC = 3.3 V
-3
VCC = 5 V
20
30
40
-4
VCC = 5 V
0
Output Current (mA)
10
20
30
40
Output Current (mA)
Figure 24.
Figure 25.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C and VCC = 3.3 V, unless otherwise noted.
CONSTANT-CURRENT ERROR vs OUTPUT
(Channel-to-Channel, RED Color)
4
4
Constant Current = 13 mA to 40 mA
Set By DCRn with High Adjustment Range
TA = +25°C, IOLCMax = 40 mA
BCR = FFh
3
2
2
1
0
-1
-2
10
20
25
30
35
-4
40
10
15
20
25
30
35
Figure 27.
CONSTANT-CURRENT ERROR vs OUTPUT
(Channel-to-Channel, BLUE Color)
CONSTANT-CURRENT ERROR vs OUTPUT
(Channel-to-Channel, RED Color)
4
Constant Current = 13 mA to 40 mA
Set By DCBn with High Adjustment Range
TA = +25°C, IOLCMax = 40 mA
BCB = FFh
2
1
0
-1
40
Constant Current = 2 mA to 27 mA
Set By DCRn with Low Adjustment Range
TA = +25°C, IOLCMax = 40 mA
BCR = FFh
3
-2
1
0
-1
-2
VCC = 3.3 V
-3
10
15
20
VCC = 3.3 V
-3
VCC = 5 V
25
30
35
-4
40
VCC = 5 V
0
5
10
15
20
25
Output Current (mA)
Output Current (mA)
Figure 28.
Figure 29.
CONSTANT-CURRENT ERROR vs OUTPUT
(Channel-to-Channel, GREEN Color)
CONSTANT-CURRENT ERROR vs OUTPUT
(Channel-to-Channel, BLUE Color)
4
4
Constant Current = 2 mA to 27 mA
Set By DCGn with Low Adjustment Range
TA = +25°C, IOLCMax = 40 mA
BCG = FFh
3
2
2
1
0
-1
-2
30
Constant Current = 2 mA to 27 mA
Set By DCBn with Low Adjustment Range
TA = +25°C, IOLCMax = 40 mA
BCB = FFh
3
DIOLC (%)
DIOLC (%)
VCC = 5 V
Figure 26.
DIOLC (%)
DIOLC (%)
15
VCC = 3.3 V
Output Current (mA)
2
1
0
-1
-2
VCC = 3.3 V
-3
18
-1
Output Current (mA)
3
-4
0
-3
VCC = 5 V
4
-4
1
-2
VCC = 3.3 V
-3
-4
Constant Current = 13 mA to 40 mA
Set By DCGn with High Adjustment Range
TA = +25°C, IOLCMax = 40 mA
BCG = FFh
3
DIOLC (%)
DIOLC (%)
CONSTANT-CURRENT ERROR vs OUTPUT
(Channel-to-Channel, GREEN Color)
0
5
10
VCC = 3.3 V
-3
VCC = 5 V
15
20
25
30
-4
VCC = 5 V
0
5
10
15
20
Output Current (mA)
Output Current (mA)
Figure 30.
Figure 31.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C and VCC = 3.3 V, unless otherwise noted.
CONSTANT-CURRENT ERROR vs OUTPUT
(Channel-to-Channel, RED Color)
4
4
Constant Current = 2 mA to 40 mA
Set By BCR with Low Adjustment Range
TA = +25°C, IOLCMax = 40 mA
DCRn = FFh
3
2
2
1
0
-1
-2
0
-1
10
VCC = 3.3 V
40
30
20
-4
VCC = 5 V
0
10
Output Current (mA)
Figure 32.
Figure 33.
CONSTANT-CURRENT ERROR vs OUTPUT
(Channel-to-Channel, BLUE Color)
DOT CORRECTION LINEARITY
(IOLCMax with Upper Range)
45
Constant Current = 2 mA to 40 mA
Set By BCB with Low Adjustment Range
TA = +25°C, IOLCMax = 40 mA
DCBn = FFh
Output Current (mA)
2
1
0
-1
-2
35
30
25
20
15
IO = 20 mA
5
VCC = 5 V
IO = 2 mA
0
0
10
40
30
20
0
16
32
Output Current (mA)
45
64
80
96
112
Figure 34.
Figure 35.
DOT CORRECTION LINEARITY
(IOLCMax with Lower Range)
DOT CORRECTION LINEARITY
(IOLCMax with Upper and Lower Range)
45
30
25
20
IO = 40 mA
15
IOLCMax = 40 mA
BCx = FFh
VCC = 3.3 V
40
Output Current (mA)
35
48
IO = 20 mA
10
35
High Adjustment Range
30
25
20
15
TA = -40°C
10
5
128
Dot Correction Data (dec)
Low Adjustment Range
TA = +25°C, BCx = FFh
VCC = 3.3 V
40
Output Current (mA)
IO = 40 mA
10
VCC = 3.3 V
-3
High Adjustment Range
TA = +25°C, BCx = FFh
VCC = 3.3 V
40
40
30
20
Output Current (mA)
3
DIOLC (%)
0
-3
VCC = 5 V
4
-4
1
-2
VCC = 3.3 V
-3
-4
Constant Current = 2 mA to 40 mA
Set By BCG with Low Adjustment Range
TA = +25°C, IOLCMax = 40 mA
DCGn = FFh
3
DIOLC (%)
DIOLC (%)
CONSTANT-CURRENT ERROR vs OUTPUT
(Channel-to-Channel, GREEN Color)
TA = +25°C
5
IO = 2 mA
0
TA = +85°C
Low Adjustment Range
0
0
16
32
48
64
80
96
112
128
0
Dot Correction Data (dec)
16
32
48
64
80
96
112
128
Dot Correction Data (dec)
Figure 36.
Figure 37.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C and VCC = 3.3 V, unless otherwise noted.
GLOBAL BRIGHTNESS CONTROL LINEARITY
(IOLCMax with Upper Range)
45
45
High Adjustment Range
TA = +25°C
DCXn = 7Fh
VCC = 3.3 V
35
High Adjustment Range
IOLCMax = 40 mA
DCXn = 7Fh
VCC = 3.3 V
40
30
Output Current (mA)
40
Output Current (mA)
GLOBAL BRIGHTNESS CONTROL LINEARITY
(Ambient Temperature with Upper Range)
IO = 40 mA
25
20
15
IO = 20 mA
10
35
30
25
20
15
TA = -40°C
10
5
TA = +25°C
5
IO = 2 mA
0
TA = +85°C
0
0
32
64
96
128
160
192
224
0
256
Brightness Correction Data (dec)
32
64
96
128
160
192
224
256
Brightness Correction Data (dec)
Figure 38.
Figure 39.
CONSTANT-CURRENT OUTPUT
VOLTAGE WAVEFORM
CH1 (2 V/div)
CH2 (2 V/div)
CH3 (2 V/div)
IOLCMax = 40 mA, BCX = 7Fh
DCXn = 7Fh with High Adjustment Range
TA = +25°C, GSCKR/G/B = 33 MHz
VCC = 3.3 V, VLED = 5 V, RL = 100 W, CL = 15 pF
Time (25 ns/div)
Figure 40.
20
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SBVS127B – MARCH 2009 – REVISED DECEMBER 2009
DETAILED DESCRIPTION
MAXIMUM CONSTANT SINK CURRENT VALUE
The TLC5951 maximum constant sink current value for each channel, IOLCMax, is determined by an external
resistor, RIREF, placed between RIREF and GND. The RIREF resistor value is calculated with Equation 1.
RIREF (kW) =
VIREF (V)
´ 40
IOLCMax (mA)
(1)
Where:
VIREF = the internal reference voltage on IREF (1.20 V, typically)
IOLCMax is the largest current for each output. Each output sinks the IOLCMax current when it is turned on, the dot
correction is set to the maximum value of 7Fh (127d), and the global brightness control data are set to the
maximum value of FFh (255d). Each output sink current can be reduced by lowering the output dot correction or
brightness control value.
RIREF must be between 1.2 kΩ and 24 kΩ to keep IOLCMax between 40 mA (typ) and 2mA (typ); the output may be
unstable when IOLCMax is set lower than 2 mA. Output currents lower than 2 mA can be achieved by setting
IOLCMax to 2 mA or higher and then using dot correction and global brightness control to lower the output current.
Figure 14 and Table 2 show the constant sink current versus external resistor, RIREF, characteristics. Multiple
outputs can be tied together to increase the constant-current capability. Different voltages can be applied to each
output.
Table 2. Maximum Constant Current Output versus
External Resistor Value
IOLCMax (mA, Typical)
RIREF (kΩ)
40
1.2
35
1.371
30
1.6
25
1.92
20
2.4
15
3.2
10
4.8
5
9.6
2
24
DOT CORRECTION (DC) FUNCTION
The TLC5951 has the capability to adjust the output current of each channel (OUTR0-OUTR7, OUTG0-OUTG7,
OUTB0-OUTB7) individually. This function is called dot correction (DC). The DC function allows the brightness
and color deviations of LEDs connected to each output to be individually adjusted. Each output DC is
programmed with a 7-bit word for each channel output. Each channel output current is adjusted with 128 steps
within one of two adjustment ranges. The dot correction high adjustment range allows the output current to be
adjusted from 33.3% to 100% of the maximum output current, IOLCMax. The dot correction low adjustment range
allows the output current to be adjusted from 0% to 66.7% of IOLCMax. The range control bits in the function
control latch select the high or low adjustment range. Equation 2 and Equation 3 calculate the actual output
current as a function of RIREF, DC value, adjustment range, and brightness control value. There are three range
control bits that control the DC adjustment range for three groups of outputs: OUTR0-OUTR7, OUTG0-OUTG7,
and OUTB0-OUTB7. DC data are programmed into the TLC5951 via the serial interface.
When the IC is powered on, the DC data in the 216-bit common shift register and data latch contain random
data. Therefore, DC data must be written to the DC latch before turning the constant-current output on.
Additionally, XBLNK should be low when the device turns on to prevent the outputs from turning on before the
proper grayscale values can be written. All constant-current outputs are off when XBLNK is low.
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GLOBAL BRIGHTNESS CONTROL (BC) FUNCTION
The TLC5951 has the capability to adjust the output current of each color group simultaneously. This function is
called global brightness control (BC). The global brightness control for each of the three color groups,
(OUTR0-OUTR7, OUTG0-OUTG7, and OUTB0-OUTB7), is programmed with a separate 8-bit word. The BC of
each group is adjusted with 256 steps from 0% to 100%. 0% corresponds to 0 mA. 100% corresponds to the
maximum output current programmed by RIREF and each output DC value. Note that even though the BC value
for all color groups are identical, the output currents can be different if the DC values are different. Equation 2
and Equation 3 calculate the actual output current as a function of RIREF, DC adjustment range, and brightness
control value. BC data are programmed into the TLC5951 via the serial interface.
When the IC is powered on, the BC data in the 216-bit common shift register and data latch contain random
data. Therefore, BC data must be written to the BC latch before turning the constant-current output on.
Additionally, XBLNK should be low when the device turns on to prevent the outputs from turning on before the
proper grayscale values can be written. All constant-current outputs are off when XBLNK is low.
Equation 2 determines the output sink current for each color group when the dot correction high adjustment
range is chosen.
1
2
DC
IOLCMax (mA) +
IOLCMax (mA) ´
3
3
127
IOUT (mA) =
´
BC
255
(2)
Equation 3 determines the output sink current for each color group when the dot correction low adjustment range
is chosen.
IOUT (mA) =
2
DC
IOLCMax (mA) ´
3
127
´
BC
255
(3)
Where:
IOLCMax = the maximum channel current for each channel determined by RIREF
DC = the decimal dot correction value for the output. This value ranges between 0 and 127.
BC = the decimal brightness control value for the output color group. This value ranges between 0 and 255.
Table 3. Output Current versus DC Data and IOLCMax with
Dot Correction High Adjustment Range (BC Data = FFh)
22
DC DATA
(Binary)
DC DATA
(Decimal)
DC DATA
(Hex)
BC DATA
(Hex)
PERCENTAGE
OF IOLCMax (%)
IOUT, mA
(IOLCMax = 40 mA)
IOUT, mA
(IOLCMax = 2 mA)
000 0000
0
00
FF
33.3
13.33
0.67
000 0001
1
01
FF
33.9
13.54
0.68
000 0010
2
02
FF
34.4
13.75
0.69
—
—
—
—
—
—
—
111 1101
125
7D
FF
99.0
39.58
1.98
111 1110
126
7E
FF
99.5
39.79
1.99
111 1111
127
7F
FF
100.0
40.00
2.00
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Table 4. Output Current versus DC Data and IOLCMax with
Dot Correction Low Adjustment Range (BC Data = FFh)
DC DATA
(Binary)
DC DATA
(Decimal)
DC DATA
(Hex)
BC DATA
(Hex)
PERCENTAGE
OF IOLCMax (%)
IOUT, mA
(IOLCMax = 40 mA)
IOUT, mA
(IOLCMax = 2 mA)
000 0000
0
00
FF
0
0
0
000 0001
1
01
FF
0.5
0.21
0.01
000 0010
2
02
FF
1.0
0.42
0.01
—
—
—
—
—
—
—
111 1101
125
7D
FF
65.6
26.25
1.31
111 1110
126
7E
FF
66.1
26.46
1.32
111 1111
127
7F
FF
66.7
26.67
1.33
Table 5. Output Current versus BC Data and IOLCMax with
Dot Correction High Adjustment Range (DC Data = 7Fh)
BC DATA
(Binary)
BC DATA
(Decimal)
BC DATA
(Hex)
DC DATA
(Hex)
PERCENTAGE
OF IOLCMax (%)
IOUT, mA
(IOLCMax = 40 mA)
IOUT, mA
(IOLCMax = 2 mA)
000 0000
0
00
7F
0
0
0
000 0001
1
01
7F
0.4
0.16
0.01
000 0010
2
02
7F
0.8
0.31
0.02
—
—
—
—
—
—
—
111 1101
253
FD
7F
99.2
39.69
1.98
111 1110
254
FE
7F
99.6
39.84
1.99
111 1111
255
FF
7F
100.0
40.00
2.00
Table 6. Output Current versus BC Data, DC Data, and IOLCMax with
Dot Correction High Adjustment Range
BC DATA
(Hex)
BC DATA
(Decimal)
DC DATA
(Hex)
DC DATA
(Decimal)
PERCENTAGE
OF IOLCMax (%)
IOLCMax = 40 mA
(mA, Typical)
IOLCMax = 2 mA
(mA, Typical)
00
0
20
32
0
0
0
—
—
—
—
—
—
—
33
51
20
32
10.02
4.01
0.2
—
—
—
—
—
—
—
80
128
20
32
25.16
10.06
0.5
—
—
—
—
—
—
—
CC
204
20
32
40.10
16.04
0.8
—
—
—
—
—
—
—
FF
255
20
32
50.13
13.33
1.0
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GRAYSCALE (GS) FUNCTION (PWM CONTROL)
The TLC5951 can adjust the brightness of each output channel using a pulse width modulation (PWM) control
scheme. The use of 12 bits per channel results in 4096 brightness steps, from 0% up to 100% brightness. The
grayscale circuitry is duplicated for each of the three color groups.
The PWM operation for each color group is controlled by a 12-bit GS counter. Three GS counters are
implemented to control each of the three color outputs, OUTR0-OUTR7, OUTG0-OUTG7, and OUTB0-OUTB7.
Each counter increments on each rising edge of the grayscale reference clock (GSCKR, GSCKG, or GSCKB).
The falling edge of XBLNK resets the three counter values to '0'. The grayscale counter values are held at '0'
while XBLNK is low, even if the GS clock input is toggled high and low. Pulling XBLNK high enables the GS
clock. The first rising edge of a GS clock after XBLNK goes high increments the corresponding grayscale counter
by one and switches on all outputs with a non-zero GS value programmed into the GS latch. Each additional
rising edge on a GS clock increases the corresponding GS counter by one.
The GS counters keep track of the number of clock pulses from the respective GS clock inputs (GSCKR,
GSCKG, and GSCKB). Each output stays on while the counter is less than or equal to the programmed
grayscale value. Each output turns off at the rising edge of the GS counter value when the counter is larger than
the output grayscale latch value.
Equation 4 calculates each output (OUTRn/Gn/Bn) on-time (tOUT_ON):
tOUTON (ns) = TGSCLKR/G/B (ns) ´ GSn
(4)
Where:
TGSCKR/G/B = one period of GS clock for the color
GSn = the programmed grayscale value for OUTRn/Gn/Bn (GSn = 0d to 4095d)
When new GS data are latched into the GS data latch with the rising edge on GSLAT during a PWM cycle, the
GS data latch registers are immediately updated. This latching can cause the outputs to turn on or off
unexpectedly. For proper operation, GS data should only be latched into the IC at the end of a display period
when XBLNK is low. Table 7 summarizes the GS data value versus the output on-time duty cycle.
When the IC is powered up, the 288-bit common shift register and GS data latch contain random data.
Therefore, GS data must be written to the GS latch before turning the constant-current output on. Additionally,
XBLNK should be low when the device is powered up to prevent the outputs from turning on before the proper
GS values are programmed into the registers. All constant-current outputs are off when XBLNK is low.
If there are any unconnected outputs (OUTRn, OUTGn, and OUTBn), including LEDs in a failed short or failed
open condition, the GS data corresponding to the unconnected output should be set to '0' before turning on the
LEDs. Otherwise, the VCC supply current (IVCC) increases while that constant-current output is programmed to
be on.
Table 7. Output Duty Cycle and On-Time versus GS Data
24
GS DATA
(Binary)
GS DATA
(Decimal)
GS DATA
(Hex)
OUTPUT ON-TIME DUTY
CYCLE (%)
OUTPUT ON-TIME
(33-MHz GS Clock) (ns)
0000 0000 0000
0
000
0
0
0000 0000 0001
1
001
0.02
30
0000 0000 0010
2
002
0.05
61
—
—
—
—
—
0111 1111 1111
2047
7FF
49.99
62030
1000 0000 0000
2048
800
50.01
62061
1000 0000 0001
2049
801
50.04
62091
—
—
—
—
—
1111 1111 1101
4093
FFD
99.95
124030
1111 1111 1110
4094
FFE
99.98
124061
1111 1111 1111
4095
FFF
100
124091
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PWM Counter 12-Bit Mode Without Auto Repeat
XBLNK
(1)
GSCKR
GSCKG
GSCKB
OUTRn/Gn/Bn
(GSDATA = 000h)
OFF (VOUTRn/Gn/BnH)
OFF
(VOUTRn/Gn/BnL)
(VOUTRn/Gn/BnL)
ON
(VOUTRn/Gn/BnL)
ON
(VOUTRn/Gn/BnH)
ON
(VOUTRn/Gn/BnL)
OFF
(VOUTRn/Gn/BnH)
T = GSCKR/G/B ´ 2048
ON
(VOUTRn/Gn/BnL)
OFF
(VOUTRn/Gn/BnH)
T = GSCKR/G/B ´ 2049
(VOUTRn/Gn/BnL)
ON
¼
¼
¼
T = GSCKR/G/B ´ 4093
(VOUTRn/Gn/BnH)
(VOUTRn/Gn/BnL)
ON
T = GSCKR/G/B ´ 4094
(VOUTRn/Gn/BnH)
(VOUTRn/Gn/BnL)
ON
OFF
OUTRn/Gn/Bn
(GSDATA = FFFh)
¼
T = GSCKR/G/B ´ 2047
OFF
OUTRn/Gn/Bn
(GSDATA = FFEh)
(VOUTRn/Gn/BnH)
T = GSCKR/G/B ´ 3
OFF
OUTRn/Gn/Bn
(GSDATA = FFDh)
(VOUTRn/Gn/BnH)
T = GSCKR/G/B ´ 2
¼
OUTRn/Gn/Bn
(GSDATA = 801h)
(VOUTRn/Gn/BnH)
T = GSCKR/G/B ´ 1
¼
OUTRn/Gn/Bn
(GSDATA = 800h)
¼
Drivers do not turn on when Grayscale data are zero.
OFF
OUTRn/Gn/Bn
(GSDATA = 7FFh)
1 2 3 4
¼
GS counter starts to count GSCKR/G/B after
XBLNK goes high.
OFF
OUTRn/Gn/Bn
(GSDATA = 003h)
¼
ON
OFF
OUTRn/Gn/Bn
(GSDATA = 002h)
4095
4096
4097 ¼
¼
ON (VOUTRn/Gn/BnL)
OUTRn/Gn/Bn
(GSDATA = 001h)
2048
2049
2050
1 2 3 4 ¼
T = GSCKR/G/B ´ 4095
(VOUTRn/Gn/BnH)
(VOUTRn/Gn/BnL)
ON
OUTRn/Gn/Bn turns on at the first rising edge of GSCKR/G/B after
XBLNK goes high except when Grayscale data are zero.
OUTRn/Gn/Bn does not turn on again until XBLNK goes low once
in case of no auto repeat mode.
(1) The internal blank signal is generated when GSLAT is input for GS data with display timing reset enabled. Also, the signal is generated at
4096th GSCKR/G/B when the auto repeat mode is enabled. XBLNK can be connected to VCC when the display timing reset or auto repeat is
enabled.
Figure 41. PWM Operation 1
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PWM Counter 8-, 10-, or 12-Bit Mode Without Auto Repeat
XBLNK
1 2 3 4
GSCKR
GSCKG
GSCKB
255
256
1023
1024
1025
257
¼
¼
¼
4095
4096
4097
¼
1 2 3 4
¼
¼
GS counter starts to count GSCKR/G/B after XBLNK goes high.
PWM 8-Bit Mode
(FC Bit 1/0 = 1/1)
OUTRn/Gn/Bn
(GSDATA = FFFh)
OFF (VOUTRn/Gn/BnH)
ON (VOUTRn/Gn/Bn)
OUTRn/Gn/Bn is forced off even if GS data is greater than 0FFh.
OUTRn/Gn/Bn does not turn on again until XBLNK goes low.
PWM 10-Bit Mode
(FC Bit 1/0 = 1/0)
OUTRn/Gn/Bn
(GSDATA = FFFh)
T = GSCKR/G/B ´ 255
OFF (VOUTXnH)
T = GSCKR/G/B ´ 1023
ON (VOUTRn/Gn/Bn)
OUTRn/Gn/Bn is forced off even if GS data are greater than 3FFh.
OUTRn/Gn/Bn does not turn on again until XBLNK goes low.
PWM 12-Bit Mode
(FC Bit 1/0 = 0/X)
OUTRn/Gn/Bn
(GSDATA = FFFh)
OFF (VOUTXnH)
T = GSCKR/G/B ´ 4095
ON (VOUTRn/Gn/Bn)
Figure 42. PWM Operation 2
PWM Counter 8-, 10-, or 12-Bit Mode With Auto Repeat
XBLNK
1 2 3
GSCKR
GSCKG
GSCKB
¼
256
255 257
¼
¼
1023
1024
1025
¼
¼
4095
4096
1 2
¼
¼
¼
4095
4096
1 2
¼
4095
4096
1 2
¼
¼
1
¼
GS counter starts to count GSCKR/G/B after XBLNK goes high.
PWM 8-Bit Mode
(FC Bit 1/0 = 1/1)
OUTRn/Gn/Bn
(GSDATA = 0FFh to FFFh)
OFF
T=
GSCKR/G/B ´ 255
T = GSCKR/G/B ´ 1
ON
OUTRn/Gn/Bn is forced off even if
GS data are greater than 0FFh.
PWM 10-Bit Mode
(FC Bit 1/0 = 1/0)
OUTRn/Gn/Bn
(GSDATA = 3FFh to FFFh)
PWM 12-Bit Mode
(FC Bit 1/0 = 0/X)
OUTRn/Gn/Bn
(GSDATA = FFFh)
OFF
x2 of off period
is generated.
x11 of off period
is generated.
x15 of off period
is generated.
T = GSCKR/G/B ´ 1023
ON
OUTRn/Gn/Bn is forced off even if
GS data are greater than 3FFh.
OFF
x2 of off period
is generated.
x3 of off period
is generated.
T = GSCKR/G/B ´ 4095
ON
Figure 43. PWM Operation 3
26
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REGISTER AND DATA LATCH CONFIGURATION
The TLC5951 has two data latches to store information: the grayscale (GS) data latch and the DC/BC/FC/UD
data latch. The GS data latch can be written as 288-bit data through GSSIN with GSSCK. The DC/BC/FC/UD
data latch can be written as data through DCSIN with DCSCK. Also, DC/BC/FC data can be written to the
DC/BC/FC/UD data latch through GSSIN with GSSCK. UD data are written to the upper 17 bits of the 216-bit
DC/BC/FC/UD shift register at the same time. The data in the DC/BC/FC/UC data latch can be read via
GSSOUT with GSSCK. Figure 44 shows the grayscale shift register and data latch configuration.
From 216-Bit DC/BC/FC/UD Data Latch
From LSD/LOD/TEF Data Holder
49
288-Bit Common Shift Register
These 49 bits of data are loaded into the
upper 49 bits of the 288-bit shift register
when GSLAT is low at the last GSSCK
rising edge before the rising edge of GSLAT.
These 216 bits of data are loaded into the
lower 216 bits of the 288-bit shift register when
GSLAT is low at the last GSSCK rising edge
before the rising edge of GSLAT.
216
LSB
MSB
GSSOUT
Common Common Common Common Common Common
Data Bit Data Bit Data Bit Data Bit Data Bit Data Bit
282
284
286
283
285
287
Common Common Common Common Common Common
Data Bit Data Bit Data Bit Data Bit Data Bit Data Bit
0
2
4
1
3
5
¼
GSSIN
GSSCK
288
Lower 216 Bits of 288 Bits
288
Grayscale Data Latch (12 Bits ´ 24 Channels)
MSB
287
OUTB7
Bit 11
276
¼
36
47
OUTB7
Bit 0
OUTR1
Bit 11
¼
GS Data for OUTB7
¼
24
35
OUTR1 OUTB0
Bit 0
Bit 11
GS Data for OUTR1
¼
GS Data for OUTB0
12
23
OUTB0 OUTG0
Bit 0
Bit 11
11
OUTG0 OUTR0
Bit 0
Bit 11
¼
GS Data for OUTG0
This latch
pulse is
generated
when GSLAT
is low at the
last GSSCK
rising edge
before the
GSLAT
rising edge.
LSB
0
¼
OUTR0
Bit 0
GS Data for OUTR0
288
To PWM Timing Control Block for Each Color
Upper 17 Bits of 216 Bits
These 17 bits of data are loaded into the upper 17 bits of the 216-bit shift register when GSLAT
is high at the last GSSCK rising edge before the GSLAT rising edge. The other bits remain unchanged.
216-Bit DC/BC/FC/UD Shift Register
DCSOUT
MSB
215
214
Data
Bit 215
Data
Bit 214
¼
¼
197
196
195
Data
Bit 197
Data
Bit 196
Data
Bit 195
Lower 199 Bits of 216 Bits
216
These 199 bits of data are loaded into the lower 199 bits of the
216-bit shift register when GSLAT is high at the last GSSCK
rising edge before the GSLAT rising edge. The User Defined
bit data in the 216-bit data latch remain unchanged.
¼
5
4
3
2
1
0
Data
Bit 5
Data
Bit 4
Data
Bit 3
Data
Bit 2
Data
Bit 1
Data
Bit 0
These 216 bits of data are automatically loaded into the
216-bit data latch by the latch pulse generated 3ms-7ms
after the DCSCK rising edge is not input.
DCSIN
DCSCK
Dot Correction (7 Bits ´ 24 Channels)/
Global Brightness Control (8 Bits ´ 3 Group)/
Function Control (7 Bits)
User Defined (17 Bits)
216-Bit DC/BC/FC/UD Data Latch
MSB
215-199 198-192 191-184 183-176 175-168 167-161 160-154 153-147
User
Defined
Bits 16-0
FUNC
Bits 6-0
BRIGHT BRIGHT BRIGHT DOTCOR DOTCOR DOTCOR
Bits 6-0
Bits 7-0
Bits 7-0
Bits 6-0
Bits 7-0
Bits 6-0
OUTB0-7 OUTG0-7 OUTR0-7 OUTB7
OUTG7
OUTR7
Function Global Brightness Control
Control
27-21
¼
20-14
13-7
LSB
6-0
DOTCOR DOTCOR DOTCOR DOTCOR
Bits 6-0
Bits 6-0
Bits 6-0
Bits 6-0
OUTR1
OUTG0 OUTR0
OUTB0
Dot Correction
This latch pulse is generated when
GSLAT is high at the last GSSCK
rising edge before the GSLAT
rising edge. Otherwise, the latch
pulse is generated 3 ms to 7 ms
after the DCSCK rising edge.
216
24
7
To GS Counter/PWM Timing
Control Block
To Global Brightness
Control Block
216
To 288-Bit Common
Shift Register
171
To Dot Correction
Control Block
Figure 44. Grayscale Shift Register and Data Latch Configuration
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288-Bit Common Shift Register
The 288-bit common shift register is used to shift data from the GSSIN pin into the TLC5951. The data shifted
into this register are used for grayscale data, global brightness control, and dot correction data. The register LSB
is connected to GSSIN and the MSB is connected to GSSOUT. On each GSSCK rising edge, the data on GSSIN
are shifted into the register LSB and all 288 bits are shifted towards the MSB. The register MSB is always
connected to GSSOUT.
The level of GSLAT at the last GSSCK before the GSLAT rising edge determines which latch the data are
transferred into. When GSLAT is low at the last GSSCK rising edge, all 288 bits are latched into the grayscale
data latch. When GSLAT is high at the last GSSCK rising edge, bits 0-198 are copied to bits 0-198 in the
DC/BC/FC/UD data latch and bits 199-215 are copied to bits 199-215 in the 216-bit DC/BC/FC/UD shift register
at the GSLAT rising edge. To avoid data from being corrupted, the GSLAT rising edge must be input more than
7 ms after the last DCSCK for a DC/BC/FC/UD data write. When the IC powers on, the 288-bit common shift
register contains random data.
Grayscale Data Latch
The grayscale (GS) data latch is 288 bits long. This latch contains the 12-bit PWM grayscale value for each of
the TLC5951 constant-current outputs. The PWM grayscale values in this latch set the PWM on-time for each
constant-current driver. See Table 7 for the on-time duty of each GS data bit. Figure 45 shows the shift register
and latch configuration. Refer to Figure 10 for the timing diagram for writing data into the GS shift register and
latch.
Data are latched from the 288-bit common shift register into the GS data latch at the rising edge of the GSLAT
pin. The conditions for latching data into this register are described in the 288-Bit Common Shift Register section.
When data are latched into the GS data latch, the new data are immediately available on the constant-current
outputs. For this reason, data should only be latched when XBLNK is low. If data are latched with XBLNK high,
the outputs may turn on or off unexpectedly.
MSB
287
OUTB7
Bit 11
276
¼
OUTB7
Bit 0
36
47
¼
GS Data for OUTB7
OUTR1
Bit 11
¼
OUTR1 OUTB0
Bit 0
Bit 11
GS Data for OUTR1
24
35
¼
OUTB0 OUTG0
Bit 0
Bit 11
GS Data for OUTB0
12
23
¼
OUTG0 OUTR0
Bit 0
Bit 11
GS Data for OUTG0
LSB
0
11
¼
OUTR0
Bit 0
GS Data for OUTR0
Figure 45. Grayscale Data Latch Configuration
28
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When the IC powers on, the grayscale data latch contains random data. Therefore, grayscale data must be
written to the 288-bit common shift register and latched into the GS data latch before turning on the
constant-current outputs. XBLNK should be low when powering on the TLC5951 to force all outputs off until the
internal registers can be programmed. All constant-current outputs are forced off when XBLNK is low. The data
bit assignment is shown in Table 8.
Table 8. Grayscale Data Bit Assignment
BITS
DATA
BITS
DATA
11-0
OUTR0
155-144
OUTR4
23-12
OUTG0
167-156
OUTG4
35-24
OUTB0
179-168
OUTB4
47-36
OUTR1
191-180
OUTR5
59-48
OUTG1
203-192
OUTG5
71-60
OUTB1
215-204
OUTB5
83-72
OUTR2
227-216
OUTR6
95-84
OUTG2
239-228
OUTG6
107-96
OUTB2
251-240
OUTB6
119-108
OUTR3
263-252
OUTR7
131-120
OUTG3
275-264
OUTG7
143-132
OUTB3
287-276
OUTB7
DC/BC/FC/UD Shift Register
The 216-bit DC/BC/FC/UD shift register is used to shift data from the DSSIN pin into the TLC5951. The data
shifted into this register are used for the dot correction (DC), global brightness control (BC), function control (FC),
and user-defined (UD) data latches. Each of these latches is described in the following sections. The register
LSB is connected to DCSIN and the MSB is connected to DCSOUT. On each DCSCK rising edge, the data on
DCSIN are shifted into the register LSB and all 216 bits are shifted towards the MSB. The register MSB is always
connected to DCOUT. When the IC is powered on, the 216-bit DC/BC/FC/UD shift register contains random
data.
DC/BC/FC/UD Data Latch
The 216-bit DC/BC/FC/UD data latch contains dot correction (DC) data, global brightness control (BC) data,
function control (FC) data, and user-defined (UD) data. Data can be written into this latch from the DC/BC/FC/UD
shift register. Furthermore, DC/BC/FC data can be written into this latch from the 288-bit common shift register.
At this time, UD data are written to bits 199-215 in the 216-bit DC/BC/FC/UD shift register data latch. When the
IC is powered on, the DC/BC/FC/UD data latch contains random data.
MSB
215-199 198-192 191-184 183-176 175-168 167-161 160-154 153-147 146-140
User
Defined
Bits 16-0
FUNC
Bits 6-0
BRIGHT BRIGHT BRIGHT DOTCOR DOTCOR DOTCOR DOTCOR
Bits 6-0
Bits 7-0
Bits 7-0
Bits 6-0
Bits 6-0
Bits 7-0
Bits 6-0
OUTR7
OUTG7
OUTB0-7 OUTG0-7 OUTR0-7 OUTB7
OUTB6
User Function Global Brightness Control
Defined Control
27-21
¼
20-14
13-7
LSB
6-0
DOTCOR DOTCOR DOTCOR DOTCOR
Bits 6-0
Bits 6-0
Bits 6-0
Bits 6-0
OUTB0
OUTG0 OUTR0
OUTR1
Dot Correction
Figure 46. DC/BC/FC/UD Data Latch Configuration
Dot Correction Data Latch
The dot correction (DC) data latch is 168 bits long. The DC data latch consists of bits 0-167 in the DC/BC/FC/UD
data latch. This latch contains the 7-bit DC value for each of the TLC5951 constant-current outputs. Each DC
value individually adjusts the output current for each constant-current driver. As explained in the Dot Correction
(DC) Function section, the DC values are used to adjust the output current from 0% to 66.7% of the maximum
value when the dot correction low adjustment range is selected and from 33.3% to 100% of the maximum value
when the dot correction high adjustment range is selected. The adjustment range is selected by the range control
bits in the function control latch.
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Table 3 and Table 4 show how the DC data affect the percentage of the maximum current each output. See
Figure 46 for the DC data latch configuration. Figure 11 illustrates the timing diagram for writing data from the GS
data path into the shift registers and latches. Figure 12 illustrates the timing diagram for writing data from the DC
data path into the shift registers and DC latches. DC data are automatically latched from the DC/BC/FC/UD shift
register into the DC data latch with an internal latch signal. The internal latch signal is generated in 3 ms to 7 ms
after the last DCSCK rising edge.
When the IC powers on, the DC data latch contains random data. Therefore, DC data must be written into the
TLC5951 and latched into the DC data latch before turning on the constant-current outputs. XBLNK should be
low when powering on the TLC5951 to force all outputs off until the internal registers can be programmed. All
constant-current outputs are forced off when XBLNK is low. The data bit assignment is shown in Table 9.
Table 9. Dot Correction Data Bit Assignment
BITS
DATA
BITS
DATA
6-0
OUTR0
90-84
OUTR4
13-7
OUTG0
97-91
OUTG4
20-14
OUTB0
104-98
OUTB4
27-21
OUTR1
111-105
OUTR5
34-28
OUTG1
118-112
OUTG5
41-35
OUTB1
125-119
OUTB5
48-42
OUTR2
132-126
OUTR6
55-49
OUTG2
139-133
OUTG6
62-56
OUTB2
146-140
OUTB6
69-63
OUTR3
153-147
OUTR7
76-70
OUTG3
160-154
OUTG7
83-77
OUTB3
167-161
OUTB7
Global Brightness Control Data Latch
The global brightness control (BC) data latch is 24 bits long. The BC data latch consists of bits 168-191 in the
DC/BC/FC/UD data latch.
The data of the BC data latch are used to adjust the constant-current values for eight channel constant-current
drivers of each color group. The current can be adjusted from 0% to 100% of each output current adjusted by
brightness control with 8-bit resolution. Table 5 describes the percentage of the maximum current for each
brightness control data.
When the IC is powered on, the data in the BC data latch are not set to a specific default value. Therefore,
brightness control data must be written to the BC latch before turning on the constant-current output. The data bit
assignment is shown in Table 10.
Table 10. Data Bit Assignment
BITS
30
GLOBAL BRIGHTNESS CONTROL DATA BITS 7-0
175-168
OUTR0-OUTR7 group
183-176
OUTG0-OUTG7 group
191-184
OUTB0-OUTB7 group
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Function Control Data Latch
The function control (FC) data latch is 7 bits in length and is used to select the dot correction adjustment range,
grayscale counter mode, enabling of the auto display repeat, and display timing reset function. When the IC is
powered on, the data in the FC latch are not set to a specific default value. Therefore, function control data must
be written to the FC data latch before turning on the constant current output.
Table 11. Data Bit Assignment
BIT
DESCRIPTION
192
Dot correction adjustment range for the RED color output (0 = lower range, 1 = higher range).
When this bit is '0', dot correction can control the range of constant current by 0% to 66.7% (typ) of the maximum current set
by an external resistor. This mode only operates the output for the red LED driver group.
When this bit is '1', dot correction can control the range of constant current by 33.3% (typ) to 100% of the maximum current set
by an external resistor.
193
Dot correction adjustment range for the GREEN color output (0 = lower range, 1 = higher range).
When this bit is '0', dot correction can control the range of constant current by 0% to 66.7% (typ) of the maximum current set
by an external resistor. This mode only operates the output for the green LED driver group.
When this bit is '1', dot correction can control the range of constant current by 33.3% (typ) to 100% of the maximum current set
by an external resistor.
194
Dot correction adjustment range for the BLUE color output (0 = lower range, 1 = higher range).
When this bit is '0', dot correction can control the range of constant current by 0% to 66.7% (typ) of the maximum current set
by an external resistor. This mode only operates the output for the blue LED driver group.
When this bit is '1', dot correction can control the range of constant current by 33.3% (typ) to 100% of the maximum current set
by an external resistor.
195
Auto display repeat mode (0 = disabled, 1 = enabled).
When this bit is '0', the auto repeat function is disabled. Each output driver is turned on and off once after XBLNK goes high.
When this bit is '1', each output driver is repeatedly toggled on/off every 4096th grayscale clock without the XBLNK level
changing when the GS counter is configured as a 12-bit mode. If the GS counter is configured as a 10-bit mode, the outputs
continue to cycle on/off every 1024th grayscale clock. If the GS counter is set to the 8-bit mode, the output on/off repetition
cycles every 256th grayscale clock.
196
Display timing reset mode (0 = disabled, 1 = enabled).
When this bit is '1', the GS counter is reset to '0' and all outputs are forced off at the GSLAT rising edge for a GS data write.
This function is identical to the low pulse of the XBLNK signal when input. Therefore, the XBLNK signal is not needed to
control from a display controller. PWM control starts again from the next input GSCKR/G/B rising edge.
When this bit is '0', the GS counter is not reset and no outputs are forced off even if a GSLAT rising edge is input. In this
mode, the XBLNK signal should be input after the PWM control of all LED are finished. Otherwise, the PWM control might be
not exact.
198, 197
Grayscale counter mode select, bits 1-0.
The grayscale counter mode is selected by the setting of bits 1 and 0. Table 12 shows the GS counter mode.
Table 12. GS Counter Mode Truth Table
GRAYSCALE COUNTER MODE
BIT 1
BIT 0
FUNCTION MODE
0
X (don't care)
12-bit counter mode (maximum output on-time = 4095 × GS clock)
1
0
10-bit counter mode (maximum output on-time = 1023 × GS clock)
1
1
8-bit counter mode (maximum output on-time = 255 × GS clock)
The grayscale data latch bit length is always 288 bits in any grayscale counter mode. All constant-current outputs
are forced off at the 256th grayscale clock in the 8-bit mode even if all grayscale data are FFFh. In 10-bit mode,
all outputs are forced off at 1024th grayscale clock even if all grayscale data are FFFh.
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User-Defined Data Latch
The user-defined (UD) data latch is 17 bits in length and is not used for any device functionality. However, these
data can be used for communication between a controller connected to DCSIN and another controller connected
to GSSIN. When the IC is powered on, the data in the UD latch are not set to a specific default value.
Table 13. Data Bit Assignment
BITS
USER-DEFINED DATA BITS
215-199
16-0
STATUS INFORMATION DATA (SID)
Status information data (SID) are 288 bits in length and are read-only data. SID consists of the LED open
detection (LOD) error, LED short detection (LSD), thermal error flag (TEF), and the data in the DC/BC/FC/UD
data latch. The SID are shifted out onto GSSOUT with the GSSCK rising edge after GSLAT is input for a GS
data write. These SID are loaded into the 288-bit common shift register after data in the 288-bit common shift
register are copied to the data latch.
LOD/LSD Data Latch (48 Bits)
216-Bit DC/BC/FC/UD Data Latch
LSB
MSB
LOD
Data of
OUTB7
¼
LOD
Data of
OUTR0
LSD
Data of
OUTB7
¼
LSD
Data of
OUTR0
TEF
Function
Control
Bits 6-0
BC Data
of
OUTBn
¼
BC Data
of
OUTRn
BC Data
of
OUTB7
¼
BC Data
of
OUTR0
Common Common Common
Data Bit Data Bit Data Bit
191
215-199 198-192
¼
Common Common
Data Bit Data Bit
167
168
¼
Common
Data Bit
0
User
Defined
Bits 16-0
17
7
(Reserved Data)
GSSOUT
Common
Data Bit
287
¼
Common Common
Data Bit Data Bit
263
264
¼
Common Common
Data Bit Data Bit
239
240
Common
Data Bit
238-216
GSSIN
GSSCK
LSB
MSB
288-Bit Common Shift Register
Figure 47. DC/BC/FC Data Load Assignment
32
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Table 14. Data Bit Assignment
BITS
DESCRIPTION
6-0
Dot correction data bits 6-0 for OUTR0
13-7
Dot correction data bits 6-0 for OUTG0
20-14
Dot correction data bits 6-0 for OUTB0
27-21
Dot correction data bits 6-0 for OUTR1
34-28
Dot correction data bits 6-0 for OUTG1
41-35
Dot correction data bits 6-0 for OUTB1
48-42
Dot correction data bits 6-0 for OUTR2
55-49
Dot correction data bits 6-0 for OUTG2
62-56
Dot correction data bits 6-0 for OUTB2
69-63
Dot correction data bits 6-0 for OUTR3
76-70
Dot correction data bits 6-0 for OUTG3
83-77
Dot correction data bits 6-0 for OUTB3
90-84
Dot correction data bits 6-0 for OUTR4
97-91
Dot correction data bits 6-0 for OUTG4
104-98
Dot correction data bits 6-0 for OUTB4
111-105
Dot correction data bits 6-0 for OUTR5
118-112
Dot correction data bits 6-0 for OUTG5
125-119
Dot correction data bits 6-0 for OUTB5
132-126
Dot correction data bits 6-0 for OUTR6
139-133
Dot correction data bits 6-0 for OUTG6
146-140
Dot correction data bits 6-0 for OUTB6
153-147
Dot correction data bits 6-0 for OUTR7
160-154
Dot correction data bits 6-0 for OUTG7
167-161
Dot correction data bits 6-0 for OUTB7
175-168
Global brightness control data bits 7-0 for OUTR0-OUTR7 group
183-176
Global brightness control data bits 7-0 for OUTG0-OUTG7 group
191-184
Global brightness control data bits 7-0 for OUTB0-OUTB7 group
198-192
Function control data bits 6-0
215-199
User-defined data bits 16-0
238-216
Reserved for TI test
239
Thermal error flag (TEF)
1 = High temperature condition, 0 = Normal temperature condition
247-240
LED short detection (LSD) data for OUTR7-OUTR0
1 = LED is short, 0 = Normal operation
255-248
LSD data for OUTG7-OUTG0
1 = LED is short, 0 = Normal operation
263-256
LSD data for OUTB7-OUTB0
1 = LED is short, 0 = Normal operation
271-264
LED open detection (LOD) data for OUTR7-OUTR0
1 = LED is open or connected to GND, 0 = Normal operation
279-272
LOD data for OUTG7-OUTG0
1 = LED is open or connected to GND, 0 = Normal operation
287-280
LOD data for OUTB7-OUTB0
1 = LED is open or connected to GND, 0 = Normal operation
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TLC5951
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www.ti.com
CONTINUOUS BASE LOD, LSD, AND TEF
The LOD data are updated at the rising edge of the 33rd GSCKR/G/B pulse after XBLNK goes high; LOD/LSD
data are retained until the next 33rd GSCKR/G/B. LOD/LSD data are only checked for outputs that are turned on
during the rising edge of the 33rd GSCKR/G/B pulse. A '1' in an LOD bit indicates an open LED or shorted LED
to GND condition for the corresponding output. A '0' indicates normal operation. It is possible for LOD/LSD data
to show a '0' even if the LED is open when the grayscale data are less than 20h (32d).
The TEF bit indicates that the IC temperature is too high. The TEF flag also indicates that the IC has turned off
all drivers to avoid damage by overheating the device. A '1' in the TEF bit means that the IC temperature has
exceeded the detect temperature threshold (TTEF) and all outputs are turned off. A '0' in the TEF bit indicates
normal operation with normal temperature conditions.
The IC automatically turns the drivers back on when the IC temperature decreases to less than (TTEF – THYST).
When the IC is powered on, LOD/LSD data do not show correct values. Therefore LOD/LSD data must be read
from the 33rd GSCKR/G/B pulse input after XBLNK goes high. Table 15 shows a truth table for LOD/LSD and
TEF.
Table 15. LOD/LSD/TEF Truth Table
CONDITION
SID DATA
LED OPEN DETECTION (LODn)
LED SHORT DETECTION (LSDn)
THERMAL ERROR FLAG (TEF)
0
LED is not opened
(VOUTRn/Gn/Bn > VLOD)
LED is not shorted
(VOUTRn/Gn/Bn ≤ VLSD)
Device temperature is lower than
high-side detect temperature
(Temperature ≤TTEF)
1
LED is open or shorted to GND
(VOUTRn/Gn/Bn ≤ VLOD)
LED is shorted between anode and
cathode or shorted to higher voltage side
(VOUTRn/Gn/Bn > VLSD)
Device temperature is higher than
high-side detect temperature and driver is
forced off
(Temperature > TTEF)
XBLNK
(1)
1 2 3 4
GSCKR
GSCKG
GSCKB
30 31 32 33 34 35
4094 4096
4093 4095
1 2 3
30 31 32 33 34 35
1st GSCLK Period
OFF
OUTRn/Gn/Bn
(Data = FFFh)
ON
VOUTRn/Gn/Bn
GND
LOD/LSD Data Latch
(Internal)
Old LOD/LSD Data
If the OUTRn/Gn/Bn voltage (VOUTRn/Gn/Bn) is less than VLOD (0.25 V, typ) at the rising edge of the 33rd
GSCKR/G/B after the rising edge of XBLNK or internal blank, the LOD sets the SID bit corresponding
to the output equal to ‘1’.
Also, if the OUTRn/Gn/Bn voltage is greater than than VLSD (2.5 V, typ) at the rising edge of the 33rd
GSCKR/G/B after the falling edge of XBLNK or internal blank, the LSD sets the SID bit equal to ‘1’.
New LOD/LSD Data
(1) The internal blank signal is generated when GSLAT is input for GS data with display timing reset enabled. Also, the signal is generated at
the 4096th GSCK when auto repeat mode is enabled. XBLNK can be connected to VCC when the display timing reset or auto repeat is
enabled.
Figure 48. LED Open Detection (LOD) LED Shorted Detection Data Update Timing
34
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TLC5951
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SBVS127B – MARCH 2009 – REVISED DECEMBER 2009
THERMAL SHUTDOWN AND THERMAL ERROR FLAG
The thermal shutdown (TSD) function turns off all constant-current outputs on the IC when the junction
temperature (TJ) exceeds the threshold (TTEF = +163°C, typ) and sets the thermal error flag (TEF) to '1'. All
outputs are latched off when TEF is set to '1' and remain off until the next grayscale cycle after XBLNK goes high
and the junction temperature drops below (TTEF – THYST). TEF remains as '1' until GSLAT is input with low
temperature. TEF is set to '0' once the junction temperature drops below (TTEF – THYST), but the output does not
turn on until the first GSCKR/G/B in the next display period even if TEF is set to '0'.
GSLAT
GSCK
Grayscale
Data Latch
XBLNK
Old Latched GS Data
New Latched GS Data
(1)
4094 4096
4093 4095
1 2 3 4
1 2 3
GSCKR/G/B
IC Junction
Temperature (TJ)
TJ < T(TEF)
TJ ³ T(TEF)
TJ < T(TEF) - T(HYS)
TJ ³ T(TEF)
The TEF bit of SID is rest to ‘0’ at the rising edge of GSSCK
after the falling edge of GSLAT for a GS data write.
'1'
TEF in SID
(Internal Data)
'0'
'0'
OUTRn/Gn/Bn is forced off when TJ exceeds T(TEF).
Also, the TEF bit is set to ‘1’ at the same time.
OFF
OUTRn/Gn/Bn
OFF
ON
ON
OUTRn/Gn/Bn is turned off at the rising edge of GSCKR/G/B
after the rising edge of XBLNK.
(1) The following internal signal also works to turn the constant outputs on as same as XBLNK inputting. The internal blank signal is
generated when GSLAT is input for GS data with display timing reset enabled. Also, the signal is generated at the 4096th GSCKR/G/B when
auto repeat mode is enabled. XBLNK can be connected to VCC when the display timing reset or auto repeat is enabled.
Figure 49. TEF/TSD Timing
NOISE REDUCTION
Large surge currents may flow through the IC and the board on which the device is mounted if all 24 outputs turn
on simultaneously at the start of each grayscale cycle. These large current surges could induce detrimental noise
and electromagnetic interference (EMI) into other circuits. The TLC5951 turns the outputs on in a series delay for
each group independently to provide a circuit soft-start feature. The output current sinks are grouped into four
groups in each color group. For example, for the RED color output, the first grouped outputs that are turned
on/off are OUTR0 and OUTR4. The second grouped outputs that are turned on/off are OUTR1 and OUTR5. The
third grouped outputs are OUTR2 and OUTR6 and the fourth grouped outputs are OUTR3 and OUTR7. Each
grouped output is turned on and off sequentially with a small delay between groups. However, each color output
on and off is controlled by the color grayscale clock.
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TLC5951
SBVS127B – MARCH 2009 – REVISED DECEMBER 2009
www.ti.com
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (April 2009) to Revision B
Page
•
Changed product status from mixed to production data ....................................................................................................... 1
•
Changed TLC5951 RHA package status to production data ............................................................................................... 2
•
Deleted footnote 2 from Ordering Information table ............................................................................................................. 2
•
Changed test conditions of tD8 in Switching Characteristics table ........................................................................................ 6
•
Deleted footnote 1 from RHA pinout ..................................................................................................................................... 8
•
Changed header for second column in Table 10 ............................................................................................................... 30
•
Changed description for bits 175-168, 183-176, and 191-184 in Table 14 ........................................................................ 33
Changes from Original (March 2009) to Revision A
Page
•
Changed TSU3 minimum specification to 40 ns in the Recommended Operating Conditions table ...................................... 3
•
Changed VO minimum specification to maximum specification in the Recommended Operating Conditions table ............. 3
•
Changed IOH minimum specification to maximum specification in the Recommended Operating Conditions table ............ 3
•
Changed IOL minimum specification to maximum specification in the Recommended Operating Conditions table ............. 3
•
Changed IOLC minimum specification to maximum specification in the Recommended Operating Conditions table ........... 3
•
Changed fCLK (SCLK) minimum specification to maximum specification in the Recommended Operating Conditions
table ...................................................................................................................................................................................... 3
•
Changed fCLK (GSCKR/G/B) minimum specification to maximum specification in the Recommended Operating Conditions
table ...................................................................................................................................................................................... 3
•
Changed ICC2 typical value to 6 mA in the Electrical Characteristics table ........................................................................... 4
•
Changed ICC3 typical value to 12 mA and maximum value to 27 mA in the Electrical Characteristics table ........................ 4
•
Changed ICC4 typical value to 21 mA and maximum value to 55 mA in the Electrical Characteristics table ........................ 4
•
Changed ΔIOLC2 typical value to ±1% in the Electrical Characteristics table ........................................................................ 4
•
Changed ΔIOLC3 typical value to ±0.5% in the Electrical Characteristics table ..................................................................... 4
•
Changed tR0 typical value to 6 ns in the Switching Characteristics table ............................................................................. 6
•
Changed tF0 typical value to 6 ns in the Switching Characteristics table ............................................................................. 6
•
Changed fourth paragraph of Maximum Constant Sink Current Value section to reference correct graph ....................... 21
•
Changed DC function adjustment range description to reflect proper adjustment range for each control in Dot
Correction (DC) Function section ....................................................................................................................................... 21
•
Changed brightness control to dot correction data in 288-Bit Common Shift Register section .......................................... 28
•
Corrected number of bits contained within the DC/BC/FC/UD shift register in the DC/BC/FC/UD Shift Register
section ................................................................................................................................................................................. 29
•
Corrected typo about which bits are written in the DC/BC/FC/UD Data Latch section ...................................................... 29
•
Corrected percentage of adjustment rage selected in the Dot Correction Data Latch section .......................................... 29
•
Deleted second paragraph of Status Information Data (SID) section ................................................................................ 32
•
Updated LOD bit = '1' condition description in the Continuous Base LOD, LSD, and TEF section ................................... 34
36
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PACKAGE OPTION ADDENDUM
www.ti.com
23-Dec-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TLC5951DAP
ACTIVE
HTSSOP
DAP
38
TLC5951DAPR
ACTIVE
HTSSOP
DAP
TLC5951RHAR
ACTIVE
VQFN
TLC5951RHAT
ACTIVE
VQFN
40
Lead/Ball Finish
MSL Peak Temp (3)
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
38
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
RHA
40
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
RHA
40
250
CU NIPDAU
Level-3-260C-168 HR
Green (RoHS &
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TLC5951RHAR
VQFN
RHA
40
2500
330.0
16.4
6.3
6.3
1.1
12.0
16.0
Q2
TLC5951RHAT
VQFN
RHA
40
250
180.0
16.4
6.3
6.3
1.1
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLC5951RHAR
VQFN
RHA
40
2500
367.0
367.0
38.0
TLC5951RHAT
VQFN
RHA
40
250
210.0
185.0
35.0
Pack Materials-Page 2
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