EON EN71NS128B0

EN71NS128B0
EN71NS128B0 Base MCP
Stacked Multi-Chip Product (MCP) Flash Memory and RAM
128 Megabit (8M x 16-bit) CMOS 1.8 Volt-only Simultaneous
Operation Burst Mode Flash Memory and
32 Megabit (2M x 16-bit) Pseudo Static RAM
Distinctive Characteristics
MCP Features
■ Power supply voltage of 1.7V to 1.95V
■ High performance
- 70 ns @ random access
- 7 ns @ burst access (108MHz)
■ Operating Temperature
- 25°C to +85°C
■ Package
- 6.2 x 7.7 x 1.0mm 56 ball BGA
General Description
The EN71NS series is a product line of stacked Multi-Chip Product (MCP) packages and consists of:
■
■
E29NS128 (Burst mode) Flash memory die.
Pseudo SRAM.
For detailed specifications, Please refer to the individual datasheets listed in the following table.
Device
Document
NOR Flash
EN29NS128
Pseudo SRAM
ENPSS32
Product Selector Guide
128 Mb Flash Memories
Device-Model#
EN71NS128B0
pSRAM density
32M pSRAM
Flash Access time
70ns at Async. Mode
7ns at Burst Read
pSRAM Access time
70ns at Async. Mode
7ns at Burst Read
pSRAM Burst mode
max frequency
108MHz
pSRAM Burst mode
108MHz
max frequency
Package
56-ball BGA
This Data Sheet may be revised by subsequent versions
1
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc.,
Rev. C, Issue Date: 2010/08/20
www.eonssi.com
EN71NS128B0
MCP Block Diagram
NOR FLASH + PSRAM DIAGRAM
Note: Amax = A22
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
2
©2004 Eon Silicon Solution, Inc.,
Rev. C, Issue Date: 2010/08/20
www.eonssi.com
EN71NS128B0
Connection Diagram
MCP
Flash-only Addresses
Shared Addresses
Shared ADQ Pins
EN71NS128B0
A22 – A21
A20 – A16
ADQ15 – ADQ0
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
3
©2004 Eon Silicon Solution, Inc.,
Rev. C, Issue Date: 2010/08/20
www.eonssi.com
EN71NS128B0
Pin Description
Symbol
A22–A16
ADQ15–ADQ0
OE#
WE#
VSSQ/VSS
VCCQ/VCC
NC
Description
Flash
pSRAM
Address Inputs
Multiplexed Address/Data
Output Enable input. Asynchronous relative to CLK for the
Burst mode.
Write Enable input.
Ground
Device Power Supply (1.7 V–1.95 V).
Not Contact; pin not connected internally
Ready output; indicates the status of the Burst read.
Flash Memory RDY (using default “Active HIGH”
configuration)
VOL = data invalid,
VOH = data valid.
Note: The default polarity for the pSRAM WAIT signal is
opposite the default polarity of the Flash RDY signal.
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
RDYf/WAITp
CLK
AVD#
RESET# f
WP#f
ACCf
CE# p
CE# f
CREp
LB#p
UB#p
RFU
pSRAM WAIT (using default “Active HIGH” configuration)
VOL = data valid,
VOH = data invalid.
To match polarities, change bit 10 of the pSRAM Bus
Configruation Register to 0 (Active LOW WAIT). Alternately,
change bit 10 of the Flash Configuration Register to 0 (Active
LOW RDY)
Clock input. In burst mode, after the initial word is output,
subsequent active edges of CLK increment the internal
address counter. Should be at VOL or VIH while in
asynchronous mode.
Address Valid input. Indicates to device that the valid address
is present on the address inputs.
VIL = for asynchronous mode, indicates valid address; for
burst mode, causes starting address to be latched on rising
edge of CLK.
VIH = device ignores address inputs
Hardware reset input. VIL = device resets and returns to
reading array data
Hardware write protect input. VIL = disables program and
erase functions in the four outermost sectors. Should be at VIH
for all other conditions.
Accelerated input. At VHH, accelerates programming;
automatically places device in Accelerated Program mode. At
VIL, disables all program and erase functions. Should be at VIH
for all other conditions. (Applying high voltage on MCP
package is prohibited; otherwise, internal RAM may be
damaged easily!)
Chip Enable Input for pSRAM.
Chip Enable Input for Flash. Asynchronous relative to CLK for
the Burst mode.
Control register enable (pSRAM).
Lower byte enable. DQ7~DQ0 (pSRAM)
Upper byte enable. DQ15~DQ8 (pSRAM)
Reserved for Future Use
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
4
©2004 Eon Silicon Solution, Inc.,
Rev. C, Issue Date: 2010/08/20
●
●
●
●
●
●
●
●
www.eonssi.com
EN71NS128B0
Operating Mode (For Asynchronous mode)
Asynchronous Mode
BCR[15]=1
Power
Read
Active
X
L
L
H
L
L
Low-z
Data out
Write
Active
X
L
X
L
L
L
High-z
Data in
Standby
Standby
H or L
X
H
X
X
L
X
High-z
High-z
No operation
Idle
X
X
L
X
X
L
X
Low-z
X
Configuration register
write
Active
X
L
H
L
H
X
Low-z
High-z
Configuration register
read
Active
X
L
L
H
H
L
Low-z
Config.
Reg.out
CLK ADV# CE# OE# WE# CRE
UB#/
WAIT2 A/DQ[15:0]
LB#
Operating Mode (For Synchronous Burst mode)
Burst Mode
BCR[15]=0
Power
Async read
Active
H or L
L
L
H
L
L
Low-z
Data out
Async write
Active
H or L
L
X
L
L
L
High-z
Data in
Standby
Standby
H or L
X
H
X
X
L
X
High-z
High-z
No operation
Idle
H or L
X
L
X
X
L
X
Low-z
X
Initial burst read
Active
L
L
X
H
L
L
Low-z
Address
Initial burst write
Active
L
L
H
L
L
X
Low-z
Address
Burst continue
Active
H
L
X
X
X
L
Low-z
Data out
or
Data in
Configuration register
write
Active
L
L
H
L
H
X
Low
High-z
Configuration register
read
Active
L
L
L
H
H
L
Low
Config.
Reg.out
CLK ADV# CE# OE# WE# CRE
UB#/
WAIT
LB#
A/DQ[15:0]
Note: X=don’t care. H=logic high. L=logic low. V= Valid data
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
5
©2004 Eon Silicon Solution, Inc.,
Rev. C, Issue Date: 2010/08/20
www.eonssi.com
EN71NS128B0
ORDERING INFORMATION
EN71NS
128
B0 -
7
DC
W
P
PACKAGING CONTENT
P = RoHS compliant
TEMPERATURE RANGE
W = Wireless (-25°C to +85°C)
PACKAGE
DC = 56-Ball BGA
0.50mm pitch, 6.2mm x 7.7mm package
BURST READ ACCESS TIME
7 = 108 MHz
Pseudo SRAM density
B0 = 32Mb
DENSITY
128 = 128Megabit (8M x 16 Bit)
BASE PART NUMBER
EN = Eon Silicon Solution Inc.
71NS = Multi-chip Product (MCP)
1.8V Simultaneous Read/Write,
Burst-mode Multiplexed Flash and RAM
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
6
©2004 Eon Silicon Solution, Inc.,
Rev. C, Issue Date: 2010/08/20
www.eonssi.com
EN71NS128B0
PACKAGE MECHANICAL
56-ball Ball Grid Array (BGA) 6.2 x 7.7 x 1.0mm Package, pitch: 0.5mm, ball: 0.3mm
SYMBOL
DIMENSION IN MM
MIN.
NOR
MAX
A
---
---
1.00
A1
0.16
---
0.26
0.676
A2
D
6.10
6.20
6.30
E
7.60
7.70
7.80
D1
4.5 BSC
E1
6.5 BSC
e
0.5 BSC
b
0.27
--Note : 1. Coplanarity: 0.1 mm
0.37
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
7
©2004 Eon Silicon Solution, Inc.,
Rev. C, Issue Date: 2010/08/20
www.eonssi.com
EN71NS128B0
Revisions List
Revision No
Description
A
Initial Release
2009/07/24
Update the package size and ball assignment from "8 x 9.2mm 56 ball
2009/12/01
FBGA" to "8 x 6mm 52 ball BGA".
Change the package option from 52 ball BGA to 56 ball BGA and
2010/08/20
related information.
B
C
Date
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
8
©2004 Eon Silicon Solution, Inc.,
Rev. C, Issue Date: 2010/08/20
www.eonssi.com