PRELIMINARY Integrated Circuit Systems, Inc. ICS85314-01 LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS85314-01 is a low skew, high performance 1-to-5 Differential-to-3.3V LVPECL fanout buffer HiPerClockS™ and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS85314-01 has two selectable clock inputs. The CLK0, nCLK0 pair can accept most standard differential input levels. The single-ended CLK1 can accept LVCMOS or LVTTL input levels. The clock enable is internally synchronized to eliminate runt clock pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. • 5 differential 2.5V/3.3V LVPECL outputs ,&6 • Selectable differential CLK0, nCLK0 or LVCMOS inputs • CLK0, nCLK0 pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • CLK1 can accept the following input levels: LVCMOS or LVTTL • Maximum output frequency: 650MHz • Translates any single-ended input signal to 3.3V LVPECL levels with resistor bias on nCLK input Guaranteed output and part-to-part skew characteristics make the ICS85314-01 ideal for those applications demanding well defined performance and repeatability. • Output skew: 50ps (maximum) • Part-to-part skew: 400ps (maximum) • Propagation delay: CLK0, nCLK0 - 2.1ns (maximum) CLK1 - 2.1ns (maximum) • LVPECL mode operating voltage supply range: VCC = 2.375V to 3.8V, VEE = 0V • -40°C to 85°C ambient operating temperature • Compatible to part number MC100LVEL14 BLOCK DIAGRAM PIN ASSIGNMENT Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 Q4 nQ4 D nCLK_EN Q LE CLK0 nCLK0 CLK1 00 1 Q0 nQ0 1 Q1 nQ1 CLK_SEL Q2 nQ2 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC nCLK_EN VCC nc CLK1 CLK0 nCLK0 nc CLK_SEL VEE ICS85314-01 Q3 nQ3 20-Lead TSSOP 6.5mm x 4.4mm x 0.92mm Package Body G Package Top View Q4 nQ4 ICS85314-01 20-Lead SOIC 7.5mm x 12.8mm x 2.3mm Package Body M Package Top View The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 85314AG-01 www.icst.com/products/hiperclocks.html 1 REV. B JUNE 21, 2002 PRELIMINARY Integrated Circuit Systems, Inc. ICS85314-01 LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name 1, 2 Q0, nQ0 Type Description Output Differential output pair. LVPECL interface levels. 3, 4 Q1, nQ1 Output Differential output pair. LVPECL interface levels. 5, 6 Q2, nQ2 Output Differential output pair. LVPECL interface levels. 7, 8 Q3, nQ3 Output Differential output pair. LVPECL interface levels. 9, 10 Q4, nQ4 Output Differential output pair. LVPECL interface levels. 11 VEE Power 12 CLK_SEL Input 13, 17 nc Unused 14 nCLK0 Input 15 CLK0 Input Pulldown Non-inver ting differential clock input. 16 CLK1 Input Pulldown Clock input. LVTTL / LVCMOS interface levels. 18, 20 VCC Power Negative supply pin. Clock select input. When HIGH, selects SCLK input. Pulldown When LOW, selects CLK, nCLK inputs. LVTTL / LVCMOS interface levels. No connect. Pullup Inver ting differential clock input. Positive supply pins. Synchronizing clock enable. When LOW, clock outputs follow clock 19 nCLK_EN Input Pulldown input. When HIGH, Q outputs are forced low, nQ outputs are forced high. LVTTL / LVCMOS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance RPULLUP Input Pullup Resistor 51 KΩ RPULLDOWN Input Pulldown Resistor 51 KΩ 85314AG-01 4 www.icst.com/products/hiperclocks.html 2 pF REV. B JUNE 21, 2002 PRELIMINARY Integrated Circuit Systems, Inc. ICS85314-01 LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER TABLE 3A. CONTROL INPUT FUNCTION TABLE Inputs Outputs nCLK_EN CLK_SEL Selected Source Q0:Q4 nQ0:nQ4 0 0 CLK0, nCLK0 Enabled Enabled 0 1 CLK1 Enabled Enabled 1 0 CLK0, nCLK0 Disabled; LOW Disabled; HIGH 1 1 CLK1 Disabled; LOW Disabled; HIGH After nCLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the CLK0, nCLK0 and CLK1 inputs as described in Table 3B. Enabled Disabled nCLK0 CLK0, CLK1 nCLK_EN nQ0:nQ4 Q0:Q4 FIGURE 1 - nCLK_EN TIMING DIAGRAM TABLE 3B. CLOCK INPUT FUNCTION TABLE Inputs Outputs CLK0 or CLK1 nCLK0 Q0:Q4 nQ0:nQ4 0 1 LOW HIGH Input to Output Mode Polarity Differential to Differential Non Inver ting 1 0 HIGH LOW Differential to Differential Non Inver ting 0 Biased; NOTE 1 LOW HIGH Single Ended to Differential Non Inver ting 1 Biased; NOTE 1 HIGH LOW Single Ended to Differential Non Inver ting Biased; NOTE 1 0 HIGH LOW Single Ended to Differential Inver ting Biased; NOTE 1 1 LOW HIGH Single Ended to Differential Inver ting NOTE 1: Please refer to the Application Information, "Wiring the Differential Input to Accept Single Ended Levels". 85314AG-01 www.icst.com/products/hiperclocks.html 3 REV. B JUNE 21, 2002 PRELIMINARY Integrated Circuit Systems, Inc. ICS85314-01 LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCCx 4.6V Inputs, VI Outputs, VO Package Thermal Impedance, θJA Storage Temperature, TSTG -0.5V to VCC + 0.5V -0.5V to VCC + 0.5V 73.2°C/W (0 lfpm) -65°C to 150°C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0V, TA = -40°C TO 85°C Symbol Parameter Test Conditions VCC Power Supply Voltage IEE Power Supply Current Minimum Typical Maximum 2.375 3.3 3.8 55 Units V mA TABLE 4B. LVCMOS / LVTTL CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0V, TA = -40°C TO 85°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current Maximum Units nCLK_EN, CLK_SEL Test Conditions Minimum 2 Typical VCC + 0.3 V CLK1 2 VCC + 0.3 V nCLK_EN, CLK_SEL -0.3 0.8 V CLK1 CLK1, CLK_SEL, nCLK_EN CLK1, CLK_SEL, nCLK_EN -0.3 1.3 V 150 µA VIN = VCC = 3.8V VCC = 3.8V, VIN = 0V -5 µA TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0V, TA = -40°C TO 85°C Symbol Parameter IIH Input High Current IIL Input Low Current Test Conditions Minimum Typical Units nCLK0 VCC = VIN = 3.8V 5 µA CLK0 VCC = VIN = 3.8V 150 µA nCLK0 VCC = 3.8V, VIN = 0V -150 CLK0 VCC = 3.8V, VIN = 0V -5 VPP Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; VCMR 0.5 NOTE 1, 2 NOTE 1: For single ended applications the maximum input voltage for CLK0, nCLK0 is VCC + 0.3V. NOTE 2: Common mode voltage is defined as VIH. 85314AG-01 Maximum www.icst.com/products/hiperclocks.html 4 µA µA 1.3 V VCC - 0.85 V REV. B JUNE 21, 2002 PRELIMINARY Integrated Circuit Systems, Inc. ICS85314-01 LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0V, TA = -40°C TO 85°C Symbol Parameter Maximum Units VOH Output High Voltage; NOTE 1 Test Conditions Minimum VCC - 1.4 Typical VCC - 1.0 V VOL Output Low Voltage; NOTE 1 VCC - 2.0 VCC - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V NOTE 1: Outputs terminated with 50Ω to VCC - 2V. TABLE 5. AC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0V, TA = -40°C TO 85°C Symbol Parameter fMAX Output Frequency tpLH Propagation Delay, Low to High Test Conditions CLK0, nCLK0; NOTE 1 CLK1; NOTE 2 Minimum Typical Maximum Units 650 MHz ƒ≤ 650MHz 1.0 2.1 ns ƒ≤ 250MHz 1.0 2.1 ns t sk(o) Output Skew; NOTE 3, 5 50 ps t sk(pp) Par t-to-Par t Skew; NOTE 4, 5 400 ps tR Output Rise Time 20% to 80% @ 50MHz 200 700 ps tF Output Fall Time 20% to 80% @ 50MHz 200 700 ps odc Output Duty Cycle ƒ≤ 650MHz 45 55 % 55 % CLK0, nCLK0 CLK1 ƒ≤ 250MHz 45 All parameters measured at 250MHz unless noted otherwise. The cycle-to-cycle jitter on the input will equal the jitter on the output. The par t does not add jitter NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Measured from VCC/2 input crossing point to the differential output crossing point. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. 85314AG-01 www.icst.com/products/hiperclocks.html 5 REV. B JUNE 21, 2002 PRELIMINARY Integrated Circuit Systems, Inc. ICS85314-01 LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION VCC SCOPE Qx LVPECL VCC = 2V nQx VEE = -1.8V to -0.375V OUTPUT LOAD TEST CIRCUIT VCC nCLK V PP Cross Points V CMR CLK VEE DIFFERENTIAL INPUT LEVEL 85314AG-01 www.icst.com/products/hiperclocks.html 6 REV. B JUNE 21, 2002 PRELIMINARY Integrated Circuit Systems, Inc. ICS85314-01 LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER nQx Qx nQy Qy tsk(o) OUTPUT SKEW nCLK CLK nQ0:nQ4 Q0:Q4 t PD PROPAGATION DELAY (DIFFERENTIAL INPUT) V CC SCLK 2 nQ0:nQ4 Q0:Q4 t PD PROPAGATION DELAY (LVCMOS INPUT) 85314AG-01 www.icst.com/products/hiperclocks.html 7 REV. B JUNE 21, 2002 PRELIMINARY Integrated Circuit Systems, Inc. ICS85314-01 LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER 80% 80% V SWING 20% 20% Clock Inputs and Outputs t INPUT t R OUTPUT RISE AND AND F FALL TIME nQ0:nQ4 Q0:Q4 Pulse Width t t odc = t PERIOD PW PERIOD odc & tPERIOD 85314AG-01 www.icst.com/products/hiperclocks.html 8 REV. B JUNE 21, 2002 PRELIMINARY Integrated Circuit Systems, Inc. ICS85314-01 LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VCC R1 1K CLK_IN + V_REF - C1 0.1uF R2 1K FIGURE 2 - SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT TERMINATION FOR LVPECL OUTPUTS 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 3.3V Zo = 50Ω 5 2 Zo FOUT Zo = 50Ω Zo = 50Ω FOUT ➤ 1 (VOH + VOL / VCC –2) –2 VCC - 2V Zo = 50Ω RTT 3 2 Zo Zo FIGURE 3A - LVPECL OUTPUT TERMINATION 85314AG-01 FIN 50 Ω 50Ω RTT = 5 2 Zo FIN 3 2 Zo FIGURE 3B - LVPECL OUTPUT TERMINATION www.icst.com/products/hiperclocks.html 9 REV. B JUNE 21, 2002 PRELIMINARY Integrated Circuit Systems, Inc. ICS85314-01 LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS85314-01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS85314-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.8V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 55mA = 209mW Power (outputs)MAX = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 5 * 30.2mW = 151mW Total Power_MAX (3.465V, with all outputs switching) = 209mW + 151mW = 360mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used . Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6A below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.360W * 66.6°C/W = 109°C. This is well below the limit of 125°C This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6A. THERMAL RESISTANCE qJA FOR 20-PIN TSSOP, FORCED CONVECTION qJA by Velocity (Linear Feet per Minute) 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TABLE 6B. THERMAL RESISTANCE qJA FOR 20-PIN SOIC, FORCED CONVECTION qJA by Velocity (Linear Feet per Minute) 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 83.2°C/W 65.7°C/W 57.5°C/W Multi-Layer PCB, JEDEC Standard Test Boards 46.2°C/W 39.7°C/W 36.8°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 85314AG-01 www.icst.com/products/hiperclocks.html 10 REV. B JUNE 21, 2002 PRELIMINARY Integrated Circuit Systems, Inc. ICS85314-01 LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER 3. Calculations and Equations. LVPECL output driver circuit and termination are shown in Figure 4. VCC Q1 VOUT RL 50 VCC - 2V FIGURE 4 - LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CC • For logic high, VOUT = V OH_MAX (V CC_MAX • -V OH_MAX OL_MAX CC_MAX -V OL_MAX CC_MAX – 1.0V ) = 1.0V For logic low, VOUT = V (V =V =V CC_MAX – 1.7V ) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V OH_MAX – (V CC_MAX - 2V))/R ] * (V CC_MAX L -V ) = [(2V - (V OH_MAX CC_MAX -V OH_MAX ))/R ] * (V CC_MAX L -V OH_MAX )= [(2V - 1V)/50Ω] * 1V = 20.0mW Pd_L = [(V OL_MAX – (V CC_MAX - 2V))/R ] * (V L CC_MAX -V OL_MAX ) = [(2V - (V CC_MAX -V OL_MAX ))/R ] * (V L CC_MAX -V OL_MAX )= [(2V - 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW 85314AG-01 www.icst.com/products/hiperclocks.html 11 REV. B JUNE 21, 2002 PRELIMINARY Integrated Circuit Systems, Inc. ICS85314-01 LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER RELIABILITY INFORMATION TABLE 7A. θJAVS. AIR FLOW TABLE FOR TSSOP q by Velocity (Linear Feet per Minute) JA Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 114.5°C/W 73.2°C/W 98.0°C/W 66.6°C/W 88.0°C/W 63.5°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TABLE 7B. θJAVS. AIR FLOW TABLE FOR SOIC q by Velocity (Linear Feet per Minute) JA 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 83.2°C/W 46.2°C/W 200 500 65.7°C/W 39.7°C/W 57.5°C/W 36.8°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS85314-01 is: 674 85314AG-01 www.icst.com/products/hiperclocks.html 12 REV. B JUNE 21, 2002 PRELIMINARY Integrated Circuit Systems, Inc. ICS85314-01 LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER PACKAGE OUTLINE - G SUFFIX TABLE 8A. PACKAGE DIMENSIONS Millimeters SYMBOL Minimum N Maximum 20 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 E E1 6.60 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 85314AG-01 www.icst.com/products/hiperclocks.html 13 REV. B JUNE 21, 2002 PRELIMINARY Integrated Circuit Systems, Inc. ICS85314-01 LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER PACKAGE OUTLINE - M SUFFIX TABLE 8B. PACKAGE DIMENSIONS Millimeters SYMBOL Minimum N A Maximum 20 -- 2.65 A1 0.10 -- A2 2.05 2.55 B 0.33 0.51 C 0.18 0.32 D 12.60 13.00 E 7.40 e H 7.60 1.27 BASIC 10.00 10.65 h 0.25 0.75 L 0.40 1.27 α 0° 8° Reference Document: JEDEC Publication 95, MS-013, MO-119 85314AG-01 www.icst.com/products/hiperclocks.html 14 REV. B JUNE 21, 2002 PRELIMINARY Integrated Circuit Systems, Inc. ICS85314-01 LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS85314AG-01 ICS85314AG01 20 lead TSSOP 72 per tube -40°C to 85°C ICS85314AG-01T ICS85314AG01 20 lead TSSOP on Tape and Reel 2500 -40°C to 85°C ICS85314AM-01 ICS85314AM01 20 lead SOIC 38 per tube -40°C to 85°C ICS85314AM-01T ICS85314AM01 20 lead SOIC on Tape and Reel 1000 -40°C to 85°C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 85314AG-01 www.icst.com/products/hiperclocks.html 15 REV. B JUNE 21, 2002