SFS9614 Advanced Power MOSFET FEATURES BVDSS = -250 V ν Avalanche Rugged Technology ν Rugged Gate Oxide Technology RDS(on) = 4.0 Ω ν Lower Input Capacitance ν Improved Gate Charge ID = -1.27 A ν Extended Safe Operating Area ν Lower Leakage Current : 10 µA (Max.) @ VDS = -250V TO-220F ν Low RDS(ON) : 3.5 Ω (Typ.) 1 2 3 1.Gate 2. Drain 3. Source Absolute Maximum Ratings Symbol VDSS Characteristic Drain-to-Source Voltage o ID Continuous Drain Current (TC=25 C) Drain Current-Pulsed VGS Gate-to-Source Voltage EAS Single Pulsed Avalanche Energy IAR Avalanche Current EAR Repetitive Avalanche Energy dv/dt Peak Diode Recovery dv/dt TJ , TSTG TL V A -0.95 O1 O O1 O1 O3 2 -5.0 + _ 30 A 110 mJ -1.27 A V 1.3 mJ -4.8 V/ns Total Power Dissipation (TC=25 C) 13 W Linear Derating Factor 0.1 W/ C o PD Units -250 -1.27 o Continuous Drain Current (TC=100 C) IDM Value Operating Junction and o - 55 to +150 Storage Temperature Range o Maximum Lead Temp. for Soldering C 300 Purposes, 1/8” from case for 5-seconds Thermal Resistance Symbol Characteristic Typ. Max. Units RθJC Junction-to-Case -- 9.62 o RθJA Junction-to-Ambient -- 62.5 C/W Rev. B1 2001 Fairchild Semiconductor Corporation P-CHANNEL POWER MOSFET SFS9614 Electrical Characteristics (TC=25oC unless otherwise specified) Symbol Characteristic BVDSS Drain-Source Breakdown Voltage ∆BV/∆TJ VGS(th) IGSS IDSS RDS(on) Min. Typ. Max. Units Breakdown Voltage Temp. Coeff. Gate Threshold Voltage Gate-Source Leakage , Forward Gate-Source Leakage , Reverse Drain-to-Source Leakage Current Static Drain-Source On-State Resistance -250 -- -- -- -0.21 -- -2.0 -- -4.0 -- -- -100 V nA See Fig 7 VDS=-5V,ID=-250µA VGS=-30V VGS=30V -- 100 -- -10 -- -- -100 -- -- 4.0 Ω VGS=-10V,ID=-0.6A 4 O S VDS=-40V,ID=-0.6A 4 O -- 0.9 -- Ciss Input Capacitance -- 225 295 Coss Output Capacitance -- 35 55 Crss Reverse Transfer Capacitance -- 13 20 td(on) Turn-On Delay Time -- 10 30 Rise Time -- 18 45 Turn-Off Delay Time -- 24 60 Fall Time -- 11 30 tf V/ C ID=-250µA -- Forward Transconductance td(off) VGS=0V,ID=-250µA o -- gfs tr V Test Condition Qg Total Gate Charge -- 9 11 Qgs Gate-Source Charge -- 2.0 -- Qgd Gate-Drain( “Miller” ) Charge -- 4.6 -- µA pF VDS=-250V o VDS=-200V,TC=125 C VGS=0V,VDS=-25V,f =1MHz See Fig 5 VDD=-125V,ID=-1.6A, ns RG=24Ω See Fig 13 5 4 O O VDS=-200V,VGS=-10V, nC ID=-1.6A See Fig 6 & Fig 12 5 4 O O Source-Drain Diode Ratings and Characteristics Symbol Characteristic IS Continuous Source Current Min. Typ. Max. Units O1 4 O Test Condition -- -- -1.27 -- -- -5.0 -- -- -4.0 V TJ=25 C,IS=-1.27A,VGS=0V A Integral reverse pn-diode ISM Pulsed-Source Current VSD Diode Forward Voltage trr Reverse Recovery Time -- 130 -- ns TJ=25 C,IF=-1.6A Qrr Reverse Recovery Charge -- 0.61 -- µC diF/dt=100A/µs Notes ; 1 Repetitive Rating : Pulse Width Limited by Maximum Junction Temperature O 2 O L=110mH, IAS=-1.27A, VDD=-50V, RG=27Ω*, Starting TJ o=25oC O3 ISD <_-1.6A, di/dt <_ 250A/µs, VDD_< BVDSS , Starting TJ =25 C _ 2% 4 Pulse Test : Pulse Width = 250µs, Duty Cycle < O Essentially Independent of Operating Temperature 5 O in the MOSFET o o 4 O P-CHANNEL POWER MOSFET SFS9614 Fig 1. Output Characteristics Fig 2. Transfer Characteristics VGS -15 V -10 V -8.0 V -7.0 V -6.0 V -5.5 V -5.0 V Bottom : -4.5 V -I D , Drain Current 0 10 [A] 0 -1 10 @ Notes : 1. 250 µs Pulse Test o 2. TC = 25 C -I D , Drain Current [A] Top : -2 o 150 C 10 0 VGS = -10 V 6 4 VGS = -20 V o @ Note : TJ = 25 C 0 1 2 3 4 -ID , Drain Current 5 6 00 10 Capacitance [pF] 10 [V] 0 o 150 C -1 10 o 25 C @ Notes : 1. VGS = 0 V 2. 250 µs Pulse Test -2 10 0.5 [A] 1.0 1.5 2.0 2.5 3.0 -VSD , Source-Drain Voltage 3.5 4.0 [V] Fig 6. Gate Charge vs. Gate-Source Voltage C iss Ciss= Cgs+ Cgd ( Cds= shorted ) Coss= Cds+ Cgd Crss= Cgd C oss @ Notes : 1. VGS = 0 V 2. f = 1 MHz C rss 101 -VDS , Drain-Source Voltage [V] [V] 12 -V GS , Gate-Source Voltage 100 8 10 Fig 5. Capacitance vs. Drain-Source Voltage 200 6 Fig 4. Source-Drain Diode Forward Voltage 400 300 4 -VGS , Gate-Source Voltage 10 0 2 [V] Fig 3. On-Resistance vs. Drain Current 2 @ Notes : 1. VGS = 0 V 2. VDS = -40 V 3. 250 µs Pulse Test -2 1 12 8 25 C o 10 -VDS , Drain-Source Voltage o [A] 10 -I DR , Reverse Drain Current -1 10 -1 - 55 C 10 10 R DS(on) , [ Ω] Drain-Source On-Resistance 10 VDS = -50 V 10 VDS = -125 V VDS = -200 V 8 6 4 2 @ Notes : ID = -1.6 A 0 0 2 4 6 QG , Total Gate Charge 8 [nC] 10 P-CHANNEL POWER MOSFET SFS9614 Fig 7. Breakdown Voltage vs. Temperature Fig 8. On-Resistance vs. Temperature RDS(on) , (Normalized) Drain-Source On-Resistance 2.5 2.0 1.5 1.0 @ Notes : 1. VGS = -10 V 2. ID = -0.8 A 0.5 0.0 -75 -50 -25 0 25 50 75 100 TJ , Junction Temperature Fig 9. Max. Safe Operating Area 125 150 175 o [ C] Fig 10. Max. Drain Current vs. Case Temperature Operation in This Area is Limited by R DS(on) -ID , Drain Current [A] 101 0.1 ms 1 ms 100 10 ms DC 10-1 @ Notes : 1. TC = 25 oC 2. TJ = 150 oC 3. Single Pulse 10-2 0 10 101 1.2 0.8 0.4 0.0 25 102 50 75 100 Tc , Case Temperature [oC] -VDS , Drain-Source Voltage [V] Thermal Response Fig 11. Thermal Response θ JC Z (t) , -ID , Drain Current [A] 1.6 101 D=0.5 @ Notes : 1. Zθ J C (t)=9.62 o C/W Max. 2. Duty Factor, D=t1 /t2 3. TJ M -TC =PD M *Zθ J C (t) 0.2 100 0.1 P.DM 0.05 t1. t2. 0.02 0.01 10- 1 - 5 10 single pulse 10- 4 10- 3 10- 2 10- 1 t 1 , Square Wave Pulse Duration 100 [sec] 101 125 150 P-CHANNEL POWER MOSFET SFS9614 Fig 12. Gate Charge Test Circuit & Waveform “ Current Regulator ” VGS Same Type as DUT 50KΩ Qg 200nF 12V -10V 300nF VDS Qgs VGS Qgd DUT -3mA R1 R2 Current Sampling (IG) Resistor Current Sampling (ID) Resistor Charge Fig 13. Resistive Switching Test Circuit & Waveforms RL t on Vout td(on) VDD Vin ( 0.5 rated VDS ) RG Vin t off tr td(off) tf 10% DUT -10V Vout 90% Fig 14. Unclamped Inductive Switching Test Circuit & Waveforms BVDSS 1 EAS = ---- LL IAS2 -------------------2 BVDSS -- VDD LL VDS Vary tp to obtain required peak ID tp ID VDD RG C VDD -10V IAS tp VDS (t) ID (t) DUT BVDSS Time P-CHANNEL POWER MOSFET SFS9614 Fig 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms + VDS DUT -IS L Driver VGS RG VGS VGS ( Driver ) Compliment of DUT (N-Channel) VDD • dv/dt controlled by “RG” • IS controlled by Duty Factor “D” Gate Pulse Width D = -------------------------Gate Pulse Period 10V Body Diode Reverse Current IRM IS ( DUT ) di/dt IFM , Body Diode Forward Current Vf VDS ( DUT ) Body Diode Forward Voltage Drop Body Diode Recovery dv/dt VDD TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H4