$GYDQFHG 3RZHU 026)(7 IRLR/U130A FEATURES BVDSS = 100 V ♦ Avalanche Rugged Technology ♦ Rugged Gate Oxide Technology RDS(on) = 0.12Ω ♦ Lower Input Capacitance ♦ Improved Gate Charge ID = 13 A ♦ Extended Safe Operating Area ♦ Lower Leakage Current: 10µA (Max.) @ VDS = 100V D-PAK ♦ Lower RDS(ON): 0.101Ω (Typ.) I-PAK 2 1 1 3 2 3 1. Gate 2. Drain 3. Source Absolute Maximum Ratings Symbol VDSS ID Characteristic Drain-to-Source Voltage 100 Continuous Drain Current (TC=25°C) 13 Continuous Drain Current (TC=100°C) 8 IDM Drain Current-Pulsed VGS Gate-to-Source Voltage EAS Single Pulsed Avalanche Energy IAR Avalanche Current EAR dv/dt PD Value TL V A 45 A ±20 V (2) 225 mJ (1) 13 A Repetitive Avalanche Energy (1) 4.6 mJ Peak Diode Recovery dv/dt (3) (1) 6.5 V/ns Total Power Dissipation (TA=25°C) * 2.5 W Total Power Dissipation (TC=25°C) 46 W 0.37 W/°C Linear Derating Factor TJ , TSTG Units Operating Junction and - 55 to +150 Storage Temperature Range °C Maximum Lead Temp. for Soldering Purposes, 1/8 300 from case for 5-seconds Thermal Resistance Symbol Characteristic Typ. Max. RθJC Junction-to-Case -- 2.7 RθJA Junction-to-Ambient * -- 50 RθJA Junction-to-Ambient -- 110 Units °C/W * When mounted on the minimum pad size recommended (PCB Mount). Rev. B ©1999 Fairchild Semiconductor Corporation 1 1&+$11(/ 32:(5 026)(7 IRLR/U130A Electrical Characteristics (TC=25°C unless otherwise specified) Symbol Characteristic Min. Typ. Max. Units BVDSS Drain-Source Breakdown Voltage 100 -- -- ∆BV/∆TJ Breakdown Voltage Temp. Coeff. -- 0.1 -- IGSS IDSS RDS(on) Gate Threshold Voltage 1.0 -- 2.0 Gate-Source Leakage , Forward -- -- 100 Gate-Source Leakage , Reverse -- -- -100 -- -- 10 Drain-to-Source Leakage Current Static Drain-Source On-State Resistance µA VGS=20V VGS=-20V VDS=100V VDS=80V,TC=150°C 100 -- -- 0.12 Ω VGS=5V,ID=6.5A (4) VDS=40V,ID=6.5A (4) -- 10.1 -- Ciss Input Capacitance -- 580 755 Coss Output Capacitance -- 140 175 Crss Reverse Transfer Capacitance -- 60 75 td(on) Turn-On Delay Time -- 10 30 Rise Time -- 11 30 Turn-Off Delay Time -- 29 70 Fall Time -- 15 40 Qg Total Gate Charge -- 16.9 24 Qgs Gate-Source Charge -- 2.7 -- Qgd Gate-Drain ( Miller ) Charge -- 9.7 -- tf nA VDS=5V,ID=250µA -- Forward Transconductance td(off) V See Fig 7 -- gfs tr V/°C ID=250µA Ω VGS(th) V Test Condition VGS=0V,ID=250µA pF VGS=0V,VDS=25V,f =1MHz See Fig 5 VDD=50V,ID=14A, ns RG=6Ω See Fig 13 (4) (5) VDS=80V,VGS=5V, nC ID=14A See Fig 6 & Fig 12 (4) (5) Source-Drain Diode Ratings and Characteristics Symbol Characteristic Min. Typ. Max. Units Test Condition IS Continuous Source Current -- -- 13 ISM Pulsed-Source Current (1) -- -- 45 VSD Diode Forward Voltage (4) -- -- 1.5 V TJ=25°C,IS=13A,VGS=0V trr Reverse Recovery Time -- 109 -- ns TJ=25°C,IF=14A Qrr Reverse Recovery Charge -- 0.41 -- µC diF/dt=100A/µs A Integral reverse pn-diode in the MOSFET (4) Notes; (1) Repetitive Rating: Pulse Width Limited by Maximum Junction Temperature (2) L=2mH, IAS=13A, VDD=25V, RG=27Ω, Starting TJ =25°C (3) ISD ≤ 14A, di/dt ≤ 350A/µs, VDD ≤ BV DSS , Starting TJ =25°C (4) Pulse Test: Pulse Width = 250µs, Duty Cycle ≤ 2% (5) Essentially Independent of Operating Temperature 2 1&+$11(/ 32:(5 026)(7 IRLR/U130A Fig 1. Output Characteristics Fig 2. Transfer Characteristics 102 V GS Top : 7.0V 6.0 V ID , Drain Current [A] ID , Drain Current [A] 5.5 V 5.0 V 4.5 V 4.0 V 101 3.5 V Bottom : 3.0V @ Notes : 1. 250 µs Pulse Test 2. TC = 25 oC 100 10-1 100 101 150 oC 100 25 oC @ Notes : 1. VGS = 0 V 2. VDS = 40 V 3. 250 µs Pulse Test - 55 oC 10-1 101 0 2 VDS , Drain-Source Voltage [V] 4 6 8 10 VGS , Gate-Source Voltage [V] Fig 3. On-Resistance vs. Drain Current Fig 4. Source-Drain Diode Forward Voltage IDR , Reverse Drain Current [A] VGS = 5 V 0.15 0.10 VGS = 10 V 0.05 o @ Note : TJ = 25 C 0.00 0 15 30 45 60 101 100 @ Notes : 1. VGS = 0 V 2. 250 µs Pulse Test 150 oC 25 oC 10-1 0.4 0.6 0.8 I , Drain Current [A] 1.0 1.2 1.4 1.6 1.8 2.0 2.2 VSD , Source-Drain Voltage [V] D Fig 5. Capacitance vs. Drain-Source Voltage Fig 6. Gate Charge vs. Gate-Source Voltage 1000 C iss Ciss= Cgs+ Cgd ( Cds= shorted ) Coss= Cds+ Cgd Crss= Cgd 600 C oss 400 @ Notes : 1. VGS = 0 V 2. f = 1 MHz C rss 200 0 100 1 10 VDS , Drain-Source Voltage [V] 6 V = 20 V VGS , Gate-Source Voltage [V] 800 Capacitance [pF] RDS(on) , [ Ω ] Drain-Source On-Resistance 0.20 DS VDS = 50 V VDS = 80 V 4 2 @ Notes : ID = 14 A 0 0 3 6 9 12 Q , Total Gate Charge [nC] G 15 18 1&+$11(/ 32:(5 026)(7 IRLR/U130A Fig 7. Breakdown Voltage vs. Temperature Fig 8. On-Resistance vs. Temperature 2.5 RDS(on) , (Normalized) 1.1 1.0 0.9 @ Notes : 1. VGS = 0 V Drain-Source On-Resistance BVDSS , (Normalized) Drain-Source Breakdown Voltage 1.2 2.0 1.5 1.0 @ Notes : 1. VGS = 5 V 0.5 2. ID = 250 µA 0.8 -75 -50 -25 0 25 50 75 100 125 150 2. ID = 7 A 0.0 -75 175 -50 -25 TJ , Junction Temperature [oC] Fig 9. Max. Safe Operating Area 75 100 125 150 175 15 ID , Drain Current [A] 1 ms 101 10 ms DC 10 50 Fig 10. Max. Drain Current vs. Case Temperature 100 µs 0 25 Operation in This Area is Limited by R DS(on) @ Notes : 1. TC = 25 oC 2. TJ = 150 oC 3. Single Pulse 10-1 0 10 12 9 6 3 101 0 25 102 50 75 100 T , Case Temperature [oC] VDS , Drain-Source Voltage [V] c Thermal Response Fig 11. Thermal Response D=0.5 100 0.2 10- 1 0.1 @ Notes : 1. Z J C (t)=2.7 o C/W Max. 0.05 2. Duty Factor, D=t1 /t2 0.02 3. TJ M -TC =PD M *Z θ θJC single pulse 10- 2 - 5 10 (t) PDM 0.01 t1 θJC Z (t) , ID , Drain Current [A] 102 0 TJ , Junction Temperature [oC] t2 10- 4 t 1 10- 3 10- 2 10- 1 , Square Wave Pulse Duration 100 [sec] 101 125 150 1&+$11(/ 32:(5 026)(7 IRLR/U130A Fig 12. Gate Charge Test Circuit & Waveform Current Regulator VGS Same Type as DUT 50kΩ Qg 200nF 12V 10V 300nF VDS Qgs VGS Qgd DUT 3mA R1 R2 Current Sampling (IG) Resistor Charge Current Sampling (ID) Resistor Fig 13. Resistive Switching Test Circuit & Waveforms RL Vout Vout 90% VDD Vin ( 0.5 rated VDS ) RG DUT Vin 10% 5V tr td(on) td(off) t on tf t off Fig 14. Unclamped Inductive Switching Test Circuit & Waveforms BVDSS 1 EAS = ---- LL IAS2 -------------------2 BVDSS -- VDD LL VDS Vary tp to obtain required peak ID BVDSS IAS ID RG C DUT ID (t) VDD VDS (t) VDD 5V tp tp Time 5 1&+$11(/ 32:(5 026)(7 IRLR/U130A Fig 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms DUT + VDS -- IS L Driver VGS RG VGS VGS ( Driver ) Same Type as DUT VDD dv/dt controlled by RG IS controlled by Duty Factor D Gate Pulse Width D = -------------------------Gate Pulse Period 5V IFM , Body Diode Forward Current IS ( DUT ) di/dt IRM Body Diode Reverse Current VDS ( DUT ) Body Diode Recovery dv/dt Vf VDD Body Diode Forward Voltage Drop 6 DPAK Package Dimensions DPAK (FS PKG CODE AA) 0.89 ±0.10 MIN0.55 0.91 ±0.10 0.50 ±0.10 9.50 ±0.30 0.76 ±0.10 0.50 ±0.10 1.02 ±0.20 2.30TYP [2.30±0.20] (1.00) (3.05) (2XR0.25) (0.10) 6.60 ±0.20 (5.34) (5.04) (1.50) (0.70) 2.30 ±0.20 (0.90) 2.70 ±0.20 2.30 ±0.10 2.70 ±0.20 2.30TYP [2.30±0.20] (0.50) 6.10 ±0.20 MAX0.96 (4.34) 9.50 ±0.30 0.80 ±0.20 0.60 ±0.20 (0.50) 6.10 ±0.20 5.34 ±0.30 0.70 ±0.20 6.60 ±0.20 0.76 ±0.10 Dimensions in Millimeters September 1999, Rev B IPAK Package Dimensions IPAK (FS PKG CODE AL) 2.30 ±0.20 6.60 ±0.20 5.34 ±0.20 0.76 ±0.10 2.30TYP [2.30±0.20] 0.50 ±0.10 16.10 ±0.30 6.10 ±0.20 0.70 ±0.20 (0.50) 9.30 ±0.30 MAX0.96 (4.34) 1.80 ±0.20 0.80 ±0.10 0.60 ±0.20 (0.50) 2.30TYP [2.30±0.20] 0.50 ±0.10 Dimensions in Millimeters September 1999, Rev B TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. HiSeC™ ISOPLANAR™ MICROWIRE™ POP™ PowerTrench QFET™ QS™ Quiet Series™ SuperSOT™-3 SuperSOT™-6 ACEx™ Bottomless™ CoolFET™ CROSSVOLT™ E2CMOSTM FACT™ FACT Quiet Series™ FAST FASTr™ GTO™ SuperSOT™-8 SyncFET™ TinyLogic™ UHC™ VCX™ DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. E