LMC6062 www.ti.com SNOS631D – NOVEMBER 1994 – REVISED MARCH 2013 LMC6062 Precision CMOS Dual Micropower Operational Amplifier Check for Samples: LMC6062 FEATURES DESCRIPTION • • • • • • The LMC6062 is a precision dual low offset voltage, micropower operational amplifier, capable of precision single supply operation. Performance characteristics include ultra low input bias current, high voltage gain, rail-to-rail output swing, and an input common mode voltage range that includes ground. These features, plus its low power consumption, make the LMC6062 ideally suited for battery powered applications. 1 2 • • • (Typical Unless Otherwise Noted) Low Offset Voltage 100μV Ultra Low Supply current 16μA/Amplifier Operates from 4.5V to 15V Single Supply Ultra Low Input Bias Current 10fA Output Swing within 10mV of Supply Rail, 100k Load Input Common-Mode Range Includes V− High Voltage Gain 140dB Improved Latchup Immunity APPLICATIONS • • • • • • • Instrumentation Amplifier Photodiode and Infrared Detector Preamplifier Transducer Amplifiers Hand-Held Analytic Instruments Medical Instrumentation D/A Converter Charge Amplifier for Piezoelectric Transducers Other applications using the LMC6062 include precision full-wave rectifiers, integrators, references, sample-and-hold circuits, and true instrumentation amplifiers. This device is built with TI's advanced double-Poly Silicon-Gate CMOS process. For designs that require higher speed, see the LMC6082 precision dual operational amplifier. PATENT PENDING Connection Diagram Figure 1. 8-Pin PDIP/SOIC Top View 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1994–2013, Texas Instruments Incorporated LMC6062 SNOS631D – NOVEMBER 1994 – REVISED MARCH 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Absolute Maximum Ratings (1) (2) Differential Input Voltage ±Supply Voltage (V+) +0.3V, Voltage at Input/Output Pin (V−) −0.3V − + Supply Voltage (V − V ) 16V Output Short Circuit to V+ See (3) Output Short Circuit to V− See (4) Lead Temperature (Soldering, 10 sec.) 260°C Storage Temp. Range −65°C to +150°C Junction Temperature 150°C ESD Tolerance (5) 2 kV Current at Input Pin ±10 mA Current at Output Pin ±30 mA Current at Power Supply Pin 40 mA Power Dissipation See (1) (2) (3) (4) (5) (6) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications Do not connect output to V+, when V+ is greater than 13V or reliability witll be adversely affected. Applies to both single-supply and split-supply operation. Continuos short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of ±30 mA over long term may adversely affect reliability. Human body model, 1.5 kΩ in series with 100 pF. The maximum power dissipation is a function of TJ(Max), θJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(Max) − TA)/θJA. Operating Ratings (1) Temperature Range −55°C ≤ TJ ≤ +125°C LMC6062AM −40°C ≤ TJ ≤ +85°C LMC6062AI, LMC6082I 4.5V ≤ V+ ≤ 15.5V Supply Voltage Thermal Resistance (θJA) (2) 8-Pin PDIP 115°C/W 8-Pin SOIC 193°C/W Power Dissipation (1) (2) (3) (6) See (3) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. All numbers apply for packages soldered directly into a PC board. For operating at elevated temperatures the device must be derated based on the thermal resistance θJA with PD = (TJ–TA)/θJA. DC Electrical Characteristics (1) Unless otherwise specified, all limits ensured for TJ = 25°C. Boldface limits apply at the temperature extremes. V+ = 5V, V− = 0V, VCM = 1.5V, VO = 2.5V and RL > 1M unless otherwise specified. Symbol VOS (1) (2) (3) 2 Parameter Input Offset Voltage Conditions Typ (2) 100 LMC6062AM LMC6062AI LMC6062I Limit (3) Limit (3) 350 350 800 μV 1200 900 1300 Max Limit (3) Units For ensured Military Temperature Range parameters, see RETSMC6062X. Typical values represent the most likely parametric norm. All limits are ensured by testing or statistical analysis. Submit Documentation Feedback Copyright © 1994–2013, Texas Instruments Incorporated Product Folder Links: LMC6062 LMC6062 www.ti.com SNOS631D – NOVEMBER 1994 – REVISED MARCH 2013 DC Electrical Characteristics(1) (continued) Unless otherwise specified, all limits ensured for TJ = 25°C. Boldface limits apply at the temperature extremes. V+ = 5V, V− = 0V, VCM = 1.5V, VO = 2.5V and RL > 1M unless otherwise specified. Symbol TCVOS Parameter Conditions Input Offset Voltage Typ (2) LMC6062AM Limit (3) LMC6062AI LMC6062I Limit (3) Limit (3) Units μV/°C 1.0 Average Drift IB Input Bias Current IOS 0.010 Input Offset Current Input Resistance CMRR Common Mode 0V ≤ VCM ≤ 12.0V Rejection Ratio V+ = 15V Positive Power Supply 5V ≤ V+ ≤ 15V Rejection Ratio VO = 2.5V Negative Power Supply 0V ≤ V− ≤ −10V −PSRR AV 85 Voltage Range for CMRR ≥ 60 dB RL = 100 kΩ (4) RL = 25 kΩ 2 Max pA Tera Ω 66 dB 72 63 Min 75 75 66 dB 70 72 63 Min 84 84 74 dB 70 81 71 Min −0.4 −0.1 −0.1 −0.1 V 0 0 0 Max V+ − 1.9 V+ − 2.3 V+ − 2.3 V+ − 2.3 V V+ − 2.6 V+ − 2.5 V+ − 2.5 Min Sourcing 400 400 300 V/mV 200 300 200 Min 90 V/mV 4000 (4) Sinking 3000 180 180 70 100 60 Min Sourcing 3000 400 400 200 V/mV 150 150 80 Min Sinking 2000 100 100 70 V/mV 35 50 35 Min 4.995 4.990 4.990 4.950 V 4.970 4.980 4.925 Min 0.010 0.010 0.050 V 0.030 0.020 0.075 Max 4.975 4.975 4.950 V 4.955 4.965 4.850 Min 0.020 0.020 0.050 V 0.045 0.035 0.150 Max 14.975 14.975 14.950 V 14.955 14.965 14.925 Min 0.025 0.025 0.050 V 0.050 0.035 0.075 Max 14.900 14.900 14.850 V 14.800 14.850 14.800 Min 0.050 0.050 0.100 V 0.200 0.150 0.200 Max V+ = 5V RL = 100 kΩ to 2.5V 0.005 V+ = 5V 4.990 RL = 25 kΩ to 2.5V 0.010 V+ = 15V 14.990 RL = 100 kΩ to 7.5V 0.010 V+ = 15V 14.965 RL = 25 kΩ to 7.5V 0.025 (4) 2 75 100 V+ = 5V and 15V Output Swing 100 70 Voltage Gain VO Max 75 85 Input Common-Mode Large Signal 4 >10 Rejection Ratio VCM 4 0.005 RIN +PSRR pA 100 V+ = 15V, VCM = 7.5V and RL connected to 7.5V. For Sourcing tests, 7.5V ≤ VO ≤ 11.5V. For Sinking tests, 2.5V ≤ VO ≤ 7.5V. Submit Documentation Feedback Copyright © 1994–2013, Texas Instruments Incorporated Product Folder Links: LMC6062 3 LMC6062 SNOS631D – NOVEMBER 1994 – REVISED MARCH 2013 www.ti.com DC Electrical Characteristics(1) (continued) Unless otherwise specified, all limits ensured for TJ = 25°C. Boldface limits apply at the temperature extremes. V+ = 5V, V− = 0V, VCM = 1.5V, VO = 2.5V and RL > 1M unless otherwise specified. Symbol IO Parameter Output Current Conditions Sourcing, VO = 0V LMC6062AI LMC6062I Limit (3) Limit (3) Limit (3) 16 16 13 mA 8 10 8 Min 16 16 16 mA 7 8 8 Min 15 15 15 mA 9 10 10 Min 35 20 20 20 mA 7 8 8 Min 32 38 38 46 μA 60 46 56 Max 47 47 57 μA 70 55 66 Max Typ (2) 22 V+ = 5V Sinking, VO = 5V IO Output Current 21 Sourcing, VO = 0V 25 V+ = 15V Sinking, VO = 13V IS Supply Current (5) Both Amplifiers V+ = +5V, VO = 1.5V Both Amplifiers 40 V+ = +15V, VO = 7.5V (5) LMC6062AM Units Do not connect output to V+, when V+ is greater than 13V or reliability will be adversely affected. AC Electrical Characteristics (1) Unless otherwise specified, all limits ensured for TJ = 25°C, Boldface limits apply at the temperature extremes. V+ = 5V, V− = 0V, VCM = 1.5V, VO = 2.5V and RL > 1M unless otherwise specified. Symbol SR Parameter Slew Rate Conditions See (4) Typ (2) 35 LMC6062AM LMC6062AI LMC6062I Limit (3) Units Limit (3) Limit (3) 20 20 15 V/ms 8 10 7 Min GBW Gain-Bandwidth Product 100 kHz θm Phase Margin 50 Deg 155 dB (5) Amp-to-Amp Isolation See en Input-Referred Voltage Noise F = 1 kHz 83 nV/√Hz in Input-Referred Current Noise F = 1 kHz 0.0002 pA/√Hz T.H.D. Total Harmonic Distortion F = 1 kHz, AV = −5 0.01 % RL = 100 kΩ, VO = 2 VPP ±5V Supply (1) (2) (3) (4) (5) 4 For ensured Military Temperature Range parameters, see RETSMC6062X. Typical values represent the most likely parametric norm. All limits are ensured by testing or statistical analysis. V+ = 15V. Connected as Voltage Follower with 10V step input. Number specified is the slower of the positive and negative slew rates. Input referred V+ = 15V and RL = 100 kΩ connected to 7.5V. Each amp excited in turn with 100 Hz to produce VO = 12 VPP. Submit Documentation Feedback Copyright © 1994–2013, Texas Instruments Incorporated Product Folder Links: LMC6062 LMC6062 www.ti.com SNOS631D – NOVEMBER 1994 – REVISED MARCH 2013 Typical Performance Characteristics VS = ±7.5V, TA = 25°C, Unless otherwise specified Distribution of LMC6062 Input Offset Voltage (TA = +25°C) Distribution of LMC6062 Input Offset Voltage (TA = −55°C) Figure 2. Figure 3. Distribution of LMC6062 Input Offset Voltage (TA = +125°C) Input Bias Current vs. Temperature Figure 4. Figure 5. Supply Current vs. Supply Voltage Input Voltage vs. Output Voltage Figure 6. Figure 7. Submit Documentation Feedback Copyright © 1994–2013, Texas Instruments Incorporated Product Folder Links: LMC6062 5 LMC6062 SNOS631D – NOVEMBER 1994 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) VS = ±7.5V, TA = 25°C, Unless otherwise specified 6 Common Mode Rejection Ratio vs. Frequency Power Supply Rejection Ratio vs. Frequency Figure 8. Figure 9. Input Voltage Noise vs. Frequency Output Characteristics Sourcing Current Figure 10. Figure 11. Output Characteristics Sinking Current Gain and Phase Response vs. Temperature (−55°C to +125°C) Figure 12. Figure 13. Submit Documentation Feedback Copyright © 1994–2013, Texas Instruments Incorporated Product Folder Links: LMC6062 LMC6062 www.ti.com SNOS631D – NOVEMBER 1994 – REVISED MARCH 2013 Typical Performance Characteristics (continued) VS = ±7.5V, TA = 25°C, Unless otherwise specified Gain and Phase Response vs. Capacitive Load with RL = 20 kΩ Gain and Phase Response vs. Capacitive Load with RL = 500 kΩ Figure 14. Figure 15. Open Loop Frequency Response Inverting Small Signal Pulse Response Figure 16. Figure 17. Inverting Large Signal Pulse Response Non-Inverting Small Signal Pulse Response Figure 18. Figure 19. Submit Documentation Feedback Copyright © 1994–2013, Texas Instruments Incorporated Product Folder Links: LMC6062 7 LMC6062 SNOS631D – NOVEMBER 1994 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) VS = ±7.5V, TA = 25°C, Unless otherwise specified 8 Non-Inverting Large Signal Pulse Response Crosstalk Rejection vs. Frequency Figure 20. Figure 21. Stability vs Capacitive Load, RL = 20 kΩ Stability vs. Capacitive Load RL = 1 MΩ Figure 22. Figure 23. Submit Documentation Feedback Copyright © 1994–2013, Texas Instruments Incorporated Product Folder Links: LMC6062 LMC6062 www.ti.com SNOS631D – NOVEMBER 1994 – REVISED MARCH 2013 APPLICATIONS HINTS AMPLIFIER TOPOLOGY The LMC6062 incorporates a novel op-amp design topology that enables it to maintain rail-to-rail output swing even when driving a large load. Instead of relying on a push-pull unity gain output buffer stage, the output stage is taken directly from the internal integrator, which provides both low output impedance and large gain. Special feed forward compensation design techniques are incorporated to maintain stability over a wider range of operating conditions than traditional micropower op amps. These features make the LMC6062 both easier to design with, and provide higher speed than products typically found in this ultra low power class. COMPENSATING FOR INPUT CAPACITANCE It is quite common to use large values of feedback resistance for amplifiers with ultra-low input current, like the LMC6062. Although the LMC6062 is highly stable over a wide range of operating conditions, certain precautions must be met to achieve the desired pulse response when a large feedback resistor is used. Large feedback resistors and even small values of input capacitance, due to transducers, photodiodes, and circuit board parasitics, reduce phase margins. When high input impedances are demanded, guarding of the LMC6062 is suggested. Guarding input lines will not only reduce leakage, but lowers stray input capacitance as well. (See PRINTED-CIRCUIT-BOARD LAYOUT FOR HIGH-IMPEDANCE WORK). The effect of input capacitance can be compensated for by adding a capacitor. Place a capacitor, Cf, around the feedback resistor (as in Figure 24 ) such that: (1) or R1 CIN ≤ R2 Cf (2) Since it is often difficult to know the exact value of CIN, Cf can be experimentally adjusted so that the desired pulse response is achieved. Refer to the LMC660 and the LMC662 for a more detailed discussion on compensating for input capacitance. Figure 24. Canceling the Effect of Input Capacitance CAPACITIVE LOAD TOLERANCE All rail-to-rail output swing operational amplifiers have voltage gain in the output stage. A compensation capacitor is normally included in this integrator stage. The frequency location of the dominate pole is affected by the resistive load on the amplifier. Capacitive load driving capability can be optimized by using an appropriate resistive load in parallel with the capacitive load (see typical curves). Direct capacitive loading will reduce the phase margin of many op-amps. A pole in the feedback loop is created by the combination of the op-amp's output impedance and the capacitive load. This pole induces phase lag at the unity-gain crossover frequency of the amplifier resulting in either an oscillatory or underdamped pulse response. With a few external components, op amps can easily indirectly drive capacitive loads, as shown in Figure 25. Submit Documentation Feedback Copyright © 1994–2013, Texas Instruments Incorporated Product Folder Links: LMC6062 9 LMC6062 SNOS631D – NOVEMBER 1994 – REVISED MARCH 2013 www.ti.com Figure 25. LMC6062 Noninverting Gain of 10 Amplifier, Compensated to Handle Capacitive Loads In the circuit of Figure 25, R1 and C1 serve to counteract the loss of phase margin by feeding the high frequency component of the output signal back to the amplifier's inverting input, thereby preserving phase margin in the overall feedback loop. Capacitive load driving capability is enhanced by using a pull up resistor to V+ (Figure 26). Typically a pull up resistor conducting 10 μA or more will significantly improve capacitive load responses. The value of the pull up resistor must be determined based on the current sinking capability of the amplifier with respect to the desired output swing. Open loop gain of the amplifier can also be affected by the pull up resistor (see Electrical Characteristics). Figure 26. Compensating for Large Capacitive Loads with a Pull Up Resistor PRINTED-CIRCUIT-BOARD LAYOUT FOR HIGH-IMPEDANCE WORK It is generally recognized that any circuit which must operate with less than 1000 pA of leakage current requires special layout of the PC board. When one wishes to take advantage of the ultra-low bias current of the LMC6062, typically less than 10 fA, it is essential to have an excellent layout. Fortunately, the techniques of obtaining low leakages are quite simple. First, the user must not ignore the surface leakage of the PC board, even though it may sometimes appear acceptably low, because under conditions of high humidity or dust or contamination, the surface leakage will be appreciable. To minimize the effect of any surface leakage, lay out a ring of foil completely surrounding the LMC6062's inputs and the terminals of capacitors, diodes, conductors, resistors, relay terminals etc. connected to the op-amp's inputs, as in Figure 27. To have a significant effect, guard rings should be placed on both the top and bottom of the PC board. This PC foil must then be connected to a voltage which is at the same voltage as the amplifier inputs, since no leakage current can flow between two points at the same potential. For example, a PC board trace-to-pad resistance of 1012Ω, which is normally considered a very large resistance, could leak 5 pA if the trace were a 5V bus adjacent to the pad of the input. This would cause a 100 times degradation from the LMC6062's actual performance. However, if a guard ring is held within 5 mV of the inputs, then even a resistance of 1011Ω would cause only 0.05 pA of leakage current. See Figure 28 for typical connections of guard rings for standard op-amp configurations. 10 Submit Documentation Feedback Copyright © 1994–2013, Texas Instruments Incorporated Product Folder Links: LMC6062 LMC6062 www.ti.com SNOS631D – NOVEMBER 1994 – REVISED MARCH 2013 Figure 27. Example of Guard Ring in P.C. Board Layout (a) Inverting Amplifier (b) Non-Inverting Amplifier (c) Follower Figure 28. Typical Connections of Guard Rings The designer should be aware that when it is inappropriate to lay out a PC board for the sake of just a few circuits, there is another technique which is even better than a guard ring on a PC board: Don't insert the amplifier's input pin into the board at all, but bend it up in the air and use only air as an insulator. Air is an excellent insulator. In this case you may have to forego some of the advantages of PC board construction, but the advantages are sometimes well worth the effort of using point-to-point up-in-the-air wiring. See Figure 29. Latchup CMOS devices tend to be susceptible to latchup due to their internal parasitic SCR effects. The (I/O) input and output pins look similar to the gate of the SCR. There is a minimum current required to trigger the SCR gate lead. The LMC6062 and LMC6082 are designed to withstand 100 mA surge current on the I/O pins. Some resistive method should be used to isolate any capacitance from supplying excess current to the I/O pins. In addition, like an SCR, there is a minimum holding current for any latchup mode. Limiting current to the supply pins will also inhibit latchup susceptibility. Submit Documentation Feedback Copyright © 1994–2013, Texas Instruments Incorporated Product Folder Links: LMC6062 11 LMC6062 SNOS631D – NOVEMBER 1994 – REVISED MARCH 2013 www.ti.com (Input pins are lifted out of PC board and soldered directly to components. All other pins connected to PC board). Figure 29. Air Wiring Typical Single-Supply Applications (V+ = 5.0 VDC) The extremely high input impedance, and low power consumption, of the LMC6062 make it ideal for applications that require battery-powered instrumentation amplifiers. Examples of these types of applications are hand-held pH probes, analytic medical instruments, magnetic field detectors, gas detectors, and silicon based pressure transducers. Figure 30 shows an instrumentation amplifier that features high differential and common mode input resistance (>1014Ω), 0.01% gain accuracy at AV = 100, excellent CMRR with 1 kΩ imbalance in bridge source resistance. Input current is less than 100 fA and offset drift is less than 2.5 μV/°C. R2 provides a simple means of adjusting gain over a wide range without degrading CMRR. R7 is an initial trim used to maximize CMRR without using super precision matched resistors. For good CMRR over temperature, low drift resistors should be used. If R1 = R5, R3 = R6, and R4 = R7; then ∴AV ≈ 100 for circuit shown (R2 = 9.822k). Figure 30. Instrumentation Amplifier 12 Submit Documentation Feedback Copyright © 1994–2013, Texas Instruments Incorporated Product Folder Links: LMC6062 LMC6062 www.ti.com SNOS631D – NOVEMBER 1994 – REVISED MARCH 2013 Figure 31. Low-Leakage Sample and Hold Figure 32. 1 Hz Square Wave Oscillator Submit Documentation Feedback Copyright © 1994–2013, Texas Instruments Incorporated Product Folder Links: LMC6062 13 LMC6062 SNOS631D – NOVEMBER 1994 – REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision C (March 2013) to Revision D • 14 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 13 Submit Documentation Feedback Copyright © 1994–2013, Texas Instruments Incorporated Product Folder Links: LMC6062 PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LMC6062AIM NRND SOIC D 8 95 TBD Call TI Call TI -40 to 85 LMC60 62AIM LMC6062AIM/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) SN | CU SN Level-1-260C-UNLIM -40 to 85 LMC60 62AIM LMC6062AIMX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMC60 62AIM LMC6062IM NRND SOIC D 8 95 TBD Call TI Call TI -40 to 85 LMC60 62IM LMC6062IM/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMC60 62IM LMC6062IMX NRND SOIC D 8 2500 TBD Call TI Call TI -40 to 85 LMC60 62IM LMC6062IMX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) SN | CU SN Level-1-260C-UNLIM -40 to 85 LMC60 62IM LMC6062IN ACTIVE PDIP P 8 40 TBD Call TI Call TI -40 to 85 LMC6062 IN LMC6062IN/NOPB ACTIVE PDIP P 8 40 Green (RoHS & no Sb/Br) CU SN Level-1-NA-UNLIM -40 to 85 LMC6062 IN (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LMC6062AIMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMC6062IMX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMC6062IMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMC6062AIMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMC6062IMX SOIC D 8 2500 367.0 367.0 35.0 LMC6062IMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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