LMP7701, LMP7702, LMP7704 www.ti.com SNOSAI9H – SEPTEMBER 2005 – REVISED MARCH 2013 LMP7701/LMP7702/LMP7704 Precision, CMOS Input, RRIO, Wide Supply Range Amplifiers Check for Samples: LMP7701, LMP7702, LMP7704 FEATURES DESCRIPTION • The LMP7701/LMP7702/LMP7704 are single, dual, and quad low offset voltage, rail-to-rail input and output precision amplifiers each with a CMOS input stage and a wide supply voltage range. The LMP7701/LMP7702/LMP7704 are part of the LMP™ precision amplifier family and are ideal for sensor interface and other instrumentation applications. 1 23 Unless Otherwise Noted, Typical Values at VS = 5V – Input Offset Voltage (LMP7701): ±200 µV (max) – Input Offset Voltage (LMP7702/LMP7704): ±220 µV (max) – Input Bias Current: ±200 fA – Input Bias Current: ±200 fA – Input Voltage Noise: 9 nV/√Hz – CMRR: 130 dB – Open Loop Gain: 130 dB – Temperature Range: −40°C to 125°C – Unity Gain Bandwidth: 2.5 MHz – Supply Current (LMP7701): 715 µA – Supply Current (LMP7702): 1.5 mA – Supply Current (LMP7704): 2.9 mA – Supply Voltage Range: 2.7V to 12V – Rail-to-Rail Input and Output APPLICATIONS • • • • • • High Impedance Sensor Interface Battery Powered Instrumentation High Gain Amplifiers DAC Buffer Instrumentation Amplifier Active Filters The specified low offset voltage of less than ±200 µV along with the specified low input bias current of less than ±1 pA make the LMP7701 ideal for precision applications. The LMP7701/LMP7702/LMP7704 are built utilizing VIP50 technology, which allows the combination of a CMOS input stage and a 12V common mode and supply voltage range. This makes the LMP7701/LMP7702/LMP7704 great choices in many applications where conventional CMOS parts cannot operate under the desired voltage conditions. The LMP7701/LMP7702/LMP7704 each have a railto-rail input stage that significantly reduces the CMRR glitch commonly associated with rail-to-rail input amplifiers. This is achieved by trimming both sides of the complimentary input stage, thereby reducing the difference between the NMOS and PMOS offsets. The output of the LMP7701/LMP7702/LMP7704 swings within 40 mV of either rail to maximize the signal dynamic range in applications requiring low supply voltage. The LMP7701 is offered in the space saving 5-Pin SOT-23 and 8-Pin SOIC package. The LMP7702 is offered in the 8-Pin SOIC and 8-Pin VSSOP package. The quad LMP7704 is offered in the 14-Pin SOIC and 14-Pin TSSOP package. These small packages are ideal solutions for area constrained PC boards and portable electronics. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. LMP is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005–2013, Texas Instruments Incorporated LMP7701, LMP7702, LMP7704 SNOSAI9H – SEPTEMBER 2005 – REVISED MARCH 2013 www.ti.com TYPICAL APPLICATION R R V1 V + - RS I = (V2 ± V1) A1 RS + V - V + Z R LOAD - R V2 A2 + - V Figure 1. Precision Current Source Absolute Maximum Ratings ESD Tolerance (3) (1) (2) Human Body Model 2000V Machine Model 200V Charge-Device Model 1000V VIN Differential ±300 mV Supply Voltage (VS = V+ – V−) 13.2V V++ 0.3V, V− − 0.3V Voltage at Input/Output Pins Input Current 10 mA −65°C to +150°C Storage Temperature Range Junction Temperature (4) Soldering Information (1) (2) (3) (4) 2 +150°C Infrared or Convection (20 sec) 235°C Wave Soldering Lead Temp. (10 sec) 260°C Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test conditions, see the Electrical Characteristics Tables. If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications. Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC) Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC). The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LMP7701 LMP7702 LMP7704 LMP7701, LMP7702, LMP7704 www.ti.com SNOSAI9H – SEPTEMBER 2005 – REVISED MARCH 2013 Operating Ratings Temperature Range (1) (2) −40°C to +125°C Supply Voltage (VS = V+ – V−) 2.7V to 12V Package Thermal Resistance (θJA (2)) (1) (2) 5-Pin SOT-23 265°C/W 8-Pin SOIC 190°C/W 8-Pin VSSOP 235°C/W 14-Pin SOIC 145°C/W 14-Pin TSSOP 122°C/W Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test conditions, see the Electrical Characteristics Tables. The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board. 3V Electrical Characteristics (1) Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = 3V, V− = 0V, VCM = V+/2, and RL > 10 kΩ to V+/2. Boldface limits apply at the temperature extremes. Parameter VOS Test Conditions Input Offset Voltage TCVOS IB Input Offset Voltage Temperature Drift Min (2) (3) ±200 ±500 LMP7702/LMP7704 ±56 ±220 ±520 ±1 ±5 ±0.2 ±1 ±50 ±0.2 ±1 ±400 (4) (4) (5) −40°C ≤ TA ≤ 125°C Input Offset Current CMRR Common Mode Rejection Ratio 86 80 130 0V ≤ VCM ≤ 3V LMP7702/LMP7704 84 78 130 86 82 98 Power Supply Rejection Ratio 2.7V ≤ V+ ≤ 12V, Vo = V+/2 CMVR Common Mode Voltage Range CMRR ≥ 80 dB CMRR ≥ 77 dB –0.2 –0.2 AVOL Open Loop Voltage Gain RL = 2 kΩ (LMP7701) VO = 0.3V to 2.7V 100 96 114 RL = 2 kΩ (LMP7702/LMP7704) VO = 0.3V to 2.7V 100 94 114 RL = 10 kΩ VO = 0.2V to 2.8V 100 96 124 (2) (3) (4) (5) Units μV μV/°C 40 0V ≤ VCM ≤ 3V LMP7701 PSRR (1) (2) ±37 −40°C ≤ TA ≤ 85°C IOS Max LMP7701 (4) (5) Input Bias Current Typ pA fA dB dB 3.2 3.2 V dB Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlations using the Statistical Quality Control (SQC) method. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped production material. This parameter is specified by design and/or characterization and is not tested in production. Positive current corresponds to current flowing into the device. Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LMP7701 LMP7702 LMP7704 Submit Documentation Feedback 3 LMP7701, LMP7702, LMP7704 SNOSAI9H – SEPTEMBER 2005 – REVISED MARCH 2013 www.ti.com 3V Electrical Characteristics (1) (continued) Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = 3V, V− = 0V, VCM = V+/2, and RL > 10 kΩ to V+/2. Boldface limits apply at the temperature extremes. Parameter VOUT Test Conditions Output Voltage Swing High Output Voltage Swing Low IOUT Output Current IS Min + (6) (7) Supply Current (8) (2) Typ (3) Max (2) RL = 2 kΩ to V /2 LMP7701 40 80 120 RL = 2 kΩ to V+/2 LMP7702/LMP7704 40 80 150 RL = 10 kΩ to V+/2 LMP7701 30 40 60 RL = 10 kΩ to V+/2 LMP7702/LMP7704 35 50 100 RL = 2 kΩ to V+/2 LMP7701 40 60 80 RL = 2 kΩ to V+/2 LMP7702/LMP7704 45 100 170 RL = 10 kΩ to V+/2 LMP7701 20 40 50 RL = 10 kΩ to V+/2 LMP7702/LMP7704 20 50 90 Sourcing VO = V+/2 VIN = 100 mV 25 15 42 Sinking VO = V+/2 VIN = −100 mV (LMP7701) 25 20 42 Sinking VO = V+/2 VIN = −100 mV (LMP7702/LMP7704) 25 15 42 Units mV from V+ mV mA LMP7701 0.670 1.0 1.2 LMP7702 1.4 1.8 2.1 LMP7704 2.9 3.5 4.5 AV = +1, VO = 2 VPP 10% to 90% 0.9 V/μs 2.5 MHz 0.02 % mA SR Slew Rate GBW Gain Bandwidth THD+N Total Harmonic Distortion + Noise f = 1 kHz, AV = 1, R.L = 10 kΩ en Input Referred Voltage Noise Density f = 1 kHz 9 nV/√Hz in Input Referred Current Noise Density f = 100 kHz 1 fA/√Hz (6) (7) (8) 4 The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board. The short circuit test is a momentary test. The number specified is the slower of positive and negative slew rates. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LMP7701 LMP7702 LMP7704 LMP7701, LMP7702, LMP7704 www.ti.com SNOSAI9H – SEPTEMBER 2005 – REVISED MARCH 2013 5V Electrical Characteristics (1) Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = 5V, V− = 0V, VCM = V+/2, and RL > 10 kΩ to V+/2. Boldface limits apply at the temperature extremes. Parameter VOS Test Conditions Input Offset Voltage TCVOS IB Input Offset Voltage Temperature Drift Min (2) (3) ±200 ±500 LMP7702/LMP7704 ±32 ±220 ±520 ±1 ±5 ±0.2 ±1 ±50 ±0.2 ±1 ±400 (4) (4) (5) −40°C ≤ TA ≤ 125°C Input Offset Current CMRR Common Mode Rejection Ratio 88 83 130 0V ≤ VCM ≤ 5V LMP7702/LMP7704 86 81 130 86 82 100 Power Supply Rejection Ratio 2.7V ≤ V+ ≤ 12V, VO = V+/2 CMVR Common Mode Voltage Range CMRR ≥ 80 dB CMRR ≥ 78 dB –0.2 –0.2 AVOL Open Loop Voltage Gain RL = 2 kΩ (LMP7701) VO = 0.3V to 4.7V 100 96 119 RL = 2 kΩ (LMP7702/LMP7704) VO = 0.3V to 4.7V 100 94 119 RL = 10 kΩ VO = 0.2V to 4.8V 100 96 130 Output Voltage Swing High Output Voltage Swing Low (1) (2) (3) (4) (5) Units μV μV/°C pA 40 0V ≤ VCM ≤ 5V LMP7701 PSRR VOUT (2) ±37 −40°C ≤ TA ≤ 85°C IOS Max LMP7701 (4) (5) Input Bias Current Typ fA dB dB 5.2 5.2 V dB RL = 2 kΩ to V+/2 LMP7701 60 110 130 RL = 2 kΩ to V+/2 LMP7702/LMP7704 60 120 200 RL = 10 kΩ to V+/2 LMP7701 40 50 70 RL = 10 kΩ to V+/2 LMP7702/LMP7704 40 60 120 RL = 2 kΩ to V+/2 LMP7701 50 80 90 RL = 2 kΩ to V+/2 LMP7702/LMP7704 50 120 190 RL = 10 kΩ to V+/2 LMP7701 30 40 50 RL = 10 kΩ to V+/2 LMP7702/LMP7704 30 50 100 mV from V+ mV Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlations using the Statistical Quality Control (SQC) method. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. This parameter is specified by design and/or characterization and is not tested in production. Positive current corresponds to current flowing into the device. Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LMP7701 LMP7702 LMP7704 Submit Documentation Feedback 5 LMP7701, LMP7702, LMP7704 SNOSAI9H – SEPTEMBER 2005 – REVISED MARCH 2013 www.ti.com 5V Electrical Characteristics (1) (continued) Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = 5V, V− = 0V, VCM = V+/2, and RL > 10 kΩ to V+/2. Boldface limits apply at the temperature extremes. Parameter IOUT Output Current IS Test Conditions (6) (7) Min + Supply Current (8) (2) Typ Sourcing VO = V /2 VIN = 100 mV (LMP7701) 40 28 66 Sourcing VO = V+/2 VIN = 100 mV (LMP7702/LMP7704) 38 25 66 Sinking VO = V+/2 VIN = −100 mV (LMP7701) 40 28 76 Sinking VO = V+/2 VIN = −100 mV (LMP7702/LMP7704) 40 23 76 (3) Max (2) Units mA LMP7701 0.715 1.0 1.2 LMP7702 1.5 1.9 2.2 LMP7704 2.9 3.7 4.6 AV = +1, VO = 4 VPP 10% to 90% 1.0 0.02 % mA SR Slew Rate GBW Gain Bandwidth THD+N Total Harmonic Distortion + Noise f = 1 kHz, AV = 1, RL = 10 kΩ en Input Referred Voltage Noise Density f = 1 kHz 9 nV/√Hz in Input Referred Current Noise Density f = 100 kHz 1 fA/√Hz (6) (7) (8) V/μs 2.5 MHz The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board. The short circuit test is a momentary test. The number specified is the slower of positive and negative slew rates. ±5V Electrical Characteristics (1) Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = 5V, V− = −5V, VCM = 0V, and RL > 10 kΩ to 0V. Boldface limits apply at the temperature extremes. Parameter VOS Test Conditions Input Offset Voltage TCVOS IB Input Offset Voltage Temperature Drift Input Bias Current Min (2) Typ (3) ±37 ±200 ±500 LMP7702/LMP7704 ±37 ±220 ±520 ±1 ±5 ±0.2 1 ±50 ±0.2 1 ±400 (4) (4) (5) (4) (5) −40°C ≤ TA ≤ 125°C Input Offset Current CMRR Common Mode Rejection Ratio (1) (2) (3) (4) (5) 6 (2) LMP7701 −40°C ≤ TA ≤ 85°C IOS Max 40 −5V ≤ VCM ≤ 5V LMP7701 92 88 138 −5V ≤ VCM ≤ 5V LMP7702/LMP7704 90 86 138 Units μV μV/°C pA fA dB Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlations using the Statistical Quality Control (SQC) method. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. This parameter is specified by design and/or characterization and is not tested in production. Positive current corresponds to current flowing into the device. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LMP7701 LMP7702 LMP7704 LMP7701, LMP7702, LMP7704 www.ti.com SNOSAI9H – SEPTEMBER 2005 – REVISED MARCH 2013 ±5V Electrical Characteristics (1) (continued) Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = 5V, V− = −5V, VCM = 0V, and RL > 10 kΩ to 0V. Boldface limits apply at the temperature extremes. Parameter Test Conditions + Min (2) Typ (3) PSRR Power Supply Rejection Ratio 2.7V ≤ V ≤ 12V, VO = 0V CMVR Common Mode Voltage Range CMRR ≥ 80 dB CMRR ≥ 78 dB −5.2 −5.2 AVOL Open Loop Voltage Gain RL = 2 kΩ (LMP7701) VO = −4.7V to 4.7V 100 98 121 RL = 2 kΩ (LMP7702/LMP7704) VO = −4.7V to 4.7V 100 94 121 RL = 10 kΩ (LMP7701) VO = −4.8V to 4.8V 100 98 134 RL = 10 kΩ (LMP7702/LMP7704) VO = −4.8V to 4.8V 100 97 134 VOUT Output Voltage Swing High Output Voltage Swing Low IOUT Output Current IS (6) (7) Supply Current (8) 86 82 Max (2) Units 98 dB 5.2 5.2 dB RL = 2 kΩ to 0V LMP7701 90 150 170 RL = 2 kΩ to 0V LMP7702/LMP7704 90 180 290 RL = 10 kΩ to 0V LMP7701 40 80 100 RL = 10 kΩ to 0V LMP7702/LMP7704 40 80 150 RL = 2 kΩ to 0V LMP7701 90 130 150 RL = 2 kΩ to 0V LMP7702/LMP7704 90 180 290 RL = 10 kΩ to 0V LMP7701 40 50 60 RL = 10 kΩ to 0V LMP7702/LMP7704 40 60 110 Sourcing VO = 0V VIN = 100 mV (LMP7701) 50 35 86 Sourcing VO = 0V VIN = 100 mV (LMP7702/LMP7704) 48 33 86 Sinking VO = 0V VIN = −100 mV 50 35 84 V mV from V+ mV from V– mA LMP7701 0.790 1.1 1.3 LMP7702 1.7 2.1 2.5 LMP7704 3.2 4.2 5.0 AV = +1, VO = 9 VPP 10% to 90% 1.1 V/μs 2.5 MHz 0.02 % mA SR Slew Rate GBW Gain Bandwidth THD+N Total Harmonic Distortion + Noise f = 1 kHz, AV = 1, RL = 10 kΩ en Input Referred Voltage Noise Density f = 1 kHz 9 nV/√Hz in Input Referred Current Noise Density f = 100 kHz 1 fA/√Hz (6) (7) (8) The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board. The short circuit test is a momentary test. The number specified is the slower of positive and negative slew rates. Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LMP7701 LMP7702 LMP7704 Submit Documentation Feedback 7 LMP7701, LMP7702, LMP7704 SNOSAI9H – SEPTEMBER 2005 – REVISED MARCH 2013 www.ti.com CONNECTION DIAGRAMS OUT - V 5 1 N/C -IN 2 + IN+ + V - 3 +IN 4 IN- 1 2 3 8 + 4 6 5 V 8 7 N/C + V OUTPUT N/C Figure 2. 5-Pin SOT-23 (LMP7701) Top View Figure 3. 8-Pin SOIC (LMP7701) Top View Figure 4. 8-Pin SOIC/VSSOP (LMP7702) Top View Figure 5. 14-Pin SOIC/TSSOP (LMP7704) Top View Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LMP7701 LMP7702 LMP7704 LMP7701, LMP7702, LMP7704 www.ti.com SNOSAI9H – SEPTEMBER 2005 – REVISED MARCH 2013 Typical Performance Characteristics Unless otherwise noted: TA = 25°C, VCM = VS/2, RL > 10 kΩ. Offset Voltage Distribution TCVOS Distribution 20 25 VS = 3V VS = 3V -40°C d TA d 125°C 16 PERCENTAGE (%) PERCENTAGE (%) 20 TA = 25°C 15 10 12 8 4 5 0 -200 0 -100 0 100 200 -3 -2 -1 0 TCVOS (PV/°C) Figure 6. Figure 7. Offset Voltage Distribution 3 TCVOS Distribution VS = 5V VS = 5V TA = 25°C -40°C d TA d 125°C 16 PERCENTAGE (%) 20 PERCENTAGE (%) 2 20 25 15 10 12 8 4 5 0 -200 0 -100 0 100 OFFSET VOLTAGE (PV) 200 -3 -2 -1 0 1 2 3 TCVOS (PV/°C) Figure 8. Figure 9. Offset Voltage Distribution TCVOS Distribution 20 25 VS = 10V VS = 10V -40°C d TA d 125°C TA = 25°C 16 PERCENTAGE (%) 20 PERCENTAGE (%) 1 OFFSET VOLTAGE (PV) 15 10 8 4 5 0 -200 12 0 -100 0 100 OFFSET VOLTAGE (PV) 200 -3 -2 Figure 10. -1 0 1 2 3 TCVOS (PV/°C) Figure 11. Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LMP7701 LMP7702 LMP7704 Submit Documentation Feedback 9 LMP7701, LMP7702, LMP7704 SNOSAI9H – SEPTEMBER 2005 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise noted: TA = 25°C, VCM = VS/2, RL > 10 kΩ. CMRR vs. Frequency 200 0 150 -20 VS = 3V 100 -40 VS = 3V 50 VS = 5V CMRR (dB) OFFSET VOLTAGE (PV) Offset Voltage vs. Temperature 0 -50 VS = 5V VS = 10V -80 -100 -100 VS = 10V -120 -150 -200 -140 -40 -20 0 20 40 60 80 100 120125 10 Figure 12. Figure 13. Offset Voltage vs. Supply Voltage Offset Voltage vs. VCM 200 200 150 150 1M VS = 3V 100 -40°C 50 0 25°C -50 -100 125°C -40°C 100 50 25°C 0 -50 125°C -100 -150 -200 2 4 6 8 10 -200 -0.5 12 0 0.5 1 1.5 2 2.5 3 3.5 VCM (V) SUPPLY VOLTAGE (V) Figure 14. Figure 15. Offset Voltage vs. VCM Offset Voltage vs. VCM 200 200 VS = 10V VS = 5V 150 150 OFFSET VOLTAGE (PV) OFFSET VOLTAGE (PV) 100k FREQUENCY (Hz) -150 100 -40°C 50 0 25°C -50 -100 125°C -150 100 -40°C 50 0 25°C -50 -100 -150 125°C -200 -200 -1 0 1 2 3 4 5 6 -1 0 1 VCM (V) Submit Documentation Feedback 2 3 4 5 6 7 8 9 10 11 VCM (V) Figure 16. 10 10k 1k 100 TEMPERATURE (°C) OFFSET VOLTAGE (PV) OFFSET VOLTAGE (PV) -60 Figure 17. Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LMP7701 LMP7702 LMP7704 LMP7701, LMP7702, LMP7704 www.ti.com SNOSAI9H – SEPTEMBER 2005 – REVISED MARCH 2013 Typical Performance Characteristics (continued) Unless otherwise noted: TA = 25°C, VCM = VS/2, RL > 10 kΩ. Input Bias Current vs. VCM Input Bias Current vs. VCM 300 200 VS = 3V VS = 3V 200 100 IBIAS (pA) IBIAS (fA) 100 -40°C 0 85°C 0 -100 -100 -200 125°C 25°C -300 -200 0 0.5 1 2 1.5 2.5 0 3 0.5 1.5 1 Figure 18. Figure 19. Input Bias Current vs. VCM Input Bias Current vs. VCM 3 300 300 VS = 5V VS = 5V 200 200 100 100 IBIAS (pA) IBIAS (fA) 2.5 2 VCM (V) VCM (V) -40°C 0 85°C 0 -100 -100 -200 -200 25°C 125°C -300 -300 0 1 2 3 4 1 0 5 2 3 4 5 VCM (V) VCM (V) Figure 20. Figure 21. Input Bias Current vs. VCM Input Bias Current vs. VCM 300 500 VS = 10V VS = 10V 200 250 IBIAS (pA) IBIAS (fA) 100 -40°C 0 85°C 0 -100 -250 -200 25°C 125°C -500 -300 0 2 4 6 8 10 0 VCM (V) 2 4 6 8 10 VCM (V) Figure 22. Figure 23. Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LMP7701 LMP7702 LMP7704 Submit Documentation Feedback 11 LMP7701, LMP7702, LMP7704 SNOSAI9H – SEPTEMBER 2005 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise noted: TA = 25°C, VCM = VS/2, RL > 10 kΩ. PSRR vs. Frequency 120 Supply Current vs. Supply Voltage (Per Channel) 1.2 VS = 10V VS = 5V 1 SUPPLY CURRENT (mA) 100 VS = 3V +PSRR PSRR (dB) 80 VS = 10V 60 VS = 5V VS = 3V 40 20 125°C 25°C 0.8 0.6 -40°C 0.4 0.2 -PSRR 0 0 10 10k 1k 100 100k 1M 2 4 6 8 10 FREQUENCY (Hz) SUPPLY VOLTAGE (V) Figure 24. Figure 25. Sinking Current vs. Supply Voltage 12 Sourcing Current vs. Supply Voltage 120 120 -40°C 100 -40°C 100 25°C 25°C 60 ISOURCE (mA) ISINK (mA) 80 125°C 40 20 80 125°C 60 40 20 0 0 2 4 6 8 10 12 2 TA = -40°C, 25°C, 125C AV = +1 1.4 + (V ) -1 VIN = 2 VPP + (V ) -2 | 2 SLEW RATE (V/Ps) 1.3 3V 12 Slew Rate vs. Supply Voltage 1.5 | 10 Figure 27. + VOUT FROM RAIL (V) 8 Figure 26. Output Voltage vs. Output Current RL = 10 k: FALLING EDGE 1.2 CL = 10 pF 1.1 1 0.9 RISING EDGE 0.8 0.7 1 VS = 3V, 5V, 10V 0.6 0.5 0 20 40 60 80 100 2 OUTPUT CURRENT (mA) Submit Documentation Feedback 4 6 8 10 12 SUPPLY VOLTAGE (V) Figure 28. 12 6 SUPPLY VOLTAGE (V) V 0 4 SUPPLY VOLTAGE (V) Figure 29. Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LMP7701 LMP7702 LMP7704 LMP7701, LMP7702, LMP7704 www.ti.com SNOSAI9H – SEPTEMBER 2005 – REVISED MARCH 2013 Typical Performance Characteristics (continued) Unless otherwise noted: TA = 25°C, VCM = VS/2, RL > 10 kΩ. Open Loop Frequency Response 100 225 GAIN 80 60 180 80 135 60 90 40 CL = 20 pF, 50 pF, 100 pF 180 RL = 10 k: VS = 10V 125°C 45 125°C 0 -40°C -20 VS = 5V -40 0 25°C CL = 20 pF GAIN (dB) 20 25°C PHASE PHASE (°) GAIN (dB) -40°C 40 CL = 20 pF PHASE 20 0 -45 -20 -90 -40 1k -45 VS = 3V -90 CL = 100 pF 10k 100k 1M -135 10M 100M -60 100 1k 10k 100k 1M -135 10M 100M FREQUENCY (Hz) Figure 31. Large Signal Step Response Small Signal Step Response 20 mV/DIV Figure 30. VS = 5V f = 10 kHz VS = 5V f = 10 kHz AV = +1 AV = +1 VIN = 2 VPP VIN = 100 mVPP RL = 10 k: RL = 10 k: CL = 10 pF CL = 10 pF 10 Ps/DIV 10 Ps/DIV Figure 32. Figure 33. Large Signal Step Response Small Signal Step Response 200 mV/DIV 500 mV/DIV 90 0 FREQUENCY (Hz) 1V/DIV 135 45 RL = 10 k: -60 100 225 VS = 3V, 5V, 10V GAIN PHASE (°) Open Loop Frequency Response 100 VS = 5V f = 10 kHz VS = 5V f = 10 kHz AV = +10 AV = +10 VIN = 400 mVPP VIN = 100 mVPP RL = 10 k: RL = 10 k: CL = 10 pF CL = 10 pF 10 Ps/DIV 10 Ps/DIV Figure 34. Figure 35. Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LMP7701 LMP7702 LMP7704 Submit Documentation Feedback 13 LMP7701, LMP7702, LMP7704 SNOSAI9H – SEPTEMBER 2005 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise noted: TA = 25°C, VCM = VS/2, RL > 10 kΩ. Input Voltage Noise vs. Frequency Open Loop Gain vs. Output Voltage Swing 150 VS = 10V 100 80 VS = 3V 60 VS = 5V 40 130 120 RL = 10 k: 110 VS = 3V 100 90 80 20 1 10 RL = 2 k: 70 VS = 10V 0 100 1k 10k 60 500 100k FREQUENCY (Hz) 400 100 0 Output Swing High vs. Supply Voltage Output Swing Low vs. Supply Voltage 50 50 RL = 10 k: 25°C 40 40 125°C 30 VOUT FROM RAIL (mV) VOUT FROM RAIL (mV) 200 Figure 37. RL = 10 k: -40°C 20 10 0 2 4 6 8 10 -40°C 30 25°C 125°C 20 10 0 12 2 6 8 10 SUPPLY VOLTAGE (V) Figure 38. Figure 39. Output Swing High vs. Supply Voltage 12 Output Swing Low vs. Supply Voltage 100 RL = 2 k: RL = 2 k: 25°C 25°C 80 80 VOUT FROM RAIL (mV) 125°C 60 -40°C 40 20 0 4 SUPPLY VOLTAGE (V) 100 VOUT FROM RAIL (mV) 300 OUTPUT SWING FROM RAIL (mV) Figure 36. 14 VS = 5V 140 OPEN LOOP GAIN (dB) INPUT REFERRED VOLTAGE NOISE (nV/ Hz) 120 2 4 6 8 10 12 125°C 60 -40°C 40 20 0 2 4 6 8 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) Figure 40. Figure 41. Submit Documentation Feedback 10 12 Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LMP7701 LMP7702 LMP7704 LMP7701, LMP7702, LMP7704 www.ti.com SNOSAI9H – SEPTEMBER 2005 – REVISED MARCH 2013 Typical Performance Characteristics (continued) Unless otherwise noted: TA = 25°C, VCM = VS/2, RL > 10 kΩ. THD+N vs. Frequency THD+N vs. Output Voltage 1 1 VS = 5V f = 1 kHz VS = 5V VO = 4.5 VPP RL = 100 k: RL = 100 k: 0.1 THD+N (%) 0.1 AV = +10 THD+N (%) AV = +10 0.01 0.01 AV = +1 AV = +1 0.001 10 100 1k 10k 0.001 0.001 100k 0.01 0.1 FREQUENCY (Hz) VOUT (V) Figure 42. Figure 43. 1 10 Crosstalk Rejection Ratio vs. Frequency (LMP7702/LMP7704) 140 CROSSTALK REJECTION (dB) VS = 12V 120 VS = 5V VS = 3V 100 80 60 40 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 44. Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LMP7701 LMP7702 LMP7704 Submit Documentation Feedback 15 LMP7701, LMP7702, LMP7704 SNOSAI9H – SEPTEMBER 2005 – REVISED MARCH 2013 www.ti.com APPLICATION INFORMATION LMP7701/LMP7702/LMP7704 The LMP7701/LMP7702/LMP7704 are single, dual, and quad low offset voltage, rail-to-rail input and output precision amplifiers each with a CMOS input stage and wide supply voltage range of 2.7V to 12V. The LMP7701/LMP7702/LMP7704 have a very low input bias current of only ±200 fA at room temperature. The wide supply voltage range of 2.7V to 12V over the extensive temperature range of −40°C to 125°C makes the LMP7701/LMP7702/LMP7704 excellent choices for low voltage precision applications with extensive temperature requirements. The LMP7701/LMP7702/LMP7704 have only ±37 μV of typical input referred offset voltage and this offset is specified to be less than ±500 μV for the single and ±520 μV for the dual and quad, over temperature. This minimal offset voltage allows more accurate signal detection and amplification in precision applications. The low input bias current of only ±200 fA along with the low input referred voltage noise of 9 nV/√Hz gives the LMP7701/LMP7702/LMP7704 superiority for use in sensor applications. Lower levels of noise from the LMP7701/LMP7702/LMP7704 mean of better signal fidelity and a higher signal-to-noise ratio. Texas Instruments is heavily committed to precision amplifiers and the market segment they serve. Technical support and extensive characterization data is available for sensitive applications or applications with a constrained error budget. The LMP7701 is offered in the space saving 5-Pin SOT-23 and 8-Pin SOIC package. The LMP7702 comes in the 8-Pin SOIC and 8-Pin VSSOP package. The LMP7704 is offered in the 14-Pin SOIC and 14-Pin TSSOP package. These small packages are ideal solutions for area constrained PC boards and portable electronics. CAPACITIVE LOAD The LMP7701/LMP7702/LMP7704 can each be connected as a non-inverting unity gain follower. This configuration is the most sensitive to capacitive loading. The combination of a capacitive load placed on the output of an amplifier along with the amplifier's output impedance creates a phase lag which in turn reduces the phase margin of the amplifier. If the phase margin is significantly reduced, the response will be either underdamped or it will oscillate. In order to drive heavier capacitive loads, an isolation resistor, RISO, in Figure 45 should be used. By using this isolation resistor, the capacitive load is isolated from the amplifier's output, and hence, the pole caused by CL is no longer in the feedback loop. The larger the value of RISO, the more stable the output voltage will be. If values of RISO are sufficiently large, the feedback loop will be stable, independent of the value of CL. However, larger values of RISO result in reduced output swing and reduced output current drive. Figure 45. Isolating Capacitive Load INPUT CAPACITANCE CMOS input stages inherently have low input bias current and higher input referred voltage noise. The LMP7701/LMP7702/LMP7704 enhance this performance by having the low input bias current of only ±200 fA, as well as, a very low input referred voltage noise of 9 nV/√Hz. In order to achieve this a larger input stage has been used. This larger input stage increases the input capacitance of the LMP7701/LMP7702/ LMP7704. The typical value of this input capacitance, CIN, for the LMP7701/LMP7702/LMP7704 is 25 pF. The input capacitance will interact with other impedances such as gain and feedback resistors, which are seen on the inputs of the 16 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LMP7701 LMP7702 LMP7704 LMP7701, LMP7702, LMP7704 www.ti.com SNOSAI9H – SEPTEMBER 2005 – REVISED MARCH 2013 amplifier, to form a pole. This pole will have little or no effect on the output of the amplifier at low frequencies and DC conditions, but will play a bigger role as the frequency increases. At higher frequencies, the presence of this pole will decrease phase margin and will also cause gain peaking. In order to compensate for the input capacitance, care must be taken in choosing the feedback resistors. In addition to being selective in picking values for the feedback resistor, a capacitor can be added to the feedback path to increase stability. The DC gain of the circuit shown in Figure 46 is simply –R2/R1. CF R2 R1 - + CIN VIN + + - - AV = - VOUT VIN =- VOUT R2 R1 Figure 46. Compensating for Input Capacitance For the time being, ignore CF. The AC gain of the circuit in Figure 46 can be calculated as follows: -R2/R1 (s) = 1+ s2 s + § A0 R 1 § A0 ¨ ¨C R + R R 2 © 1 © IN 2 § ¨ © VIN § ¨ © VOUT This equation is rearranged to find the location of the two poles: -1 2CIN 1 1 + r R1 R2 §1 1 + ¨ R2 © R1 § ¨ © P1,2 = 2 4 A0CIN - R2 (1) As shown in Equation 1, as values of R1 and R2 are increased, the magnitude of the poles is reduced, which in turn decreases the bandwidth of the amplifier. Whenever possible, it is best to choose smaller feedback resistors. Figure 47 shows the effect of the feedback resistor on the bandwidth of the LMP7701/LMP7702/LMP7704. 2 VS = 5V CF = 0 pF NORMALIZED GAIN (dB) 0 AV = -1 -2 R1 = R2 = 100 k: -4 R1 = R2 = 30 k: -6 R1 = R2 = 10 k: -8 R1 = R2 = 1 k: -10 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 47. Closed Loop Gain vs. Frequency Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LMP7701 LMP7702 LMP7704 Submit Documentation Feedback 17 LMP7701, LMP7702, LMP7704 SNOSAI9H – SEPTEMBER 2005 – REVISED MARCH 2013 www.ti.com Equation 1 has two poles. In most cases, it is the presence of pairs of poles that causes gain peaking. In order to eliminate this effect, the poles should be placed in Butterworth position, since poles in Butterworth position do not cause gain peaking. To achieve a Butterworth pair, the quantity under the square root in Equation 1 should be set to equal −1. Using this fact and the relation between R1 and R2, R2 = −AV R1, the optimum value for R1 can be found. This is shown in Equation 2. If R1 is chosen to be larger than this optimum value, gain peaking will occur. R1 < (1 - AV) 2 2A0AVCIN (2) In Figure 46, CF is added to compensate for input capacitance and to increase stability. Additionally, CF reduces or eliminates the gain peaking that can be caused by having a larger feedback resistor. Figure 48 shows how CF reduces gain peaking. 2 CF = 0 pF NORMALIZED GAIN (dB) 0 CF = 1 pF -2 CF = 5 pF -4 CF = 3 pF -6 VS = 5V -8 R1 = R2 = 100 k: AV = -1 -10 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 48. Closed Loop Gain vs. Frequency with Compensation DIODES BETWEEN THE INPUTS The LMP7701/LMP7702/LMP7704 have a set of anti-parallel diodes between the input pins, as shown in Figure 49. These diodes are present to protect the input stage of the amplifier. At the same time, they limit the amount of differential input voltage that is allowed on the input pins. A differential signal larger than one diode voltage drop might damage the diodes. The differential signal between the inputs needs to be limited to ±300 mV or the input current needs to be limited to ±10 mA. V V D1 ESD IN + + R1 ESD R2 + IN ESD ESD D2 V - - - V Figure 49. Input of LMP7701 18 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LMP7701 LMP7702 LMP7704 LMP7701, LMP7702, LMP7704 www.ti.com SNOSAI9H – SEPTEMBER 2005 – REVISED MARCH 2013 PRECISION CURRENT SOURCE The LMP7701/LMP7702/LMP7704 can each be used as a precision current source in many different applications. Figure 50 shows a typical precision current source. This circuit implements a precision voltage controlled current source. Amplifier A1 is a differential amplifier that uses the voltage drop across RS as the feedback signal. Amplifier A2 is a buffer that eliminates the error current from the load side of the RS resistor that would flow in the feedback resistor if it were connected to the load side of the RS resistor. In general, the circuit is stable as long as the closed loop bandwidth of amplifier A2 is greater then the closed loop bandwidth of amplifier A1. Note that if A1 and A2 are the same type of amplifiers, then the feedback around A1 will reduce its bandwidth compared to A2. R R V1 V + - RS I = (V2 ± V1) A1 RS + V - V + Z LOAD - R R V2 A2 + - V Figure 50. Precision Current Source The equation for output current can be derived as follows: V2R R+R + (V0 ± IRS)R R+R = V1R + R+R V0R R+R Solving for the current I results in the following equation: I= V2 ± V1 RS LOW INPUT VOLTAGE NOISE The LMP7701/LMP7702/LMP7704 have the very low input voltage noise of 9 nV/√Hz. This input voltage noise can be further reduced by placing N amplifiers in parallel as shown in Figure 51. The total voltage noise on the output of this circuit is divided by the square root of the number of amplifiers used in this parallel combination. This is because each individual amplifier acts as an independent noise source, and the average noise of independent sources is the quadrature sum of the independent sources divided by the number of sources. For N identical amplifiers, this means: REDUCED INPUT VOLTAGE NOISE = 1 N en1+en2+ = 1 N Nen = = 1 2 2 2 2 +enN N en N en N Figure 51 shows a schematic of this input voltage noise reduction circuit. Typical resistor values are: RG = 10Ω, RF = 1 kΩ, and RO = 1 kΩ. Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LMP7701 LMP7702 LMP7704 Submit Documentation Feedback 19 LMP7701, LMP7702, LMP7704 SNOSAI9H – SEPTEMBER 2005 – REVISED MARCH 2013 www.ti.com + V + - VIN VOUT - RG RO V RF + V + RG V - RO RF + V + RG V - RO RF + V + RG V - RO RF Figure 51. Noise Reduction Circuit TOTAL NOISE CONTRIBUTION The LMP7701/LMP7702/LMP7704 have very low input bias current, very low input current noise, and very low input voltage noise. As a result, these amplifiers are ideal choices for circuits with high impedance sensor applications. Figure 52 shows the typical input noise of the LMP7701/LMP7702/LMP7704 as a function of source resistance where: en denotes the input referred voltage noise ei is the voltage drop across source resistance due to input referred current noise or ei = RS * in et shows the thermal noise of the source resistance eni shows the total noise on the input. Where: eni = 2 2 2 en + ei + et The input current noise of the LMP7701/LMP7702/LMP7704 is so low that it will not become the dominant factor in the total noise unless source resistance exceeds 300 MΩ, which is an unrealistically high value. As is evident in Figure 52, at lower RS values, total noise is dominated by the amplifier's input voltage noise. Once RS is larger than a few kilo-Ohms, then the dominant noise factor becomes the thermal noise of RS. As mentioned before, the current noise will not be the dominant noise factor for any practical application. 20 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LMP7701 LMP7702 LMP7704 LMP7701, LMP7702, LMP7704 www.ti.com SNOSAI9H – SEPTEMBER 2005 – REVISED MARCH 2013 VOLTAGE NOISE DENSITY (nV/ Hz) 1000 100 eni en 10 et ei 1 0.1 10 100 1k 10k 100k 1M 10M RS (:) Figure 52. Total Input Noise HIGH IMPEDANCE SENSOR INTERFACE Many sensors have high source impedances that may range up to 10 MΩ. The output signal of sensors often needs to be amplified or otherwise conditioned by means of an amplifier. The input bias current of this amplifier can load the sensor's output and cause a voltage drop across the source resistance as shown in Figure 53, where VIN+ = VS – IBIAS*RS The last term, IBIAS*RS, shows the voltage drop across RS. To prevent errors introduced to the system due to this voltage, an op amp with very low input bias current must be used with high impedance sensors. This is to keep the error contribution by IBIAS*RS less than the input voltage noise of the amplifier, so that it will not become the dominant noise factor. SENSOR RS + IB V VIN+ + VS + - - V Figure 53. Noise Due to IBIAS pH electrodes are very high impedance sensors. As their name indicates, they are used to measure the pH of a solution. They usually do this by generating an output voltage which is proportional to the pH of the solution. pH electrodes are calibrated so that they have zero output for a neutral solution, pH = 7, and positive and negative voltages for acidic or alkaline solutions. This means that the output of a pH electrode is bipolar and has to be level shifted to be used in a single supply system. The rate of change of this voltage is usually shown in mV/pH and is different for different pH sensors. Temperature is also an important factor in a pH electrode reading. The output voltage of the senor will change with temperature. Figure 54 shows a typical output voltage spectrum of a pH electrode. Note that the exact values of output voltage will be different for different sensors. In this example, the pH electrode has an output voltage of 59.15 mV/pH at 25°C. Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LMP7701 LMP7702 LMP7704 Submit Documentation Feedback 21 LMP7701, LMP7702, LMP7704 SNOSAI9H – SEPTEMBER 2005 – REVISED MARCH 2013 www.ti.com ACID +414 mV BASE 4 7 10 +177 mV 0 mV -177 mV 2 0 14 pH 12 -414 mV Figure 54. Output Voltage of a pH Electrode The temperature dependence of a typical pH electrode is shown in Figure 55. As is evident, the output voltage changes with changes in temperature. mV 600 10°C (74.04 mV/pH) 500 400 25°C (59.15 mV/pH) 300 200 100 2 4 12 10 8 14 pH 0 -100 1 3 5 7 9 11 13 -200 -300 -400 -500 0°C (54.20 mV/pH) -600 Figure 55. Temperature Dependence of a pH Electrode The schematic shown in Figure 56 is a typical circuit which can be used for pH measurement. The LM35 is a precision integrated circuit temperature sensor. This sensor is differentiated from similar products because it has an output voltage linearly proportional to Celcius measurement, without the need to convert the temperature to Kelvin. The LM35 is used to measure the temperature of the solution and feeds this reading to the Analog to Digital Converter, ADC. This information is used by the ADC to calculate the temperature effects on the pH readings. The LM35 needs to have a resistor, RT in Figure 56, to –V+ in order to be able to read temperatures below 0°C. RT is not needed if temperatures are not expected to go below zero. The output of pH electrodes is usually large enough that it does not require much amplification; however, due to the very high impedance, the output of a pH electrode needs to be buffered before it can go to an ADC. Since most ADCs are operated on single supply, the output of the pH electrode also needs to be level shifted. Amplifier A1 buffers the output of the pH electrode with a moderate gain of +2, while A2 provides the level shifting. VOUT at the output of A2 is given by: VOUT = −2VpH + 1.024V. The LM4140A is a precision, low noise, voltage reference used to provide the level shift needed. The ADC used in this application is the ADC12032 which is a 12-bit, 2 channel converter with multiplexers on the inputs and a serial output. The 12-bit ADC enables users to measure pH with an accuracy of 0.003 of a pH unit. Adequate power supply bypassing and grounding is extremely important for ADCs. Recommended bypass capacitors are shown in Figure 56. It is common to share power supplies between different components in a circuit. To minimize the effects of power supply ripples caused by other components, the op amps need to have bypass capacitors on the supply pins. Using the same value capacitors as those used with the ADC are ideal. The combination of these three values of capacitors ensures that AC noise present on the power supply line is grounded and does not interfere with the amplifiers' signal. 22 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LMP7701 LMP7702 LMP7704 LMP7701, LMP7702, LMP7704 www.ti.com SNOSAI9H – SEPTEMBER 2005 – REVISED MARCH 2013 + V pH ELECTRODE TEMPERATURE 0.01 PF 0.01 PF 0.1 PF 0.1 PF 10 PF 10 PF + 75: V 1 PF + 1 A1 R2 10 k: R1 10 k: - V+ + V VD + V R3 10 k: R4 10 k: VA + CH0 - VOUT A2 CH1 + RT + V VOFFSET = 0.5012V LM35 -V+ 2 3 LM4140A 6 R5 10 k: - ADC12034 V R6 3.3 k: 1,4,7,8 AGND VREFVREF+ DGND pH ELECTRODE Figure 56. pH Measurement Circuit Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LMP7701 LMP7702 LMP7704 Submit Documentation Feedback 23 LMP7701, LMP7702, LMP7704 SNOSAI9H – SEPTEMBER 2005 – REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision G (March 2013) to Revision H • 24 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 23 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LMP7701 LMP7702 LMP7704 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) LMP7701MA/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM LMP77 01MA LMP7701MAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM LMP77 01MA LMP7701MF ACTIVE SOT-23 DBV 5 1000 TBD Call TI Call TI -40 to 125 AC2A LMP7701MF/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AC2A LMP7701MFX ACTIVE SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 AC2A LMP7701MFX/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AC2A LMP7702MA/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM LMP77 02MA LMP7702MAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM LMP77 02MA LMP7702MM ACTIVE VSSOP DGK 8 1000 TBD Call TI Call TI -40 to 125 AA3A LMP7702MM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AA3A LMP7702MMX ACTIVE VSSOP DGK 8 3500 TBD Call TI Call TI -40 to 125 AA3A LMP7702MMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AA3A LMP7704MA/NOPB ACTIVE SOIC D 14 55 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM LMP7704 MA LMP7704MAX/NOPB ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM LMP7704 MA LMP7704MT ACTIVE TSSOP PW 14 94 TBD Call TI Call TI -40 to 125 LMP77 04MT LMP7704MT/NOPB ACTIVE TSSOP PW 14 94 Pb-Free (RoHS) CU SN Level-1-260C-UNLIM -40 to 125 LMP77 04MT LMP7704MTX ACTIVE TSSOP PW 14 2500 TBD Call TI Call TI -40 to 125 LMP77 04MT LMP7704MTX/NOPB ACTIVE TSSOP PW 14 2500 Pb-Free (RoHS) CU SN Level-1-260C-UNLIM -40 to 125 LMP77 04MT Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LMP7701MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMP7701MF SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMP7701MF/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMP7701MFX SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMP7701MFX/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMP7702MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMP7702MM VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMP7702MM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMP7702MMX VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMP7702MMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMP7704MAX/NOPB SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1 LMP7704MTX TSSOP PW 14 2500 330.0 12.4 6.95 8.3 1.6 8.0 12.0 Q1 LMP7704MTX/NOPB TSSOP PW 14 2500 330.0 12.4 6.95 8.3 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMP7701MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMP7701MF SOT-23 DBV 5 1000 210.0 185.0 35.0 LMP7701MF/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LMP7701MFX SOT-23 DBV 5 3000 210.0 185.0 35.0 LMP7701MFX/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LMP7702MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMP7702MM VSSOP DGK 8 1000 210.0 185.0 35.0 LMP7702MM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LMP7702MMX VSSOP DGK 8 3500 367.0 367.0 35.0 LMP7702MMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 LMP7704MAX/NOPB SOIC D 14 2500 367.0 367.0 35.0 LMP7704MTX TSSOP PW 14 2500 367.0 367.0 35.0 LMP7704MTX/NOPB TSSOP PW 14 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2013, Texas Instruments Incorporated