LMV112 www.ti.com SNAS297B – MAY 2005 – REVISED MAY 2013 LMV112 40 MHz Dual Clock Buffer Check for Samples: LMV112 FEATURES DESCRIPTION • The LMV112 is a high speed dual clock buffer designed for portable communications and accurate multi-clock systems. The LMV112 integrates two 40 MHz low noise buffers which optimizes application and out performs large discrete solutions. This device enables superb system operation between the base band and the oscillator signal path while eliminating crosstalk. 1 2 • • • • • • • • • • • (Typical Values are: VSUPPLY = 2.7V and CL = 20 pF, Unless Otherwise Specified.) Small Signal Bandwidth 40 MHz Supply Voltage Range 2.4V to 5V Slew Rate 110 V/μs Total Supply Current 1.6 mA Shutdown Current 59 µA Rail-to-Rail Input and Output Individual Buffer Enable Pins Rapid Ton Technology Crosstalk Rejection Circuitry 8-pin WSON, Pin Access Packaging Temperature Range −40°C to 85°C APPLICATIONS • • • • • 3G Mobile Applications WLAN-WiMAX Modules TD_SCDMA Multi-Mode MP3 and Camera GSM Modules Oscillator Modules Texas Instruments' unique technology and design deliver accuracy, capacitance and load resistance while increasing the drive capability of the device. The low power consumption makes the LMV112 perfect for battery applications. The robust, independent, and flexible buffers are designed to provide the customer with the ability to manage complex clock signals in the latest wireless applications. The buffers deliver 110 V/μs internal slew rate with independent shutdown and duty cycle precision. The patented analog circuit drives capacitive loads beyond 20 pF. Texas Instruments' proven biasing technique has 1V centering, rail-to-rail input/output unity gain, and AC coupled convenient inputs. These integrated cells save space and require no external bias resistors. Texas Instruments' rapid recovery after disable optimizes performance and current consumption. The LMV112 offers individual enable pin controls and since there is no internal ground reference either single or split supply configurations offer additional system flexibility and power choices. The LMV112 is a proven replacement for any discrete circuitry and simplifies board layout while minimizing related parasitic components. The LMV112 is produced in the small WSON package which offers high quality while minimizing its use of PCB space. Texas Instruments' advanced packaging offers direct PCB-IC evaluation via pin access. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005–2013, Texas Instruments Incorporated LMV112 SNAS297B – MAY 2005 – REVISED MAY 2013 www.ti.com TYPICAL APPLICATION VCC Enable EN1 8 IN1 2 VCTCXO 1 7 1 OUT1 LOAD1 Rload 1 nF Cload LMV112 IN2 3 EN2 4 6 2 OUT2 LOAD2 Rload Cload 5 Enable GND Figure 1. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) (2) Supply Voltages (V+– V−) ESD Tolerance 5.5V (3) Human Body 2000V Machine Model 200V −65°C to +150°C Storage Temperature Range Junction Temperature (4) +150°C Soldering Information Infrared or Convection (35 sec.) (1) (2) (3) (4) 235°C Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For specifications and the test conditions, see the Electrical Characteristics Tables. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Human Body Model: 1.5 kΩ in series with 100 pF. Machine Model: 0Ω in series with 200 pF. The maximum power dissipation is a function of TJ(MAX), θJA , and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) − TA) / θJA. All numbers apply for packages soldered directly onto a PC board. OPERATING RATINGS (1) Supply Voltage (V+ – V−) Temperature Range 2.4V to 5.0V (2) (3) Package Thermal Resistance −40°C to +85°C (2) (3) WSON-8 (θJA) (1) (2) (3) 2 217°C/W Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For specifications and the test conditions, see the Electrical Characteristics Tables. The maximum power dissipation is a function of TJ(MAX), θJA , and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) − TA) / θJA. All numbers apply for packages soldered directly onto a PC board. Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA . Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LMV112 LMV112 www.ti.com SNAS297B – MAY 2005 – REVISED MAY 2013 2.7V ELECTRICAL CHARACTERISTICS Unless otherwise specified, all limits are specified for TJ = 25°C, VDD = 2.7V, VSS = 0V, VCM = 1V, Enable1,2 = VDD, CL = 20 pF, RL = 30 kΩ, CCOUPLING = 1 nF. Boldface limits apply at temperature range extremes of operating condition. See (1). Symbol Parameter Conditions Min (2) Typ (3) Max (2) Units Frequency Domain Response SSBW Small Signal Bandwidth VIN = 0.63 VPP; −3 dB 40 MHz FPBW Full Power Bandwidth VIN = 1.6 VPP; −3 dB 28 MHz GFN Gain Flatness < 0.1 dB f > 100 kHz 3.4 MHz Distortion and Noise Performance en Input-Referred Voltage Noise f = 1 MHz 26 nV/√Hz ISOLATION Output to Input f = 1 MHz 91 dB CT Crosstalk Rejection f = 26 MHz, PIN = 0 dBm 54 dB 0.1 VPP Step (10-90%), f = 1 MHz 7 ns 6 ns ns Time Domain Response tr Rise Time tf Fall Time ts Settling Time to 0.1% 1 VPP Step, f = 1 MHz 118 OS Overshoot 0.1 VPP Step, f = 1 MHz 41 % SR Slew Rate VIN = 1.6 VPP, f = 26 MHz 110 V/µs Enable1,2 = VDD ; No Load 1.6 2.0 2.1 mA Enable1,2 = VSS ; No Load 59 72 78 μA (4) Static DC Performance IS Supply Current PSRR Power Supply Rejection Ratio DC (3.0V to 5.0V) ACL Small Signal Voltage Gain VOUT = 0.1 VPP VOS Output Offset Voltage TC VOS Temperature Coefficient Output Offset Voltage (5) ROUT Output Resistance 58 57 68 0.97 0.95 1.01 1.05 1.07 V/V 0.4 16 17 mV dB 4 f = 100 kHz 0.5 f = 26 MHz 140 Enable = VDD 141 Enable = VSS 141 Enable = VDD 2.3 Enable = VSS 2.3 f = 26 MHz, Enable = VDD 10.4 f = 26 MHz, Enable = VSS 10.9 µV/°C Ω Miscellaneous Performance RIN CIN ZIN VO (1) (2) (3) (4) (5) Input Resistance per Buffer Input Capacitance per Buffer Input Impedance Output Swing Positive VIN = VDD Output Swing Negative VIN = VSS 2.65 2.63 kΩ pF kΩ 2.69 10 V 50 65 mV Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA . All limits are specified by testing or statistical analysis. Typical Values represent the most likely parametric norm. Slew rate is the average of the positive and negative slew rate. Average Temperature Coefficient is determined by dividing the changing in a parameter at temperature extremes by the total temperature change. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LMV112 3 LMV112 SNAS297B – MAY 2005 – REVISED MAY 2013 www.ti.com 2.7V ELECTRICAL CHARACTERISTICS (continued) Unless otherwise specified, all limits are specified for TJ = 25°C, VDD = 2.7V, VSS = 0V, VCM = 1V, Enable1,2 = VDD, CL = 20 pF, RL = 30 kΩ, CCOUPLING = 1 nF. Boldface limits apply at temperature range extremes of operating condition. See (1). Symbol ISC Min (2) Typ (3) Sourcing −18 −13 −27 Sinking 20 16 30 Parameter Output Short-Circuit Current Conditions (6) Ven_hmin Enable High Active Minimum Voltage 1.2 Ven_lmax Enable Low Inactive Maximum Voltage 0.6 (6) Max (2) Units mA V Short-Circuit test is a momentary test. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150°C. 5V ELECTRICAL CHARACTERISTICS Unless otherwise specified, all limits are specified for TJ = 25°C, VDD = 5V, VSS = 0V, VCM = 1V, Enable1,2 = VDD, CL = 20 pF, RL = 30 kΩ, CCOUPLING = 1 nF. Boldface limits apply at temperature range extremes of operating condition. See (1). Symbol Parameter Conditions Min (2) Typ (3) Max (2) Units Frequency Domain Response SSBW Small Signal Bandwidth VIN = 0.63 VPP; −3 dB 42 MHz FPBW Full Power Bandwidth VIN = 1.6 VPP; −3 dB 31 MHz GFN Gain Flatness < 0.1 dB f > 100 kHz 4.9 MHz Distortion and Noise Performance en Input-Referred Voltage Noise f = 1 MHz 27 nV/√Hz ISOLATION Output to Input f = 1 MHz 90 dB CT Crosstalk Rejection f = 26 MHz, PIN = 0 dBm 61 dB 0.1 VPP Step (10-90%), f = 1 MHz 7 ns 6 ns Time Domain Response tr Rise Time tf Fall Time ts Settling Time to 0.1% 1 VPP Step, f = 1 MHz 80 ns OS Overshoot 0.1VPP Step, f = 1 MHz 20 % VIN = 1.6 VPP, f = 26 MHz 120 V/µs Enable1,2 = VDD ; No Load 2.5 3.5 3.8 mA Enable1,2 = VSS ; No Load 62 80 89 μA SR Slew Rate (4) Static DC Performance IS Supply Current PSRR Power Supply Rejection Ratio DC (3.0V to 5.0V) ACL Small Signal Voltage Gain VOUT = 0.1 VPP VOS Output Offset Voltage TC VOS Temperature Coefficient Output Offset Voltage (5) ROUT Output Resistance (1) (2) (3) (4) (5) 4 58 57 68 0.99 0.97 1.00 1.01 1.03 V/V 1.3 16 17 mV 3 f = 100 kHz 0.5 f = 26 MHz 118 dB µV/°C Ω Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA . All limits are specified by testing or statistical analysis. Typical Values represent the most likely parametric norm. Slew rate is the average of the positive and negative slew rate. Average Temperature Coefficient is determined by dividing the changing in a parameter at temperature extremes by the total temperature change. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LMV112 LMV112 www.ti.com SNAS297B – MAY 2005 – REVISED MAY 2013 5V ELECTRICAL CHARACTERISTICS (continued) Unless otherwise specified, all limits are specified for TJ = 25°C, VDD = 5V, VSS = 0V, VCM = 1V, Enable1,2 = VDD, CL = 20 pF, RL = 30 kΩ, CCOUPLING = 1 nF. Boldface limits apply at temperature range extremes of operating condition. See (1). Symbol Parameter Conditions Min (2) Typ (3) Max (2) Units Miscellaneous Performance RIN Input Resistance per Buffer CIN Input Capacitance per Buffer ZIN Input Impedance VO ISC Enable = VDD 134 Enable = VSS 134 Enable = VDD 2.0 Enable = VSS 2.0 f = 26 MHz, Enable = VDD 7.2 f = 26 MHz, Enable = VSS 8.0 Output Swing Positive VIN = VDD Output Swing Negative VIN = VSS Output Short-Circuit Current (6) 4.96 4.94 pF kΩ 4.99 10 Sourcing -40 -28 -68 Sinking 70 50 98 Ven_hmin Enable High Active Minimum Voltage 1.2 Ven_lmax Enable Low Inactive Maximum Voltage 0.6 (6) kΩ V 40 55 mV mA V Short-Circuit test is a momentary test. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150°C. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LMV112 5 LMV112 SNAS297B – MAY 2005 – REVISED MAY 2013 www.ti.com BLOCK DIAGRAM ENABLE 1 VDD IN 1 1 OUT 1 IN 2 2 OUT 2 ENABLE 2 VSS Figure 2. PIN DESCRIPTIONS Pin No. Pin Name 1 VDD Voltage supply connection Description 2 IN 1 Input 1 3 IN 2 Input 2 4 ENABLE 2 5 VSS 6 OUT 2 Output 2 7 OUT 1 Output 1 8 ENABLE 1 Enable buffer 2 Ground connection Enable buffer 1 CONNECTION DIAGRAM Top View VDD 1 IN 1 2 8 ENABLE 1 7 OUT 1 DEVICE CODE IN 2 3 6 OUT 2 ENABLE 2 4 5 VSS Figure 3. 8-Pin WSON (NGQ Package) 6 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LMV112 LMV112 www.ti.com SNAS297B – MAY 2005 – REVISED MAY 2013 TYPICAL PERFORMANCE CHARACTERISTICS TJ = 25°C, VDD = 2.7V, VSS = 0V, Enable1,2 = VDD, CL = 20 pF, RL = 30 kΩ and CCOUPLING = 1 nF, unless otherwise specified. Frequency Response Phase Response Figure 4. Figure 5. Frequency Response Over Temperature Frequency Response Over Temperature Figure 6. Figure 7. Phase Response Over Temperature Phase Response Over Temperature Figure 8. Figure 9. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LMV112 7 LMV112 SNAS297B – MAY 2005 – REVISED MAY 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) TJ = 25°C, VDD = 2.7V, VSS = 0V, Enable1,2 = VDD, CL = 20 pF, RL = 30 kΩ and CCOUPLING = 1 nF, unless otherwise specified. Full Power Bandwidth Gain Flatness 0.1 dB (GFN) Figure 10. Figure 11. Voltage Noise Isolation Output to Input vs. Frequency 180 VOLTAGE NOISE (nV/ Hz) 160 140 2.7V 120 100 80 60 5.0V 40 20 0 100 1k 10k 100k 1M FREQUENCY (Hz) 8 Figure 12. Figure 13. Crosstalk Rejection vs. Frequency Transient Response Positive Figure 14. Figure 15. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LMV112 LMV112 www.ti.com SNAS297B – MAY 2005 – REVISED MAY 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) TJ = 25°C, VDD = 2.7V, VSS = 0V, Enable1,2 = VDD, CL = 20 pF, RL = 30 kΩ and CCOUPLING = 1 nF, unless otherwise specified. Transient Response Negative Small Signal Pulse Response Figure 16. Figure 17. Small Signal Pulse Response Large Signal Pulse Response Figure 18. Figure 19. Large Signal Pulse Response ISUPPLY vs. VSUPPLY Figure 20. Figure 21. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LMV112 9 LMV112 SNAS297B – MAY 2005 – REVISED MAY 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) TJ = 25°C, VDD = 2.7V, VSS = 0V, Enable1,2 = VDD, CL = 20 pF, RL = 30 kΩ and CCOUPLING = 1 nF, unless otherwise specified. 10 ISUPPLY vs. VSUPPLY ISUPPLY vs. VSUPPLY Figure 22. Figure 23. PSRR vs. Frequency VOS vs. VSUPPLY Figure 24. Figure 25. ROUT vs. Frequency Input Impedance vs. Frequency Figure 26. Figure 27. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LMV112 LMV112 www.ti.com SNAS297B – MAY 2005 – REVISED MAY 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) TJ = 25°C, VDD = 2.7V, VSS = 0V, Enable1,2 = VDD, CL = 20 pF, RL = 30 kΩ and CCOUPLING = 1 nF, unless otherwise specified. VOUT vs. IOUT (Sourcing) VOUT vs. IOUT (Sourcing) Figure 28. Figure 29. VOUT vs. IOUT (Sinking) VOUT vs. IOUT (Sinking) Figure 30. Figure 31. ISC Sourcing vs. VSUPPLY over Temperature ISC Sinking vs. VSUPPLY over Temperature Figure 32. Figure 33. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LMV112 11 LMV112 SNAS297B – MAY 2005 – REVISED MAY 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) TJ = 25°C, VDD = 2.7V, VSS = 0V, Enable1,2 = VDD, CL = 20 pF, RL = 30 kΩ and CCOUPLING = 1 nF, unless otherwise specified. 12 ISUPPLY vs VENABLE ISUPPLY vs VENABLE Figure 34. Figure 35. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LMV112 LMV112 www.ti.com SNAS297B – MAY 2005 – REVISED MAY 2013 APPLICATION INFORMATION GENERAL The LMV112 is designed to minimize the effects of spurious signals from the base band chip to the oscillator. Also the influence of varying load resistance and capacitance to the oscillator is minimized, while the drive capability is increased. The inputs of the LMV112 are internally biased at 1V, making AC coupling possible without external bias resistors. To optimize current consumption, the buffer not in use can be disabled by connecting the enable pin to VSS. The LMV112 has no internal ground reference; therefore, either single or split supply configurations can be used. The LMV112 is an easy replacement for discrete circuitry. It simplifies board layout and minimizes the effect of layout related parasitic components. INPUT CONFIGURATION AC coupling is made possible by biasing the input. A large DC load at the oscillator input could change the load impedance and therefore it’s oscillating frequency. To avoid external resistors the inputs are internally biased. This biasing is set at 1V as depicted in Figure 36. Because this biasing is set at 1V, the maximum amplitude of the AC signal is 2 VPP. The coupling capacitance should be large enough to let the AC signal pass. This is a unity gain buffer with railto-rail inputs and outputs. VDD ENABLE 1V OSC IN OUT C1 VSS Figure 36. Input Configuration FREQUENCY PULLING Frequency pulling is the frequency variation of an oscillator caused by a varying load. In the typical application, the load of the oscillator is a fixed capacitor (C1) and the input impedance of the buffer. To keep the input impedance as constant as possible, the input is biased at 1V, even when the part is disabled. A simplified schematic of the input configuration is shown in Figure 36. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LMV112 13 LMV112 SNAS297B – MAY 2005 – REVISED MAY 2013 www.ti.com ISOLATION AND CROSSTALK Output to input isolation prevents the clock from being affected by spurious signals generated by the digital blocks at the output buffer. See the characteristic graphic entitled “Isolation Output to Input vs. Frequency” in the TYPICAL PERFORMANCE CHARACTERISTICS section. A block diagram of the isolation is shown in Figure 37. Crosstalk rejection between buffers prevents signals from affecting each other. Figure 37 shows a Base band IC and a Bluetooth module as examples of this. For more information, see the characteristic graphic labeled “Crosstalk Rejection vs. Frequency” in the TYPICAL PERFORMANCE CHARACTERISTICS section. LMV112 Base band IC OUT 1 IN 1 C1 Isolation Crosstalk VCTCXO IN 2 OUT 2 Bluetooth Radio / Camera Figure 37. Isolation Block Diagram DRIVING CAPACITIVE LOADS Each buffer can drive a capacitive load. Be aware that every capacitor directly connected to the output becomes part of the loop of the buffer. In most applications the load consists of the capacitance of copper tracks and the input capacitance of the application blocks. Capacitance reduces the gain/phase margin and increases the instability. It leads to peaking in the frequency response and in extreme situations oscillations can occur. To drive a large capacitive load it is recommended that a series resistor is included between the buffer and the load capacitor. The best value for this isolation resistance is often found by experimentation. The LMV112 datasheet reflects measurements with capacitance loads of 20 pF at the output of the buffers. Most common applications will probably use a lower capacitance load, which will result in lower peaking and significantly greater bandwidth, see Figure 38. Figure 38. Bandwidth and Peaking 14 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LMV112 LMV112 www.ti.com SNAS297B – MAY 2005 – REVISED MAY 2013 LAYOUT DESIGN RECOMMENDATION Careful consideration for circuitry design and PCB layout will eliminate problems and will optimize the performance of the LMV112. It is best to have the same ground plane on the PCB for all power supply lines. This gives a low impedance return path for all decoupling and other ground connections. To ensure a clean supply voltage it is best to place decoupling capacitors close to the LMV112, between VCC and ground. The output of the VCO must be correctly terminated with proper load impedance. Another important issue is the value of the components, which also determines the sensitivity to disturbances. Resistor value's should be but avoid using values that cause a significant increase in power consumption while loading inputs or outputs to heavily. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LMV112 15 LMV112 SNAS297B – MAY 2005 – REVISED MAY 2013 www.ti.com REVISION HISTORY Changes from Revision A (May 2013) to Revision B • 16 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 15 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LMV112 PACKAGE OPTION ADDENDUM www.ti.com 3-May-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) LMV112SD ACTIVE WSON NGQ 8 1000 TBD Call TI Call TI -40 to 85 112SD LMV112SD/NOPB ACTIVE WSON NGQ 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 112SD LMV112SDX ACTIVE WSON NGQ 8 4500 TBD Call TI Call TI -40 to 85 112SD LMV112SDX/NOPB ACTIVE WSON NGQ 8 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 112SD (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. 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Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 3-May-2013 Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 8-May-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LMV112SD WSON NGQ 8 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1 LMV112SD/NOPB WSON NGQ 8 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1 LMV112SDX WSON NGQ 8 4500 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1 LMV112SDX/NOPB WSON NGQ 8 4500 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 8-May-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMV112SD WSON NGQ 8 1000 210.0 185.0 35.0 LMV112SD/NOPB WSON NGQ 8 1000 210.0 185.0 35.0 LMV112SDX WSON NGQ 8 4500 367.0 367.0 35.0 LMV112SDX/NOPB WSON NGQ 8 4500 367.0 367.0 35.0 Pack Materials-Page 2 MECHANICAL DATA NGQ0008A SDA08A (Rev A) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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