TI LPV358M

LPV321, LPV324-N, LPV358-N
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SNOS413D – AUGUST 2000 – REVISED MARCH 2013
LPV321-N Single/LPV358 Dual/LPV324 Quad General Purpose, Low Voltage, Low Power,
Rail-to-Rail Output Operational Amplifiers
Check for Samples: LPV321, LPV324-N, LPV358-N
FEATURES
DESCRIPTION
1
(For V+ = 5V and V− = 0V, Typical Unless
Otherwise Noted)
2
•
•
•
•
•
•
•
•
Ensured 2.7V and 5V Performance
No Crossover Distortion
Space Saving Package
– 5-Pin SC70 2.0x2.1x1.0 mm
Industrial Temperature Range, −40°C to +85°C
Gain-Bandwidth Product, 152 kHz
Low Supply Current
– LPV321-N, 9 μA
– LPV358, 15 μA
– LPV324, 28 μA
Rail-to-Rail Output Swing @ 100 kΩ Load
– V+−3.5 mV
– V−+90 mV
VCM, −0.2V to V+−0.8V
APPLICATIONS
•
•
•
Active Filters
General Purpose Low Voltage Applications
General Purpose Portable Devices
The LPV321-N/358/324 are low power (9 µA per
channel at 5.0V) versions of the LMV321/358/324 op
amps. This is another addition to the LMV321N/358/324 family of commodity op amps.
The LPV321-N/358/324 are the most cost effective
solutions for the applications where low voltage, low
power operation, space saving and low price are
needed. The LPV321-N/358/324 have rail-to-rail
output swing capability and the input common-mode
voltage range includes ground. They all exhibit
excellent speed-power ratio, achieving 5 kHz of
bandwidth with a supply current of only 9 µA.
The LPV321-N is available in space saving 5-Pin
SC70, which is approximately half the size of 5-Pin
SOT-23. The small package saves space on PC
boards, and enables the design of small portable
electronic devices. It also allows the designer to place
the device closer to the signal source to reduce noise
pickup and increase signal integrity.
The chips are built with Texas Instruments's
advanced submicron silicon-gate BiCMOS process.
The LPV321-N/358/324 have bipolar input and output
stages for improved noise performance and higher
output current drive.
Connection Diagram
Top View
Figure 1. 5-Pin SC70 and SOT-23
Packages
See Package Numbers
DCK0005A and DBV0005A
Top View
Top View
Figure 2. 8-Pin SOIC and VSSOP Figure 3. 14-Pin SOIC and TSSOP
Packages
Packages
See Package Numbers D0008A
See Package Numbers D0014A
and DGK0008A
and PW0014A
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2000–2013, Texas Instruments Incorporated
LPV321, LPV324-N, LPV358-N
SNOS413D – AUGUST 2000 – REVISED MARCH 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
ESD Tolerance
(1) (2)
(3)
Human Body Model
LPV324
2000V
LPV358
1500V
LPV321-N
1500V
Machine Model
100V
Differential Input Voltage
±Supply Voltage
Supply Voltage (V+–V −)
5.5V
Output Short Circuit to V +
(4)
Output Short Circuit to V −
(5)
Soldering Information
Infrared or Convection (20 sec)
235°C
Storage Temperature Range
−65°C to 150°C
(6)
150°C
Junction Temp. (TJ, max)
(1)
(2)
(3)
(4)
(5)
(6)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC)Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
Shorting output to V+ will adversely affect reliability.
Shorting output to V− will adversely affect reliability.
The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
Operating Ratings
(1)
Supply Voltage
2.7V to 5V
−40°C to +85°C
Temperature Range
Thermal Resistance (θJA) (2)
(1)
(2)
2
5-Pin SC70
478°C/W
5-Pin SOT-23
265°C/W
8-Pin SOIC
190°C/W
8-Pin VSSOP
235°C/W
14-Pin SOIC
145°C/W
14-Pin TSSOP
155°C/W
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics.
All numbers are typical, and apply for packages soldered directly onto a PC board in still air.
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SNOS413D – AUGUST 2000 – REVISED MARCH 2013
2.7V DC Electrical Characteristics
Unless otherwise specified, all limits specified for TJ = 25°C, V+ = 2.7V, V− = 0V, VCM = 1.0V, VO = V+/2 and R L > 1 MΩ.
Parameter
Test Conditions
Min
(1)
Typ
(2)
(1)
Units
VOS
Input Offset Voltage
TCVOS
Input Offset Voltage Average Drift
IB
Input Bias Current
1.7
50
nA
IOS
Input Offset Current
0.6
40
nA
CMRR
Common Mode Rejection Ratio
0V ≤ VCM ≤ 1.7V
50
70
dB
PSRR
Power Supply Rejection Ratio
2.7V ≤ V+ ≤ 5V
VO = 1V, VCM = 1V
50
65
dB
VCM
Input Common-Mode Voltage
Range
For CMRR ≥ 50 dB
0
−0.2
Output Swing
RL = 100 kΩ to 1.35V
VO
1.2
Max
1.9
(1)
(2)
Supply Current
mV
µV/°C
V+ −100
V
1.7
V+ −3
80
IS
7
2
mV
180
LPV321-N
4
8
LPV358
Both Amplifiers
8
16
LPV324
All Four Amplifiers
16
µA
24
All limits are specified by testing or statistical analysis.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
2.7V AC Electrical Characteristics
Unless otherwise specified, all limits specified for TJ = 25°C, V+ = 2.7V, V− = 0V, VCM = 1.0V, VO = V+/2 and R L > 1 MΩ.
Parameter
Test Conditions
Min
(1)
(2)
Max
(1)
Units
GBWP
Gain-Bandwidth Product
112
kHz
Φm
Phase Margin
97
Deg
Gm
Gain Margin
35
dB
en
Input-Referred Voltage Noise
f = 1 kHz
178
nV/√Hz
in
Input-Referred Current Noise
f = 1 kHz
0.50
pA/√Hz
(1)
(2)
CL = 22 pF
Typ
All limits are specified by testing or statistical analysis.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
5V DC Electrical Characteristics
Unless otherwise specified, all limits specified for TJ = 25°C, V+ = 5V, V− = 0V, VCM = 2.0V, VO = V+/2 and R L > 1 MΩ.
Boldface limits apply at the temperature extremes.
Parameter
Test Conditions
Min
(1)
Typ
(2)
(1)
Units
VOS
Input Offset Voltage
TCVOS
Input Offset Voltage Average Drift
2
IB
Input Bias Current
2
50
60
nA
IOS
Input Offset Current
0.6
40
50
nA
CMRR
Common Mode Rejection Ratio
(1)
(2)
1.5
Max
0V ≤ VCM ≤ 4V
50
7
10
mV
µV/°C
71
dB
All limits are specified by testing or statistical analysis.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
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5V DC Electrical Characteristics (continued)
Unless otherwise specified, all limits specified for TJ = 25°C, V+ = 5V, V− = 0V, VCM = 2.0V, VO = V+/2 and R L > 1 MΩ.
Boldface limits apply at the temperature extremes.
Parameter
Test Conditions
+
Min
(1)
Typ
(2)
PSRR
Power Supply Rejection Ratio
2.7V ≤ V ≤ 5V
VO = 1V, VCM = 1V
50
65
VCM
Input Common-Mode Voltage
Range
For CMRR ≥ 50 dB
0
−0.2
Large Signal Voltage Gain
RL = 100 kΩ
AV
VO
Output Swing
RL = 100 kΩ to 2.5V
15
10
V+
+
−100
V −200
Output Short Circuit Current
Sourcing
LPV324, LPV358, and LPV321-N
VO = 0V
Output Short Circuit Current Sinking LPV321-N
VO = 5V
LPV324 and LPV358
VO = 5V
IS
(3)
Supply Current
Units
V
4
100
V/mV
+
V −3.5
90
IO
(1)
dB
4.2
(3)
Max
2
16
20
60
11
16
180
220
mV
mA
LPV321-N
9
12
15
LPV358
Both amplifiers
15
20
24
LPV324
All four amplifiers
28
42
46
µA
RL is connected to V -. The output voltage is 0.5V ≤ VO ≤ 4.5V.
5V AC Electrical Characteristics
Unless otherwise specified, all limits specified for TJ = 25°C, V+ = 5V, V− = 0V, VCM = 2.0V, VO = V+/2 and R L > 1MΩ.
Boldface limits apply at the temperature extremes.
Parameter
SR
Slew Rate
GBWP
Gain-Bandwidth Product
Φm
Gm
en
Input-Referred Voltage Noise
in
Input-Referred Current Noise
(1)
(2)
(3)
4
Test Conditions
Min
(1)
(3)
Typ
(2)
Min
(1)
Units
0.1
V/µs
152
kHz
Phase Margin
87
Deg
Gain Margin
19
dB
f = 1 kHz,
146
nV/√Hz
f = 1 kHz
0.30
pA/√Hz
CL = 22 pF
All limits are specified by testing or statistical analysis.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
Connected as voltage follower with 3V step input. Number specified is the slower of the positive and negative slew rates.
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SNOS413D – AUGUST 2000 – REVISED MARCH 2013
Typical Performance Characteristics
Unless otherwise specified, VS = +5V, single supply, TA = 25°C.
Supply Current
vs.
Supply Voltage (LPV321-N)
Input Current
vs.
Temperature
Figure 4.
Figure 5.
Sourcing Current
vs.
Output Voltage
Sourcing Current
vs.
Output Voltage
Figure 6.
Figure 7.
Sinking Current
vs.
Output Voltage
Sinking Current
vs.
Output Voltage
Figure 8.
Figure 9.
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Typical Performance Characteristics (continued)
Unless otherwise specified, VS = +5V, single supply, TA = 25°C.
6
Output Voltage Swing
vs.
Supply Voltage
Input Voltage Noise
vs.
Frequency
Figure 10.
Figure 11.
Input Current Noise
vs
Frequency
Input Current Noise
vs
Frequency
Figure 12.
Figure 13.
Crosstalk Rejection
vs.
Frequency
PSRR
vs.
Frequency
Figure 14.
Figure 15.
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SNOS413D – AUGUST 2000 – REVISED MARCH 2013
Typical Performance Characteristics (continued)
Unless otherwise specified, VS = +5V, single supply, TA = 25°C.
CMRR
vs.
Frequency
CMRR
vs.
Input Common Mode Voltage
Figure 16.
Figure 17.
CMRR
vs.
Input Common Mode Voltage
ΔVOS
vs.
VCM
Figure 18.
Figure 19.
ΔVOS
vs.
VCM
Input Voltage
vs.
Output Voltage
Figure 20.
Figure 21.
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Typical Performance Characteristics (continued)
Unless otherwise specified, VS = +5V, single supply, TA = 25°C.
8
Input Voltage
vs.
Output Voltage
Open Loop Frequency Response
Figure 22.
Figure 23.
Open Loop Frequency Response
Gain and Phase
vs.
Capacitive Load
Figure 24.
Figure 25.
Gain and Phase
vs.
Capacitive Load
Slew Rate
vs.
Supply Voltage
Figure 26.
Figure 27.
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SNOS413D – AUGUST 2000 – REVISED MARCH 2013
Typical Performance Characteristics (continued)
Unless otherwise specified, VS = +5V, single supply, TA = 25°C.
Non-Inverting Large Signal Pulse Response
Non-Inverting Small Signal Pulse Response
Figure 28.
Figure 29.
Inverting Large Signal Pulse Response
Inverting Small Signal Pulse Response
Figure 30.
Figure 31.
Stability
vs.
Capacitive Load
Stability
vs.
Capacitive Load
Figure 32.
Figure 33.
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Typical Performance Characteristics (continued)
Unless otherwise specified, VS = +5V, single supply, TA = 25°C.
10
Stability
vs.
Capacitive Load
Stability
vs.
Capacitive Load
Figure 34.
Figure 35.
THD
vs.
Frequency
Open Loop Output Impedance
vs
Frequency
Figure 36.
Figure 37.
Short Circuit Current
vs.
Temperature (Sinking)
Short Circuit Current
vs.
Temperature (Sourcing)
Figure 38.
Figure 39.
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SNOS413D – AUGUST 2000 – REVISED MARCH 2013
APPLICATION INFORMATION
Benefits of the LPV321-N/358/324
Size
The small footprints of the LPV321-N/358/324 packages save space on printed circuit boards, and enable the
design of smaller electronic products, such as cellular phones, pagers, or other portable systems. The low profile
of the LPV321-N/358/324 make them possible to use in PCMCIA type III cards.
Signal Integrity
Signals can pick up noise between the signal source and the amplifier. By using a physically smaller amplifier
package, the LPV321-N/358/324 can be placed closer to the signal source, reducing noise pickup and increasing
signal integrity.
Simplified Board Layout
These products help you to avoid using long pc traces in your pc board layout. This means that no additional
components, such as capacitors and resistors, are needed to filter out the unwanted signals due to the
interference between the long pc traces.
Low Supply Current
These devices will help you to maximize battery life. They are ideal for battery powered systems.
Low Supply Voltage
TI provides ensured performance at 2.7V and 5V. These specifications ensure operation throughout the battery
lifetime.
Rail-to-Rail Output
Rail-to-rail output swing provides maximum possible dynamic range at the output. This is particularly important
when operating on low supply voltages.
Input Includes Ground
Allows direct sensing near GND in single supply operation.
The differential input voltage may be larger than V+ without damaging the device. Protection should be provided
to prevent the input voltages from going negative more than −0.3V (at 25°C). An input clamp diode with a resistor
to the IC input terminal can be used.
Capacitive Load Tolerance
The LPV321-N/358/324 can directly drive 200 pF in unity-gain without oscillation. The unity-gain follower is the
most sensitive configuration to capacitive loading. Direct capacitive loading reduces the phase margin of
amplifiers. The combination of the amplifier's output impedance and the capacitive load induces phase lag. This
results in either an underdamped pulse response or oscillation. To drive a heavier capacitive load, circuit in
Figure 40 can be used.
Figure 40. Indirectly Driving A Capacitive Load Using Resistive Isolation
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In Figure 40, the isolation resistor RISO and the load capacitor CL form a pole to increase stability by adding more
phase margin to the overall system. The desired performance depends on the value of RISO. The bigger the RISO
resistor value, the more stable VOUT will be. Figure 41 is an output waveform of Figure 40 using 100 kΩ for RISO
and 1000 pF for CL.
Figure 41. Pulse Response of the LPV324 Circuit in Figure 40
The circuit in Figure 42 is an improvement to the one in Figure 40 because it provides DC accuracy as well as
AC stability. If there were a load resistor in Figure 40, the output would be voltage divided by RISO and the load
resistor. Instead, in Figure 42, RF provides the DC accuracy by using feed-forward techniques to connect VIN to
RL. Caution is needed in choosing the value of RF due to the input bias current of the LPV321-N/358/324. CF and
RISO serve to counteract the loss of phase margin by feeding the high frequency component of the output signal
back to the amplifier's inverting input, thereby preserving phase margin in the overall feedback loop. Increased
capacitive drive is possible by increasing the value of CF. This in turn will slow down the pulse response.
Figure 42. Indirectly Driving A Capacitive Load with DC Accuracy
Input Bias Current Cancellation
The LPV321-N/358/324 family has a bipolar input stage. The typical input bias current of LPV321-N/358/324 is
1.5 nA with 5V supply. Thus a 100 kΩ input resistor will cause 0.15 mV of error voltage. By balancing the resistor
values at both inverting and non-inverting inputs, the error caused by the amplifier's input bias current will be
reduced. The circuit in Figure 43 shows how to cancel the error caused by input bias current.
Figure 43. Cancelling the Error Caused by Input Bias Current
12
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SNOS413D – AUGUST 2000 – REVISED MARCH 2013
Typical Single-Supply Application Circuits
Difference Amplifier
The difference amplifier allows the subtraction of two voltages or, as a special case, the cancellation of a signal
common to two inputs. It is useful as a computational amplifier, in making a differential to single-ended
conversion or in rejecting a common mode signal.
Figure 44. Difference Amplifier
(1)
Instrumentation Circuits
The input impedance of the previous difference amplifier is set by the resistor R1, R2, R3, and R4. To eliminate
the problems of low input impedance, one way is to use a voltage follower ahead of each input as shown in the
following two instrumentation amplifiers.
Three-op-amp Instrumentation Amplifier
The quad LPV324 can be used to build a three-op-amp instrumentation amplifier as shown in Figure 45
Figure 45. Three-op-amp Instrumentation Amplifier
The first stage of this instrumentation amplifier is a differential-input, differential-output amplifier, with two voltage
followers. These two voltage followers assure that the input impedance is over 100 MΩ. The gain of this
instrumentation amplifier is set by the ratio of R2/R1. R3 should equal R1 and R4 equal R2. Matching of R3 to R1
and R4 to R2 affects the CMRR. For good CMRR over temperature, low drift resistors should be used. Making R4
Slightly smaller than R 2 and adding a trim pot equal to twice the difference between R 2 and R4 will allow the
CMRR to be adjusted for optimum.
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Two-op-amp Instrumentation Amplifier
A two-op-amp instrumentation amplifier can also be used to make a high-input-impedance DC differential
amplifier (Figure 46). As in the three-op-amp circuit, this instrumentation amplifier requires precise resistor
matching for good CMRR. R4 should equal to R1 and R3 should equal R2.
Figure 46. Two-op-amp Instrumentation Amplifier
(2)
Single-Supply Inverting Amplifier
There may be cases where the input signal going into the amplifier is negative. Because the amplifier is
operating in single supply voltage, a voltage divider using R3 and R4 is implemented to bias the amplifier so the
input signal is within the input common-common voltage range of the amplifier. The capacitor C1 is placed
between the inverting input and resistor R1 to block the DC signal going into the AC signal source, VIN. The
values of R1 and C1 affect the cutoff frequency,
fc = 1/2π R 1C1
(3)
As a result, the output signal is centered around mid-supply (if the voltage divider provides V+/2 at the noninverting input). The output can swing to both rails, maximizing the signal-to-noise ratio in a low voltage system.
Figure 47. Single-Supply Inverting Amplifier
(4)
Active Filter
Simple Low-Pass Active Filter
The simple low-pass filter is shown in Figure 48. Its low-frequency gain(ω → o) is defined by −R3/R1. This allows
low-frequency gains other than unity to be obtained. The filter has a −20 dB/decade roll-off after its corner
frequency fc. R2 should be chosen equal to the parallel combination of R1 and R3 to minimize errors due to bais
current. The frequency response of the filter is shown in Figure 49
14
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Figure 48. Simple Low-Pass Active Filter
(5)
Figure 49. Frequency Response of Simple Low-pass Active Filter in Figure 9
Note that the single-op-amp active filters are used in to the applications that require low quality factor, Q (≤ 10),
low frequency (≤ 5 kHz), and low gain (≤ 10), or a small value for the product of gain times Q (≤ 100). The op
amp should have an open loop voltage gain at the highest frequency of interest at least 50 times larger than the
gain of the filter at this frequency. In addition, the selected op amp should have a slew rate that meets the
following requirement:
Slew Rate ≥ 0.5 x (ωHV OPP) X 10−6V/µsec
where
•
•
ωH is the highest frequency of interest
VOPP is the output peak-to-peak voltage
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(6)
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REVISION HISTORY
Changes from Revision C (March 2013) to Revision D
•
16
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 15
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PACKAGE OPTION ADDENDUM
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1-Nov-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LPV321M5
NRND
SOT-23
DBV
5
1000
TBD
Call TI
Call TI
-40 to 85
A27A
LPV321M5/NOPB
ACTIVE
SOT-23
DBV
5
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
A27A
LPV321M5X
NRND
SOT-23
DBV
5
3000
TBD
Call TI
Call TI
-40 to 85
A27A
LPV321M5X/NOPB
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
A27A
LPV321M7
NRND
SC70
DCK
5
1000
TBD
Call TI
Call TI
-40 to 85
A19
LPV321M7/NOPB
ACTIVE
SC70
DCK
5
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
A19
LPV321M7X
NRND
SC70
DCK
5
3000
TBD
Call TI
Call TI
-40 to 85
A19
LPV321M7X/NOPB
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
A19
LPV324M/NOPB
ACTIVE
SOIC
D
14
55
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
LPV324M
LPV324MT/NOPB
ACTIVE
TSSOP
PW
14
94
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
LPV324
MT
LPV324MTX
NRND
TSSOP
PW
14
2500
TBD
Call TI
Call TI
-40 to 85
LPV324
MT
LPV324MTX/NOPB
ACTIVE
TSSOP
PW
14
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
LPV324
MT
LPV324MX
NRND
SOIC
D
14
2500
TBD
Call TI
Call TI
-40 to 85
LPV324M
LPV324MX/NOPB
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
LPV324M
LPV358M/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LPV
358M
LPV358MM
NRND
VSSOP
DGK
8
1000
TBD
Call TI
Call TI
-40 to 85
P358
LPV358MM/NOPB
ACTIVE
VSSOP
DGK
8
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
P358
LPV358MMX/NOPB
ACTIVE
VSSOP
DGK
8
3500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
P358
LPV358MX
NRND
SOIC
D
8
2500
TBD
Call TI
Call TI
-40 to 85
LPV
358M
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
1-Nov-2013
Status
(1)
LPV358MX/NOPB
ACTIVE
Package Type Package Pins Package
Drawing
Qty
SOIC
D
8
2500
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
Op Temp (°C)
Device Marking
(4/5)
-40 to 85
LPV
358M
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
LPV321M5
SOT-23
DBV
5
1000
178.0
8.4
LPV321M5/NOPB
SOT-23
DBV
5
1000
178.0
LPV321M5X
SOT-23
DBV
5
3000
178.0
LPV321M5X/NOPB
SOT-23
DBV
5
3000
LPV321M7
SC70
DCK
5
LPV321M7/NOPB
SC70
DCK
LPV321M7X
SC70
DCK
LPV321M7X/NOPB
SC70
W
Pin1
(mm) Quadrant
3.2
3.2
1.4
4.0
8.0
Q3
8.4
3.2
3.2
1.4
4.0
8.0
Q3
8.4
3.2
3.2
1.4
4.0
8.0
Q3
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
1000
178.0
8.4
2.25
2.45
1.2
4.0
8.0
Q3
5
1000
178.0
8.4
2.25
2.45
1.2
4.0
8.0
Q3
5
3000
178.0
8.4
2.25
2.45
1.2
4.0
8.0
Q3
DCK
5
3000
178.0
8.4
2.25
2.45
1.2
4.0
8.0
Q3
LPV324MTX
TSSOP
PW
14
2500
330.0
12.4
6.95
8.3
1.6
8.0
12.0
Q1
LPV324MTX/NOPB
TSSOP
PW
14
2500
330.0
12.4
6.95
8.3
1.6
8.0
12.0
Q1
LPV324MX
SOIC
D
14
2500
330.0
16.4
6.5
9.35
2.3
8.0
16.0
Q1
LPV324MX/NOPB
SOIC
D
14
2500
330.0
16.4
6.5
9.35
2.3
8.0
16.0
Q1
LPV358MM
VSSOP
DGK
8
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LPV358MM/NOPB
VSSOP
DGK
8
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LPV358MMX/NOPB
VSSOP
DGK
8
3500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LPV358MX
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LPV358MX/NOPB
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LPV321M5
SOT-23
DBV
5
1000
210.0
185.0
35.0
LPV321M5/NOPB
SOT-23
DBV
5
1000
210.0
185.0
35.0
LPV321M5X
SOT-23
DBV
5
3000
210.0
185.0
35.0
LPV321M5X/NOPB
SOT-23
DBV
5
3000
210.0
185.0
35.0
LPV321M7
SC70
DCK
5
1000
210.0
185.0
35.0
LPV321M7/NOPB
SC70
DCK
5
1000
210.0
185.0
35.0
LPV321M7X
SC70
DCK
5
3000
210.0
185.0
35.0
LPV321M7X/NOPB
SC70
DCK
5
3000
210.0
185.0
35.0
LPV324MTX
TSSOP
PW
14
2500
367.0
367.0
35.0
LPV324MTX/NOPB
TSSOP
PW
14
2500
367.0
367.0
35.0
LPV324MX
SOIC
D
14
2500
367.0
367.0
35.0
LPV324MX/NOPB
SOIC
D
14
2500
367.0
367.0
35.0
LPV358MM
VSSOP
DGK
8
1000
210.0
185.0
35.0
LPV358MM/NOPB
VSSOP
DGK
8
1000
210.0
185.0
35.0
LPV358MMX/NOPB
VSSOP
DGK
8
3500
367.0
367.0
35.0
LPV358MX
SOIC
D
8
2500
367.0
367.0
35.0
LPV358MX/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
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